coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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580 discussions

New patch to review for coreboot: 174746b lenovo/t530: Apply ME workaround for S3 resume
by Edward O'Callaghan 11 Sep '14

11 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6876 -gerrit commit 174746b445baef5c347c7f32c06ac74b386e126b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Sep 12 03:53:43 2014 +1000 lenovo/t530: Apply ME workaround for S3 resume Upon S3 resume, the machine powers off due to the ME not being awake yet. Change-Id: I0255dd0fa6b4cb3b539e11a69a618c770c44f4b0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/acpi/platform.asl | 4 ++++ src/mainboard/lenovo/t530/dsdt.asl | 1 + 2 files changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index 5466bed..72b9dbf 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -68,6 +68,10 @@ Method(_PTS,1) Method(_WAK,1) { + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 0e7a965..c73f795 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -24,6 +24,7 @@ #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define RP03_IS_EXPRESSCARD 1 +#define EC_LENOVO_H8_ME_WORKAROUND 1 #define HAVE_LCD_SCREEN 1 DefinitionBlock(

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New patch to review for coreboot: 1749207 lenovo/t530: Remove empty mainboard.asl
by Edward O'Callaghan 11 Sep '14

11 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6875 -gerrit commit 1749207a398ed3796e16968bec25139c535ae27e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Sep 12 04:00:44 2014 +1000 lenovo/t530: Remove empty mainboard.asl Change-Id: Iaccaf5246e7ac5da2b51dd915c3f3ef807fc6467 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/acpi/mainboard.asl | 0 src/mainboard/lenovo/t530/dsdt.asl | 1 - 2 files changed, 1 deletion(-) diff --git a/src/mainboard/lenovo/t530/acpi/mainboard.asl b/src/mainboard/lenovo/t530/acpi/mainboard.asl deleted file mode 100644 index e69de29..0000000 diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index d09a451..0e7a965 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -37,7 +37,6 @@ DefinitionBlock( { // Some generic macros #include "acpi/platform.asl" - #include "acpi/mainboard.asl" // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>

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New patch to review for coreboot: 007b7cd panther: update chromeos.c
by Isaac Christensen 11 Sep '14

11 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6874 -gerrit commit 007b7cd66294ccbb44919d272162cb16fe5bed5d Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Thu Sep 11 11:02:29 2014 -0600 panther: update chromeos.c The google mainboards were updated to unconditionally include chromeos.c except for panther. Change-Id: I35bbd56326ee0f94ee542bae28f9c23980e9a9ed Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/panther/Makefile.inc | 4 ++-- src/mainboard/google/panther/chromeos.c | 25 ++++++------------------- 2 files changed, 8 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/panther/Makefile.inc b/src/mainboard/google/panther/Makefile.inc index 7533fcf..2932f4d 100644 --- a/src/mainboard/google/panther/Makefile.inc +++ b/src/mainboard/google/panther/Makefile.inc @@ -17,8 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_CHROMEOS) += chromeos.c -ramstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += chromeos.c +ramstage-y += chromeos.c ramstage-y += lan.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 62165da..b35bf56 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -19,7 +19,7 @@ #include <string.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> +#include <bootmode.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> @@ -32,23 +32,10 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#define GPIO_COUNT 6 -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 - #ifndef __PRE_RAM__ -static void fill_lb_gpio(struct lb_gpio *gpio, int num, - int polarity, const char *name, int force) -{ - memset(gpio, 0, sizeof(*gpio)); - gpio->port = num; - gpio->polarity = polarity; - if (force >= 0) - gpio->value = force; - else if (num >= 0) - gpio->value = get_gpio(num); - strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); -} +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -65,7 +52,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) get_developer_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); } #endif @@ -97,7 +84,7 @@ int get_recovery_mode_switch(void) } #ifdef __PRE_RAM__ -void save_chromeos_gpios(void) +void init_bootmode_straps(void) { u32 flags = 0;

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New patch to review for coreboot: 58255b0 snow/pit: include chromeos.c in romstage
by Isaac Christensen 11 Sep '14

11 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6873 -gerrit commit 58255b0e9234b46a58bd634380aede1e71407a5e Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Thu Sep 11 11:14:15 2014 -0600 snow/pit: include chromeos.c in romstage Change-Id: I0edcb141b9a79fad6b1a629bf77cae656c3d6319 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/pit/Makefile.inc | 1 + src/mainboard/google/snow/Makefile.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/pit/Makefile.inc b/src/mainboard/google/pit/Makefile.inc index 2858743..df9b797 100644 --- a/src/mainboard/google/pit/Makefile.inc +++ b/src/mainboard/google/pit/Makefile.inc @@ -22,6 +22,7 @@ bootblock-y += wakeup.c romstage-y += memory.c romstage-y += romstage.c romstage-y += wakeup.c +romstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += chromeos.c diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 2858743..df9b797 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -22,6 +22,7 @@ bootblock-y += wakeup.c romstage-y += memory.c romstage-y += romstage.c romstage-y += wakeup.c +romstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += chromeos.c

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New patch to review for coreboot: 3e0b0db google mainboards: add missing board_info.txt
by Isaac Christensen 11 Sep '14

11 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6872 -gerrit commit 3e0b0dbf62f24d126fc2cd03b8fc498fe0b76b31 Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Thu Sep 11 11:15:24 2014 -0600 google mainboards: add missing board_info.txt Change-Id: Ibab271cdfde81f161af08e0b8fb6435c29410087 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/board_info.txt | 5 +++++ src/mainboard/google/panther/board_info.txt | 5 +++++ src/mainboard/google/pit/board_info.txt | 7 +++++++ src/mainboard/google/rambi/board_info.txt | 5 +++++ src/mainboard/google/samus/board_info.txt | 5 +++++ 5 files changed, 27 insertions(+) diff --git a/src/mainboard/google/nyan/board_info.txt b/src/mainboard/google/nyan/board_info.txt new file mode 100644 index 0000000..f498046 --- /dev/null +++ b/src/mainboard/google/nyan/board_info.txt @@ -0,0 +1,5 @@ +Category: unclass +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/panther/board_info.txt b/src/mainboard/google/panther/board_info.txt new file mode 100644 index 0000000..f498046 --- /dev/null +++ b/src/mainboard/google/panther/board_info.txt @@ -0,0 +1,5 @@ +Category: unclass +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/pit/board_info.txt b/src/mainboard/google/pit/board_info.txt new file mode 100644 index 0000000..5083498 --- /dev/null +++ b/src/mainboard/google/pit/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Samsung +Board name: ARM Chromebook +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rambi/board_info.txt b/src/mainboard/google/rambi/board_info.txt new file mode 100644 index 0000000..f498046 --- /dev/null +++ b/src/mainboard/google/rambi/board_info.txt @@ -0,0 +1,5 @@ +Category: unclass +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/samus/board_info.txt b/src/mainboard/google/samus/board_info.txt new file mode 100644 index 0000000..f498046 --- /dev/null +++ b/src/mainboard/google/samus/board_info.txt @@ -0,0 +1,5 @@ +Category: unclass +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y

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New patch to review for coreboot: a6a44ca google/panther: add board_info.txt
by Matt DeVillier 11 Sep '14

11 Sep '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6871 -gerrit commit a6a44ca70c68d82a5a8fd58d80febf980c01cea5 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Sep 11 12:06:19 2014 -0500 google/panther: add board_info.txt Change-Id: Iec0397a981c31c8af3def04b8c170884f79a50cc Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/panther/board_info.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/panther/board_info.txt b/src/mainboard/google/panther/board_info.txt new file mode 100644 index 0000000..7dbef2e --- /dev/null +++ b/src/mainboard/google/panther/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Asus +Board name: Chromebox +Category: half +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y

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Patch set updated for coreboot: cdc1a22 payloads/external/SeaBIOS: Allow setting buffers below 0xC0000
by Martin Roth 11 Sep '14

11 Sep '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6364 -gerrit commit cdc1a2285c0616b6a43b716a5439083c0c2fb496 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Jul 25 14:39:05 2014 -0600 payloads/external/SeaBIOS: Allow setting buffers below 0xC0000 Add the option to coreboot to set the SeaBIOS buffers below 0xC0000. This is a requirement on the Intel Rangeley processor because it is designed so that only the processor can write the higher memory areas. This prevents USB and SATA from bus-mastering into the buffers when they're set in the typical 0xE0000 area. This will be set to Y unless defaulted to N by the mainboard or chipset. Push the SeaBIOS buffers down to 0x90000 segment for Mohon Peak Change-Id: I15638605d1c66a2277d4b852796db89978551a34 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- payloads/external/SeaBIOS/Makefile.inc | 3 +++ src/Kconfig | 13 +++++++++++++ src/arch/x86/Makefile.inc | 1 + src/mainboard/intel/mohonpeak/Kconfig | 8 ++++++++ 4 files changed, 25 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 97f9d56..21bc9a7 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -31,6 +31,9 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y) else echo "# CONFIG_DEBUG_SERIAL is not set" >> seabios/.config endif +ifneq ($(CONFIG_SEABIOS_MALLOC_UPPERMEMORY),y) + echo "# CONFIG_MALLOC_UPPERMEMORY is not set" >> $(OUT)/seabios/.config +endif ifneq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) echo "# CONFIG_THREAD_OPTIONROMS is not set" >> seabios/.config endif diff --git a/src/Kconfig b/src/Kconfig index 97a4799..443732a 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -623,6 +623,19 @@ config SEABIOS_THREAD_OPTIONROMS variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option. +config SEABIOS_MALLOC_UPPERMEMORY + bool + default y + depends on PAYLOAD_SEABIOS + help + Use the "Upper Memory Block" area (0xc0000-0xf0000) for internal + "low memory" allocations. If this is not selected, the memory is + instead allocated from the "9-segment" (0x90000-0xa0000). + This is not typically needed, but may be required on some platforms + to allow USB and SATA buffers to be written correctly by the + hardware. In general, if this is desired, the option will be + set to 'N' by the chipset Kconfig. + choice prompt "GRUB2 version" default GRUB2_MASTER diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 036dc1a..aa058c0 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -351,6 +351,7 @@ seabios: CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ CONFIG_TTYS0_BASE=$(CONFIG_TTYS0_BASE) \ + CONFIG_SEABIOS_MALLOC_UPPERMEMORY=$(CONFIG_SEABIOS_MALLOC_UPPERMEMORY) \ OUT=$(abspath $(obj)) IASL="$(IASL)" filo: diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig index edf1fb8..eb97663 100644 --- a/src/mainboard/intel/mohonpeak/Kconfig +++ b/src/mainboard/intel/mohonpeak/Kconfig @@ -96,4 +96,12 @@ config UART_FOR_CONSOLE help The Mohon Peak board uses COM2 (2f8) for the serial console. +config SEABIOS_MALLOC_UPPERMEMORY + bool + default n + help + The Avoton/Rangeley chip does not allow devices to write into the 0xe000 + segment. This means that USB/SATA devices will not work in SeaBIOS unless + we put the SeaBIOS buffer area down in the 0x9000 segment. + endif # BOARD_INTEL_MOHONPEAK

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Patch merged into coreboot/master: 955ca5d mainboard/google/parrot: fix ACPI interrupt storm on lid switch change
by gerrit＠coreboot.org 11 Sep '14

11 Sep '14

the following patch was just integrated into master: commit 955ca5d948519e89573b1508bb85d3b01353ac60 Author: Andrew Litt <ajlitt(a)splunge.net> Date: Tue Sep 9 10:49:19 2014 -0500 mainboard/google/parrot: fix ACPI interrupt storm on lid switch change This fixes the ACPI interrupt storm on Parrot that happens when closing the lid or entering suspend by lid close (seen in /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt trigger level every time the interrupt is received so that it doesn't fire until the next state change. http://askubuntu.com/questions/310196 is a good example of what this is trying to solve. Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234 Signed-off-by: Andrew Litt <ajlitt(a)splunge.net> Reviewed-on: http://review.coreboot.org/6858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/6858 for details. -gerrit

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Patch set updated for coreboot: c8abdea lenovo/t530: Use native raminit over MRC blob
by Edward O'Callaghan 11 Sep '14

11 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6394 -gerrit commit c8abdeafdaadcfee39967086dd2a95d29f37e81e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 14:09:27 2014 +1000 lenovo/t530: Use native raminit over MRC blob We now have Native raminit for both sandy/ivybridge introduced in: 7686a56 sandy/ivybridge: Native raminit. Let us make good use of this support over using the Intel MRC blob to initialise memory. USB RCBA configuration data taken between base of 0x3500 up to 0x3600 from `inteltool -r`. Remark: Note the current port is poorly tested at the moment and I am the sole maintainer, however one less blob invites more interest for better support. More to come hopefully. Change-Id: I41d0ef8303dfd369c5565b823e68a6bee09c44f5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 10 +-- src/mainboard/lenovo/t530/romstage.c | 134 +++++++++++++---------------------- 2 files changed, 54 insertions(+), 90 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 1a68a6f..8e49277 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -3,7 +3,7 @@ if BOARD_LENOVO_T530 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_IVYBRIDGE + select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select SOUTHBRIDGE_INTEL_C216 select EC_LENOVO_PMH7 select EC_LENOVO_H8 @@ -19,8 +19,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE config HAVE_MRC_CACHE - bool - default n + bool + default y config HAVE_IFD_BIN bool @@ -42,10 +42,6 @@ config MMCONF_BASE_ADDRESS hex default 0xf0000000 -config CACHE_ROM_SIZE_OVERRIDE - hex - default 0x800000 - config IRQ_SLOT_COUNT int default 18 diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index abad272..c9ad90d 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -33,7 +33,7 @@ #include <cbmem.h> #include <console/console.h> #include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" +#include "northbridge/intel/sandybridge/raminit_native.h" #include "southbridge/intel/bd82x6x/pch.h" #include "southbridge/intel/bd82x6x/gpio.h" #include <arch/cpu.h> @@ -110,66 +110,57 @@ static void rcba_config(void) RCBA32(BUC) = 0; } +static void init_usb(void) +{ + const u32 rcba_dump[64] = { + /* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57, + /* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b, + /* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153, + /* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, + /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448, + /* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + int i; + /* Activate PMBAR. */ + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + + /* Unlock registers. */ + outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c); + + for (i = 0; i < 64; i++) + write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]); + + pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + + /* Relock registers. */ + outw (0x0000, DEFAULT_PMBASE | 0x003c); +} + + void main(unsigned long bist) { - int boot_mode = 0; - int cbmem_was_initted; + int s3resume = 0; u32 pm1_cnt; u16 pm1_sts; + spd_raw_data spd[4]; if (MCHBAR16(SSKPD) == 0xCAFE) { outb(0x6, 0xcf9); hlt (); } - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - .ddr3lv_support = 0, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb_port_config = { - /* enabled usb oc pin length */ - { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ - { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ - { 1, 3, 0x0080 }, /* P2: dock, OC 3 */ - { 1, 0, 0x0040 }, /* P3: wwan, no OC */ - { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ - { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ - { 0, 0, 0x0000 }, /* P6: Empty */ - { 1, 0, 0x0080 }, /* P7: dock, no OC */ - { 0, 0, 0x0000 }, /* P8: Empty */ - { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ - { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ - { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ - { 1, 0, 0x0040 }, /* P12: wlan, no OC */ - { 1, 0, 0x0080 }, /* P13: webcam, no OC */ - }, - .ddr_refresh_rate_config = 2, /* Force double refresh rate */ - }; - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_START_ROMSTAGE); @@ -195,6 +186,8 @@ void main(unsigned long bist) outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3); outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3); + init_usb(); + /* Initialize console device(s) */ console_init(); @@ -216,7 +209,7 @@ void main(unsigned long bist) if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { if (acpi_s3_resume_allowed()) { printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; + s3resume = 1; /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ @@ -230,31 +223,16 @@ void main(unsigned long bist) /* Enable SPD ROMs and DDR-III DRAM */ enable_smbus(); - /* Prepare USB controller early in S3 resume */ - if (boot_mode == 2) - enable_usb_bar(); - post_code(0x39); post_code(0x3a); - pei_data.boot_mode = boot_mode; timestamp_add_now(TS_BEFORE_INITRAM); - /* MRC.bin has a bug and sometimes halts (instead of reboot?). - */ - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ - outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ - } - - sdram_initialize(&pei_data); + memset (spd, 0, sizeof (spd)); + read_spd (&spd[0], 0x50); + read_spd (&spd[2], 0x51); - if (boot_mode != 2) - { - RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ - } + init_dram_ddr3 (spd, 1, TCK_800MHZ, s3resume); timestamp_add_now(TS_AFTER_INITRAM); post_code(0x3c); @@ -262,13 +240,7 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d); - quick_ram_check(); - post_code(0x3e); - MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_recovery(boot_mode==2); - if (boot_mode!=2) - save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so @@ -278,18 +250,14 @@ void main(unsigned long bist) *(u32 *)CBMEM_BOOT_MODE = 0; *(u32 *)CBMEM_RESUME_BACKUP = 0; - if ((boot_mode == 2) && cbmem_was_initted) { + if (s3resume) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_BOOT_MODE = 2; *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; } /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { - /* Failed S3 resume, reset to come up cleanly */ - outb(0x6, 0xcf9); - hlt(); } else { pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); }

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Patch set updated for coreboot: 396845a lenovo/t530: Use native LVDS gfx init
by Edward O'Callaghan 11 Sep '14

11 Sep '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6395 -gerrit commit 396845a095863ef6b0999c0c2a90da9677eac07b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 29 14:42:26 2014 +1000 lenovo/t530: Use native LVDS gfx init As introduced in: 1783a3c ivybridge: LVDS gfx init. The panel on the T530 is a AUO B156HW01 V.4, 40 pin LVDS (2 ch, 6-bit). Tx parameters derived from datasheet table. Change-Id: I2e3b56a2a3d1ede08a704b839cc11fe6d685cf5b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t530/Kconfig | 6 ++++++ src/mainboard/lenovo/t530/devicetree.cb | 10 ++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 8e49277..c34b647 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -14,6 +14,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select INTEL_INT15 + select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 6a09004..b22d405 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -8,8 +8,14 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms - register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "1" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989

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coreboot-gerrit September 2014