coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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580 discussions

Patch merged into coreboot/master: d518c7a tpm: Clean up I2C TPM driver
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit d518c7a2d7ba839f0480a933a7a7c6d7f797e3bf Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Nov 4 17:38:32 2013 -0800 tpm: Clean up I2C TPM driver Drop a lot of u-boot-isms and share common TIS API between I2C driver and LPC driver. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e Reviewed-on: https://chromium-review.googlesource.com/175670 Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 3fc8515b9dcef66998658e1aa5c020d22509810c) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6855 for details. -gerrit

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Patch merged into coreboot/master: 5c85e66 libpayload: usbhid: Fix typo on descriptor parsing
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 5c85e66b178c4fb4ddc6bcd98d13f43f9ad58792 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 17 14:31:36 2013 -0700 libpayload: usbhid: Fix typo on descriptor parsing Forgot an asterisk and everything goes to hell. Sorry about that. Change-Id: I6b2503ca3ea0f80d4e4e5d8b8c0e986fec5db2c9 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173587 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Commit-Queue: David James <davidjames(a)chromium.org> (cherry picked from commit 2a357560a697b56cc6022a4dd3dda47b33568d83) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6854 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6854 for details. -gerrit

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Patch merged into coreboot/master: 8e7a9e1 libpayload: ehci: Fix byte count in dump_td()
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 8e7a9e1c4e760d8dc6e688b8c3adb9e0f5b40608 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Oct 29 11:31:40 2013 -0700 libpayload: ehci: Fix byte count in dump_td() The dump_td() debug function in the EHCI stack incorrectly masks the amount of transferred bytes on output... the actual field is 15 bits wide (30:16). Let's just use the mask constant we already have for all the other code. Change-Id: I28c6f0ec75cc613e38d53b670645d19bf9ffe1b9 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174986 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 570077da7f16bbe2204b4a80790e4bd8fe1a2bd7) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6853 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6853 for details. -gerrit

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Patch merged into coreboot/master: 587193d samus: GPIO updates for Proto1b
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 587193d4613653d975ff6a3a707596450d0b0120 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 31 11:31:20 2013 -0700 samus: GPIO updates for Proto1b Move NFC_INT to GPIO9 Swap CODEC_INT to GPIO46 and WLAN_DISABLE_L to GPIO42 Swap ACCEL_INT to GPIO45 and PP1800_CODEC_EN to GPIO43 Enable PP1800_CODEC_EN, CODEC_LDOENA, CODEC_RESET_L Old-Change-Id: I5547d34f1b7953808375aa5fe5e0a9640ae7e05e Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175291 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 5bb4bc59e37ee4fe9a0556e08a53402c822e5bd6) samus: Misc fixes from proto1b bringup - NFC interrupt is expected in the kernel as a GPIO now, so set it back to that type - NFC FW update GPIO should be low - Accel/Codec interrupts were still set as GPIO type, they should be set as PIRQ type Old-Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176513 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 75a0944f320c80618f12732a23344ce40010a688) Squashed two small patches for samus. Change-Id: I7ec56191fe2b7f19e470df175ad0bbe320a442f5 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6852 for details. -gerrit

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Patch merged into coreboot/master: 91b30d3 nyan: Add a stub mainboard.
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 91b30d364aaf7d9ca1a189189bfc6666e98553e2 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Sep 26 16:27:55 2013 -0700 nyan: Add a stub mainboard. Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170837 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea) nyan: Add a "special-class" for aggregating BCT files into bct.cfg. The config file which cbootimage processes to create a BCT could come from multiple different files, individually selected based on config options, and/or split up into different files for organizational purposes. This change adds a special-class which collects those files and concatenates them all together in a bct.cfg which can be processed more easily by other parts of the build. While the BCT files themselves are potentially very board specific, for instance ones that hold memory timing information, this bit of code which collects them is not. It has to be in each board file instead of alongside the CPU, however, to ensure that the special class is set up before another Makefile tries to use it. If we end up with lots of Tegra based boards which duplicate this code over and over, we might want to revisit how this works. Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170922 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a) nyan: Add bct files for nyan. There's a config option which selects between the emmc and spi config files depending on what the firmware is intended to boot from. These are copied from the files installed by the tegra-bct-nyan ebuild, except that the spi config file has been modified so that there's only one copy of the BCT and so that it only has one configuration. This is to save space in the final image. Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170923 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0) Squashed three commits required to get nyan building since some patches were out of order. Added a select to the nyan mainboard Kconfig to have a rom size of 1024K to match the saved config on the chromium side. Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6669 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6669 for details. -gerrit

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Patch merged into coreboot/master: 3a92be7 nvidia-cbootimage: integrate into coreboot make
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 3a92be72f868249e6b0ab3853cda4c22bcf81ff2 Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Mon Sep 8 15:28:17 2014 -0600 nvidia-cbootimage: integrate into coreboot make Add rules for building the nvidia-cbootimage utility and add dependencies to the tegra124 platform. Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6851 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6851 for details. -gerrit

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Patch merged into coreboot/master: a447e48 lenovo/t520/acpi/gpe.asl: fix ExpressCard gpe configExpre
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit a447e48453bf95dde41cd7597a2b0890c65bdd43 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sun Sep 7 15:21:31 2014 +0200 lenovo/t520/acpi/gpe.asl: fix ExpressCard gpe configExpre ExpressCard is connected to PCIe port 4. Change-Id: I0cffabd9d9435d24a7e9c178c2f96fb1a9390320 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6850 for details. -gerrit

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Patch merged into coreboot/master: f98e668 lenovo/t520/hda_verb.h: update azalia codec config
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit f98e66825b72dab5face6b771fa0d93e5bf49028 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Sep 6 18:03:05 2014 +0200 lenovo/t520/hda_verb.h: update azalia codec config Replace codec config copied form T530 with dumped values from T520 /sys/class/sound/card0/hdaudioC0D0/init_pin_configs. Intel Azalia HDMI is always enabled, but DP isn't connected to a connector. Change-Id: Iabdae4a6669ff429d5769a1bb0c0fb1abc12ba82 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6849 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6849 for details. -gerrit

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Patch merged into coreboot/master: 1bcb407 lenovo/t520/gpio.h: Fix current gpio configuration
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 1bcb4078f92ee33de63e8f99d88e33d1842cea51 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Sat Sep 6 14:09:52 2014 +0200 lenovo/t520/gpio.h: Fix current gpio configuration Change-Id: I67f321583211efd9ed917276cc3989c6dc4ac649 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/6848 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6848 for details. -gerrit

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New patch to review for coreboot: 2f517cc tegra: Reorder GPIO register accesses to avoid glitching
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6868 -gerrit commit 2f517ccb7b2cd51b1bab0811ae97ab1a4306e183 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Oct 10 19:20:06 2013 -0700 tegra: Reorder GPIO register accesses to avoid glitching This patch changes the order of GPIO and pinmux register accesses when setting GPIOs to make the operations as atomic as possible, and avoid output-to-output as well as special-function-to-input glitches under some circumstances. It also sets the TRISTATE pinmux for input GPIOs, since according to my understanding of the pinmux circuit this is the right thing to do. Also changed all uintXX_t types to uXX, since I think we agreed on preferring that for all new code. Old-Change-Id: I2e0156fbaa85e46e460b4494765a06e19f50d4e4 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172730 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write The GPIO wrappers are already pretty nice, but you still end up writing everything twice since you need to specify the pinmux register: gpio_output(GPIO_Q2, PINMUX_GPIO_Q2, 1); Calculating the pinmux index from the GPIO isn't easy, but luckily the enums use a similar naming scheme. This patch changes the wrapper functions to macros that generate the corresponding pinmux name automatically. Old-Change-Id: Id23855c5aec5f87b4201f22bac32503e72f83392 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172731 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments This patch changes the GPIO API once again, this time back to functions. It introduces a new opaque type gpio_t that holds both the GPIO number and the corresponding pinmux number and can be constructed with a macro (e.g. 'gpio_output(GPIO(Q2), 1);' ). This makes the GPIO functions convenient to use, but also allows passing GPIOs around in variables and function parameters. Old-Change-Id: I519c32b872b0c912046a3aaa070ef4e9699856ee Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172916 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) Squashed three gpio related commits for tegra. Change-Id: Ibd3f2134d8473314ebe898ee21a8bf3630a9c8ad Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/nvidia/tegra/gpio.c | 210 ++++++++++++++++++++--------------------- src/soc/nvidia/tegra/gpio.h | 62 ++++++++---- src/soc/nvidia/tegra124/gpio.h | 7 +- 3 files changed, 147 insertions(+), 132 deletions(-) diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index d4b5bdd..0615320 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -26,41 +26,25 @@ #include "gpio.h" #include "pinmux.h" -static void gpio_input_common(int gpio_index, int pinmux_index, - uint32_t pconfig) +void __gpio_input(gpio_t gpio, u32 pull) { - pconfig |= PINMUX_INPUT_ENABLE; - gpio_set_int_enable(gpio_index, 0); - gpio_set_mode(gpio_index, GPIO_MODE_GPIO); - gpio_set_out_enable(gpio_index, 0); - pinmux_set_config(pinmux_index, pconfig); -} - -void gpio_input(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_NONE); -} + u32 pinmux_config = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | pull; -void gpio_input_pullup(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_UP); -} - -void gpio_input_pulldown(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_DOWN); + gpio_set_int_enable(gpio, 0); + gpio_set_out_enable(gpio, 0); + gpio_set_mode(gpio, GPIO_MODE_GPIO); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, pinmux_config); } -void gpio_output(int gpio_index, int pinmux_index, int value) +void gpio_output(gpio_t gpio, int value) { - uint32_t pconfig = PINMUX_PULL_NONE; + /* TODO: Set OPEN_DRAIN based on what pin it is? */ - pinmux_set_config(pinmux_index, pconfig | PINMUX_TRISTATE); - gpio_set_int_enable(gpio_index, 0); - gpio_set_mode(gpio_index, GPIO_MODE_GPIO); - gpio_set_out_enable(gpio_index, 1); - gpio_set_out_value(gpio_index, value); - pinmux_set_config(pinmux_index, pconfig); + gpio_set_int_enable(gpio, 0); + gpio_set_out_value(gpio, value); + gpio_set_out_enable(gpio, 1); + gpio_set_mode(gpio, GPIO_MODE_GPIO); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE); } enum { @@ -74,167 +58,173 @@ enum { struct gpio_bank { // Values - uint32_t config[GPIO_PORTS_PER_BANK]; - uint32_t out_enable[GPIO_PORTS_PER_BANK]; - uint32_t out_value[GPIO_PORTS_PER_BANK]; - uint32_t in_value[GPIO_PORTS_PER_BANK]; - uint32_t int_status[GPIO_PORTS_PER_BANK]; - uint32_t int_enable[GPIO_PORTS_PER_BANK]; - uint32_t int_level[GPIO_PORTS_PER_BANK]; - uint32_t int_clear[GPIO_PORTS_PER_BANK]; + u32 config[GPIO_PORTS_PER_BANK]; + u32 out_enable[GPIO_PORTS_PER_BANK]; + u32 out_value[GPIO_PORTS_PER_BANK]; + u32 in_value[GPIO_PORTS_PER_BANK]; + u32 int_status[GPIO_PORTS_PER_BANK]; + u32 int_enable[GPIO_PORTS_PER_BANK]; + u32 int_level[GPIO_PORTS_PER_BANK]; + u32 int_clear[GPIO_PORTS_PER_BANK]; // Masks - uint32_t config_mask[GPIO_PORTS_PER_BANK]; - uint32_t out_enable_mask[GPIO_PORTS_PER_BANK]; - uint32_t out_value_mask[GPIO_PORTS_PER_BANK]; - uint32_t in_value_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_status_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_enable_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_level_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_clear_mask[GPIO_PORTS_PER_BANK]; + u32 config_mask[GPIO_PORTS_PER_BANK]; + u32 out_enable_mask[GPIO_PORTS_PER_BANK]; + u32 out_value_mask[GPIO_PORTS_PER_BANK]; + u32 in_value_mask[GPIO_PORTS_PER_BANK]; + u32 int_status_mask[GPIO_PORTS_PER_BANK]; + u32 int_enable_mask[GPIO_PORTS_PER_BANK]; + u32 int_level_mask[GPIO_PORTS_PER_BANK]; + u32 int_clear_mask[GPIO_PORTS_PER_BANK]; }; static const struct gpio_bank *gpio_banks = (void *)TEGRA_GPIO_BASE; -static uint32_t gpio_read_port(int index, size_t offset) +static u32 gpio_read_port(int index, size_t offset) { int bank = index / GPIO_GPIOS_PER_BANK; int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; - return read32((uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); + return read32((u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); } -static void gpio_write_port(int index, size_t offset, - uint32_t mask, uint32_t value) +static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) { int bank = index / GPIO_GPIOS_PER_BANK; int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; - uint32_t reg = read32((uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); - uint32_t new_reg = (reg & ~mask) | (value & mask); + u32 reg = read32((u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); + u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - write32(new_reg, (uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); + write32(new_reg, (u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); } } -void gpio_set_mode(int gpio_index, enum gpio_mode mode) +void gpio_set_mode(gpio_t gpio, enum gpio_mode mode) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 1 << bit, mode ? (1 << bit) : 0); } -int gpio_get_mode(int gpio_index) +int gpio_get_mode(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, config)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config)); return (port & (1 << bit)) != 0; } -void gpio_set_lock(int gpio_index) +void gpio_set_lock(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + int bit = gpio % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 1 << bit, 1 << bit); } -int gpio_get_lock(int gpio_index) +int gpio_get_lock(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, config)); + int bit = gpio % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config)); return (port & (1 << bit)) != 0; } -void gpio_set_out_enable(int gpio_index, int enable) +void gpio_set_out_enable(gpio_t gpio, int enable) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_enable), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_enable), 1 << bit, enable ? (1 << bit) : 0); } -int gpio_get_out_enable(int gpio_index) +int gpio_get_out_enable(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, out_enable)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_enable)); return (port & (1 << bit)) != 0; } -void gpio_set_out_value(int gpio_index, int value) +void gpio_set_out_value(gpio_t gpio, int value) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_value), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_value), 1 << bit, value ? (1 << bit) : 0); } -int gpio_get_out_value(int gpio_index) +int gpio_get_out_value(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, out_value)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_value)); return (port & (1 << bit)) != 0; } -int gpio_get_in_value(int gpio_index) +int gpio_get_in_value(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, in_value)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, in_value)); return (port & (1 << bit)) != 0; } -int gpio_get_int_status(int gpio_index) +int gpio_get_int_status(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_status)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_status)); return (port & (1 << bit)) != 0; } -void gpio_set_int_enable(int gpio_index, int enable) +void gpio_set_int_enable(gpio_t gpio, int enable) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_enable), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_enable), 1 << bit, enable ? (1 << bit) : 0); } -int gpio_get_int_enable(int gpio_index) +int gpio_get_int_enable(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_enable)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_enable)); return (port & (1 << bit)) != 0; } -void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta) +void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t value = (high_rise ? (0x000001 << bit) : 0) | + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 value = (high_rise ? (0x000001 << bit) : 0) | (edge ? (0x000100 << bit) : 0) | - (delta ? (0x010000 << bit) : 0); - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + (delta ? (0x010000 << bit) : 0); + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 0x010101 << bit, value); } -void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta) +void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_level)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_level)); *high_rise = ((port & (0x000001 << bit)) != 0); *edge = ((port & (0x000100 << bit)) != 0); *delta = ((port & (0x010000 << bit)) != 0); } -void gpio_set_int_clear(int gpio_index) +void gpio_set_int_clear(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_clear), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_clear), 1 << bit, 1 << bit); } diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index b62dc90..546ea05 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -22,12 +22,34 @@ #include <stdint.h> -/* Higher level functions for common GPIO configurations. */ +#include "pinmux.h" -void gpio_input(int gpio_index, int pinmux_index); -void gpio_input_pullup(int gpio_index, int pinmux_index); -void gpio_input_pulldown(int gpio_index, int pinmux_index); -void gpio_output(int gpio_index, int pinmux_index, int value); +/* Wrapper type for GPIOs. Always use GPIO() macro to generate. */ +typedef u32 gpio_t; + +#define GPIO_PINMUX_SHIFT 16 +#define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \ + (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT))) + +/* Higher level function wrappers for common GPIO configurations. */ + +void gpio_output(gpio_t gpio, int value); +void __gpio_input(gpio_t gpio, u32 pull); + +static inline void gpio_input(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_NONE); +} + +static inline void gpio_input_pulldown(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_DOWN); +} + +static inline void gpio_input_pullup(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_UP); +} /* Functions to modify specific GPIO control values. */ @@ -35,29 +57,29 @@ enum gpio_mode { GPIO_MODE_SPIO = 0, GPIO_MODE_GPIO = 1 }; -void gpio_set_mode(int gpio_index, enum gpio_mode); -int gpio_get_mode(int gpio_index); +void gpio_set_mode(gpio_t gpio, enum gpio_mode); +int gpio_get_mode(gpio_t gpio); // Lock a GPIO with extreme caution since they can't be unlocked. -void gpio_set_lock(int gpio_index); -int gpio_get_lock(int gpio_index); +void gpio_set_lock(gpio_t gpio); +int gpio_get_lock(gpio_t gpio); -void gpio_set_out_enable(int gpio_index, int enable); -int gpio_get_out_enable(int gpio_index); +void gpio_set_out_enable(gpio_t gpio, int enable); +int gpio_get_out_enable(gpio_t gpio); -void gpio_set_out_value(int gpio_index, int value); -int gpio_get_out_value(int gpio_index); +void gpio_set_out_value(gpio_t gpio, int value); +int gpio_get_out_value(gpio_t gpio); -int gpio_get_in_value(int gpio_index); +int gpio_get_in_value(gpio_t gpio); -int gpio_get_int_status(int gpio_index); +int gpio_get_int_status(gpio_t gpio); -void gpio_set_int_enable(int gpio_index, int enable); -int gpio_get_int_enable(int gpio_index); +void gpio_set_int_enable(gpio_t gpio, int enable); +int gpio_get_int_enable(gpio_t gpio); -void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta); -void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta); +void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta); +void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta); -void gpio_set_int_clear(int gpio_index); +void gpio_set_int_clear(gpio_t gpio); #endif /* __SOC_NVIDIA_TEGRA_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra124/gpio.h b/src/soc/nvidia/tegra124/gpio.h index 83d727d..f7d1c30 100644 --- a/src/soc/nvidia/tegra124/gpio.h +++ b/src/soc/nvidia/tegra124/gpio.h @@ -23,11 +23,14 @@ #include <soc/nvidia/tegra/gpio.h> #include <stdint.h> +#include "pinmux.h" /* for pinmux constants in GPIO macro */ + /* GPIO index constants. */ #define GPIO_PORT_CONSTANTS(port) \ - GPIO_##port##0, GPIO_##port##1, GPIO_##port##2, GPIO_##port##3, \ - GPIO_##port##4, GPIO_##port##5, GPIO_##port##6, GPIO_##port##7 + GPIO_##port##0_INDEX, GPIO_##port##1_INDEX, GPIO_##port##2_INDEX, \ + GPIO_##port##3_INDEX, GPIO_##port##4_INDEX, GPIO_##port##5_INDEX, \ + GPIO_##port##6_INDEX, GPIO_##port##7_INDEX enum { GPIO_PORT_CONSTANTS(A),

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coreboot-gerrit September 2014