coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: d780f59 amd/cimx: fix sb(8|9)00 NULL type redefine
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit d780f5905df20f1c0c336a90eae56b2ee5611818 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 22:20:01 2014 -0600 amd/cimx: fix sb(8|9)00 NULL type redefine It is inappropriate for chipset code to be redefining types -- especially NULL to a non-pointer type. There's only one non-straight forward change. A condition being checked was '!ptr_type == NULL' (0 as int). That check is actually 'ptr_type != NULL'. Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5088 for details. -gerrit

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Patch merged into coreboot/master: 80d99ae baytrail: add reset support
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 80d99aef700d334f2b59f1f786c1910628ded86d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 20:54:57 2013 -0500 baytrail: add reset support Bay Trail has the following types of resets it supports: - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but with ETR[20] set. While these are documented this support currently provides support for 2nd soft reset as well as cold and warm reset. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted. Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172710 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4878 for details. -gerrit

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Patch merged into coreboot/master: cf672d2 rambi: Add platform GPIO configuration tables
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit cf672d2db07d1fd972d462cd38e5625a69634ffb Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Oct 10 13:41:19 2013 -0700 rambi: Add platform GPIO configuration tables Configure GPIOs according to function on board. TEST=compile only. BUG=chrome-os-partner:22863 Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172657 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4875 for details. -gerrit

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Patch merged into coreboot/master: ac70f50 rambi: Add ncore GPIO config tables
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit ac70f5099b621b472bcfbc30e97c33a15c0154ef Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Oct 9 15:29:46 2013 -0700 rambi: Add ncore GPIO config tables gpncore config tables were previously missing -- add them. Also, make the baytrail GPIO/PAD LUTs easier to read. TEST=Manual. Build + boot on bayleybay. BUG=chrome-os-partner:22865 Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172510 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4874 for details. -gerrit

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Patch merged into coreboot/master: 79ee493 rambi: add per-sku SPD support
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 79ee493ce5ffb9befedc270928fe7b09ef47db56 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 8 15:33:39 2013 -0500 rambi: add per-sku SPD support There are currently 4 SKUs: 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz Add each of the 4 spds to the build, and use the proper parameters to MRC to use the in-memory SPD information. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Noted 1024 bytes of SPD content. Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172280 See http://review.coreboot.org/4872 for details. -gerrit

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Patch merged into coreboot/master: 824845a baytrail: move early init to before mainboard
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 824845a71e21871bc158fce423ee1f839ee50e28 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 8 16:54:18 2013 -0500 baytrail: move early init to before mainboard It's helpful to have a lot of the early init happen before the handoff to mainboard. One example of this need is having the BARs programmed so that the mainboard can read board-specific gpios. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Booted and saw console outout in bayleybay mainboard. Signed-off-by; Aaron Durbin <adurbin(a)chromium.org> Change-Id: I030d7b4f9061ad7501049e8e204ea12255061fbe Reviewed-on: https://chromium-review.googlesource.com/172290 Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4871 for details. -gerrit

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Patch merged into coreboot/master: 53f9748 baytrail: Add functions to peek at GPIO input values
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 53f9748322e978c78b467a9be224af98e427d8e8 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Oct 8 11:31:21 2013 -0700 baytrail: Add functions to peek at GPIO input values - Add functions to peek at GPIO input pad values (need to be used from romstage for board ram_id GPIOs) - Modify UART GPIOs to use existing fn-assignment function TEST=Manual. Add debug print and verify that GPIO functions return input values. Also, verify UART still functions in romstage. BUG=chrome-os-partner:22865 Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172189 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4870 for details. -gerrit

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Patch merged into coreboot/master: ea43d74 baytrail: set max frequency early in romstage
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit ea43d74fc24edc00a0151ea7201a00fc59fce879 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 7 17:12:20 2013 -0500 baytrail: set max frequency early in romstage Set the BSP to operate at max frequency early in romstage. The call to punit_init() is when the frequency actually ramps as that makes the punit actually start working. BUG=chrome-os-partner:22857 BRANCH=None TEST=Built and booted. Noted operating frequency status is max. Change-Id: Icfd9e5c7682aa21fc740bd687607ca6a66597d5e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172131 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4869 for details. -gerrit

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Patch merged into coreboot/master: 0ed3ab7 baytrail: adjust cache policy during romstage
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 0ed3ab7d8619eb3fb0fe61d3990f2d2a91f3b00b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 7 16:24:44 2013 -0500 baytrail: adjust cache policy during romstage The caching policy for romstage was previously using a 32KiB of cache-as-ram for both the MRC wrapper and the romstage stack/data. It also used a 32KiB code cache region. The BWG's limitations for the code and data region before memory is up was wrong. It consists of a 16-way set associative 1MiB cache. As long as enough addresses are not read there isn't a risk of evicting the data/stack. Now create a 64KiB cache-as-ram region split evenly between romstage and the MRC wrapper. Additionally cache the memory just below 4GiB in CBFS size. This will cover any code and read-only data needed. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted quickly with corresponding changes to MRC warpper. CQ-DEPEND=CL:*146175 Change-Id: I021cecb886a9c0622005edc389136d22905d4520 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172150 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4868 for details. -gerrit

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Patch merged into coreboot/master: 50285b8 baytrail: add punit access functions
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 50285b862ea931e97d22ecdd9f0523b6402f0f43 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 15:23:31 2013 -0500 baytrail: add punit access functions Like the bunit and dunit, add the punit accessor functions. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built. Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171931 See http://review.coreboot.org/4867 for details. -gerrit

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coreboot-gerrit February 2014