coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch merged into coreboot/master: 80c1ecc lenovo/x201: Move mainboard init to mainboard_init.
by gerrit＠coreboot.org 01 Mar '14

01 Mar '14

the following patch was just integrated into master: commit 80c1ecc6bdacd18967d88f5eb1c7ab97b2cdf334 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jan 28 00:05:29 2014 +0100 lenovo/x201: Move mainboard init to mainboard_init. Rather than having it inside mainboard_enable. Change-Id: Ie8bd25eb49b919b4e25c4628e3557fc66b2ba4d9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4840 for details. -gerrit

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New patch to review for coreboot: 6dad95c lib/selfboot: s_srcaddr is uninitialized.
by Edward O'Callaghan 28 Feb '14

28 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5314 -gerrit commit 6dad95cd87ecfe03055c49721c877a459da7fd28 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Mar 1 09:27:37 2014 +1100 lib/selfboot: s_srcaddr is uninitialized. s_srcaddr is uninitialized in the BSS section, leading to a garbage valued operand on the LHS of a '<' on line 383. Change-Id: Ie4fec91b09c70fb1d91ad3918ac3f60653fa1d83 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/lib/selfboot.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 222eae2..2d12a2b 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -352,6 +352,7 @@ static int build_self_segment_list( ntohl(segment->mem_len)); new = malloc(sizeof(*new)); new->s_filesz = 0; + new->s_srcaddr = NULL; new->s_dstaddr = ntohll(segment->load_addr); new->s_memsz = ntohl(segment->mem_len); break;

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Patch set updated for coreboot: 44208ea vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility.
by Edward O'Callaghan 28 Feb '14

28 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5277 -gerrit commit 44208ea58ca04c9e2ce434932a8398ea7ab934d6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Feb 21 12:43:07 2014 +1100 vendorcode/amd/agesa/f*: Improve gcccar.inc assembler compatibility. A comparison with a two's complement in gcccar.inc has dubious GAS/AT&T notation. Clang miss-parses 0x-1 as an invalid hexadecimal number. Change-Id: I88baa5c2513f062ff309df05916a3832b9bd9bb1 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f10/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f12/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f15/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 61a8d3e..11f50db 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -827,7 +827,7 @@ fam14_disable_stack_hook_exit: LOCAL node_core_f14_exit - cmp $0x-1, %si # Has node/core already been discovered? + cmp $-1, %si # Has node/core already been discovered? jnz node_core_f14_exit # Br if yes AMD_CPUID $CPUID_MODEL diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index d7da81d..22564cb 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -821,7 +821,7 @@ fam14_disable_stack_hook_exit: LOCAL node_core_f14_exit - cmp $0x-1, %si # Has node/core already been discovered? + cmp $-1, %si # Has node/core already been discovered? jnz node_core_f14_exit # Br if yes AMD_CPUID $CPUID_MODEL diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 7037344..40e0e31 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -835,7 +835,7 @@ fam14_disable_stack_hook_exit: LOCAL node_core_f14_exit - cmp $0x-1, %si # Has node/core already been discovered? + cmp $-1, %si # Has node/core already been discovered? jnz node_core_f14_exit # Br if yes AMD_CPUID $CPUID_MODEL diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index b20c77e..c88709c 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -842,7 +842,7 @@ fam14_disable_stack_hook_exit: LOCAL node_core_f14_exit - cmp $0x-1, %si # Has node/core already been discovered? + cmp $-1, %si # Has node/core already been discovered? jnz node_core_f14_exit # Br if yes AMD_CPUID $CPUID_MODEL diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index c76ad16..d6dd49a 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -875,7 +875,7 @@ fam14_disable_stack_hook_exit: LOCAL node_core_f14_exit - cmp $0x-1, %si # Has node/core already been discovered? + cmp $-1, %si # Has node/core already been discovered? jnz node_core_f14_exit # Br if yes AMD_CPUID $CPUID_MODEL

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Patch set updated for coreboot: 6d53cd9 intel/sandybridge: add PCI IDs for 6-Series PCH
by Christopher Douglass 28 Feb '14

28 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5226 -gerrit commit 6d53cd9d7e25786ed1a4feafc488b4dac5be3ffe Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:52 2014 -0500 intel/sandybridge: add PCI IDs for 6-Series PCH The PCI ids are taken from: Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update – NDA October 2013 CDI / IBP#: 440377 Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- .../intel/sandybridge/report_platform.c | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index cc74841..8230729 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -59,11 +59,36 @@ static void report_cpu_info(void) mode[aes], mode[txt], mode[vt]); } -/* The PCI id name match comes from Intel document 472178 */ static struct { u16 dev_id; const char *dev_name; } pch_table [] = { + /* 6-series PCI ids from + * Intel® 6 Series Chipset and + * Intel® C200 Series Chipset + * Specification Update – NDA + * October 2013 + * CDI / IBP#: 440377 + */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ {0x1E41, "Desktop Sample"}, {0x1E42, "Mobile Sample"}, {0x1E43, "SFF Sample"},

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Patch set updated for coreboot: 62b7ff8 drivers/spi: Add support for adesto SPI flash parts
by Christopher Douglass 28 Feb '14

28 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5225 -gerrit commit 62b7ff8b2aafb2e5cd5dcb5488e43a714ca98d23 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:26 2014 -0500 drivers/spi: Add support for adesto SPI flash parts Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- src/drivers/spi/Kconfig | 8 ++ src/drivers/spi/Makefile.inc | 2 + src/drivers/spi/adesto.c | 197 +++++++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 3 + src/drivers/spi/spi_flash_internal.h | 1 + 5 files changed, 211 insertions(+) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index c5db969..8ce6def 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -102,3 +102,11 @@ config SPI_FLASH_GIGADEVICE help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice. + +config SPI_FLASH_ADESTO + bool + default y + depends on SPI_FLASH + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Adesto Technologies. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 641ad8d..7d36754 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -2,6 +2,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +ramstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c ramstage-$(CONFIG_SPI_FLASH_AMIC) += amic.c ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c @@ -17,6 +18,7 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +smm-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c smm-$(CONFIG_SPI_FLASH_AMIC) += amic.c smm-$(CONFIG_SPI_FLASH_EON) += eon.c smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c new file mode 100644 index 0000000..83be8b8 --- /dev/null +++ b/src/drivers/spi/adesto.c @@ -0,0 +1,197 @@ +/* + * adesto.c + * Driver for Adesto Technologies SPI flash + * Copyright 2014 Orion Technologies, LLC + * Author: Chris Douglass <cdouglass <at> oriontechnologies.com> + * + * based on winbond.c + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* at25dfxx-specific commands */ +#define CMD_AT25DF_WREN 0x06 /* Write Enable */ +#define CMD_AT25DF_WRDI 0x04 /* Write Disable */ +#define CMD_AT25DF_RDSR 0x05 /* Read Status Register */ +#define CMD_AT25DF_WRSR 0x01 /* Write Status Register */ +#define CMD_AT25DF_READ 0x03 /* Read Data Bytes */ +#define CMD_AT25DF_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_AT25DF_PP 0x02 /* Page Program */ +#define CMD_AT25DF_SE 0x20 /* Sector (4K) Erase */ +#define CMD_AT25DF_BE 0xd8 /* Block (64K) Erase */ +#define CMD_AT25DF_CE 0xc7 /* Chip Erase */ +#define CMD_AT25DF_DP 0xb9 /* Deep Power-down */ +#define CMD_AT25DF_RES 0xab /* Release from DP, and Read Signature */ + +struct adesto_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct adesto_spi_flash { + struct spi_flash flash; + const struct adesto_spi_flash_params *params; +}; + +static inline struct adesto_spi_flash * +to_adesto_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct adesto_spi_flash, flash); +} + +static const struct adesto_spi_flash_params adesto_spi_flash_table[] = { + { + .id = 0x4501, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "AT25DF081", + }, + { + .id = 0x4701, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "AT25DF321", + }, + { + .id = 0x4800, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "AT25DF641", + }, +}; + +static int adesto_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct adesto_spi_flash *stm = to_adesto_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_AT25DF_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = spi_flash_cmd(flash->spi, CMD_AT25DF_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: adesto Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "SF: adesto: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int adesto_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_AT25DF_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode) +{ + const struct adesto_spi_flash_params *params; + unsigned page_size; + struct adesto_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(adesto_spi_flash_table); i++) { + params = &adesto_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(adesto_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported adesto ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct adesto_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = adesto_write; + stm->flash.erase = adesto_erase; +#if CONFIG_SPI_FLASH_NO_FAST_READ + stm->flash.read = spi_flash_cmd_read_slow; +#else + stm->flash.read = spi_flash_cmd_read_fast; +#endif + stm->flash.sector_size = (1 << stm->params->l2_page_size) * + stm->params->pages_per_sector; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &stm->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 63093d2..33588d5 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -246,6 +246,9 @@ static struct { #if CONFIG_SPI_FLASH_STMICRO { 0, 0xff, spi_flash_probe_stmicro, }, #endif +#if CONFIG_SPI_FLASH_ADESTO + { 0, 0x1f, spi_flash_probe_adesto, }, +#endif }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index fd5c7a8..e696948 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -81,4 +81,5 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);

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Patch merged into coreboot/master: 6f47f9b drivers/spi: Sort SPI flash files
by gerrit＠coreboot.org 28 Feb '14

28 Feb '14

the following patch was just integrated into master: commit 6f47f9b58c54a6499d9e0b8016e70c12946b5f96 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Tue Feb 18 11:21:02 2014 -0500 drivers/spi: Sort SPI flash files Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> See http://review.coreboot.org/5260 for details. -gerrit

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Patch merged into coreboot/master: 8e4b3c5 util/ifdtool: cleanup some magic numbers
by gerrit＠coreboot.org 28 Feb '14

28 Feb '14

the following patch was just integrated into master: commit 8e4b3c56abf8083f1816b607760f3ad8fdcc7873 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 28 08:54:41 2014 -0500 util/ifdtool: cleanup some magic numbers There are five firmware regions that are (currently) defined. This was assumed throughout the ifdtool code with many literal 4s and 5s. This patch changes them to refer to a new #define NUM_REGIONS. Change-Id: I523d3763942f875025ebc4b9ba8b2ccf1db5b2f5 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> See http://review.coreboot.org/5313 for details. -gerrit

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Patch merged into coreboot/master: 4a26616 util/ifdtool: add option to change flash layout
by gerrit＠coreboot.org 28 Feb '14

28 Feb '14

the following patch was just integrated into master: commit 4a2661620347a6e8deba6ed579f9c4ecf17c3c18 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Thu Feb 27 09:25:19 2014 -0500 util/ifdtool: add option to change flash layout The new option "--newlayout <file>" will read <file> in flashrom's layout format and copy flash regions from the current flash image file to a new flash image file. If a region grows, the padding is added at the beginning of the target region in the new file so that the data is "right-aligned" to the end of the region. If a region shrinks, a warning is given and the tail end of existing data is copied to the target region in the new file. Regions of zero or negative size are ignored. (In the example below 00fff000:00000fff regions are an artifact of the address encoding in the register fields.) Example Usage: Given a flash image for a board with a Sandy Bridge processor and Intel 6-Series chipset in the file vpx7654.bin ifdtool --layout layout.txt vpx7564.bin will yield the file layout.txt: 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd Notice that the "bios" portion extends to the end of the 4MB flash. It may be edited to extend the bios portion to consume to the extent of an 8MB flash. like layout2.txt: 00000000:00000fff fd 00180000:007fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd ifdtool --newlayout layout.txt vpx7654.bin will create a file vpx7654.bin.new that is 8MB. Change-Id: I0e0925a725c40fa44d8c4b6e86552028779d0523 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> See http://review.coreboot.org/5312 for details. -gerrit

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Patch merged into coreboot/master: d6c514c util/ifdtool: add option to dump flashrom layout
by gerrit＠coreboot.org 28 Feb '14

28 Feb '14

the following patch was just integrated into master: commit d6c514c05327e5399e90a95e95d5dbdccd7841d5 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Wed Feb 26 13:30:13 2014 -0500 util/ifdtool: add option to dump flashrom layout Dump the Intel Flash Descriptor map in the format expected by flashrom's "layout" option. Example usage: Given a 4MB flash image vpx7654.bin that was generated by Intel's FITC tool for a 6-Series chipset... ./ifdtool --layout l.txt vpx7654.bin cat l.txt 00000000:00000fff fd 00180000:003fffff bios 00001000:0017ffff me 00fff000:00000fff gbe 00fff000:00000fff pd Change-Id: Ib740178ed6935b5f6e1dba1be674303f9f980429 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> See http://review.coreboot.org/5306 for details. -gerrit

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Patch set updated for coreboot: d2f768b util/board_status/board_status.sh: set its executable flag
by Idwer Vollering 28 Feb '14

28 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5171 -gerrit commit d2f768b6800e8571d50a06f1a78a8501ba3156dc Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 9 10:20:02 2014 +0100 util/board_status/board_status.sh: set its executable flag Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/board_status/board_status.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh old mode 100644 new mode 100755

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coreboot-gerrit February 2014