coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

1 participants
1135 discussions

Patch set updated for coreboot: c7dda32 console: Use single driver entry for UARTs
by Kyösti Mälkki 27 Feb '14

27 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5308 -gerrit commit c7dda322626bc3fb20f7d1d2aaab46cd870f64a6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 10:31:38 2014 +0200 console: Use single driver entry for UARTs UARTs now have unified prototypes and can use a single entry in the list of drivers for ramstage. Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Makefile.inc | 3 +- src/console/uart8250_console.c | 54 --------------------------------- src/console/uart8250mem_console.c | 54 --------------------------------- src/console/uart_console.c | 59 ++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/uart_console.c | 33 +++----------------- src/cpu/samsung/exynos5250/uart.c | 15 +-------- src/cpu/samsung/exynos5420/uart.c | 15 +-------- src/cpu/ti/am335x/uart.c | 25 ++++----------- src/drivers/uart/pl011.c | 15 +++++---- src/include/console/uart.h | 2 ++ 10 files changed, 82 insertions(+), 193 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index f158670..df08e80 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -17,8 +17,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c bootblock-y += console.c bootblock-y += die.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c +ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_CONSOLE_USB) += usbdebug_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c deleted file mode 100644 index 52f59f6..0000000 --- a/src/console/uart8250_console.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -static void ttyS0_init(void) -{ - uart_init(); -} - -static void ttyS0_tx_byte(unsigned char data) -{ - uart_tx_byte(data); -} - -static void ttyS0_tx_flush(void) -{ - uart_tx_flush(); -} - -static unsigned char ttyS0_rx_byte(void) -{ - return uart_rx_byte(); -} - -static int ttyS0_tst_byte(void) -{ - return uart_can_rx_byte(); -} - -static const struct console_driver uart8250_console __console = { - .init = ttyS0_init, - .tx_byte = ttyS0_tx_byte, - .tx_flush = ttyS0_tx_flush, - .rx_byte = ttyS0_rx_byte, - .tst_byte = ttyS0_tst_byte, -}; diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c deleted file mode 100644 index 7e52aed..0000000 --- a/src/console/uart8250mem_console.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -static void uartmem_init(void) -{ - uart_init(); -} - -static void uartmem_tx_byte(unsigned char data) -{ - uart_tx_byte(data); -} - -static void uartmem_tx_flush(void) -{ - uart_tx_flush(); -} - -static unsigned char uartmem_rx_byte(void) -{ - return uart_rx_byte(); -} - -static int uartmem_tst_byte(void) -{ - return uart_can_rx_byte(); -} - -static const struct console_driver uart8250mem_console __console = { - .init = uartmem_init, - .tx_byte = uartmem_tx_byte, - .tx_flush = uartmem_tx_flush, - .rx_byte = uartmem_rx_byte, - .tst_byte = uartmem_tst_byte, -}; diff --git a/src/console/uart_console.c b/src/console/uart_console.c new file mode 100644 index 0000000..e2cd6a8 --- /dev/null +++ b/src/console/uart_console.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/uart.h> + +static void uartmem_init(void) +{ + uart_init(); +} + +static void uartmem_tx_byte(unsigned char data) +{ + uart_tx_byte(data); +} + +static void uartmem_tx_flush(void) +{ + uart_tx_flush(); +} + +static unsigned char uartmem_rx_byte(void) +{ + return uart_rx_byte(); +} + +/* This only relevant with x86 with GDB_STUB enabled.*/ +static int uartmem_tst_byte(void) +{ +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM + return uart_can_rx_byte(); +#else + return 0; +#endif +} + +static const struct console_driver uart_console __console = { + .init = uartmem_init, + .tx_byte = uartmem_tx_byte, + .tx_flush = uartmem_tx_flush, + .rx_byte = uartmem_rx_byte, + .tst_byte = uartmem_tst_byte, +}; diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index af66cb7..aea1189 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -11,7 +11,6 @@ #include <console/uart.h> #include <arch/io.h> -#include <console/console.h> #include <cpu/allwinner/a10/uart.h> static void *get_console_uart_base_addr(void) @@ -44,7 +43,7 @@ unsigned int uart_platform_refclk(void) return 24000000; } -static void a10_uart_init_dev(void) +void uart_init(void) { void *uart_base = get_console_uart_base_addr(); @@ -54,46 +53,24 @@ static void a10_uart_init_dev(void) a10_uart_enable_fifos(uart_base); } -static unsigned char a10_uart_rx_byte(void) +unsigned char uart_rx_byte(void) { return a10_uart_rx_blocking(get_console_uart_base_addr()); } -static void a10_uart_tx_byte(unsigned char data) +void uart_tx_byte(unsigned char data) { a10_uart_tx_blocking(get_console_uart_base_addr(), data); } +#if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { return (uint32_t) get_console_uart_base_addr(); } - -#if !defined(__PRE_RAM__) -static const struct console_driver a10_uart_console __console = { - .init = a10_uart_init_dev, - .tx_byte = a10_uart_tx_byte, - .rx_byte = a10_uart_rx_byte, -}; -#else - -void uart_init(void) -{ - a10_uart_init_dev(); -} - -unsigned char uart_rx_byte(void) -{ - return a10_uart_rx_byte(); -} - -void uart_tx_byte(unsigned char data) -{ - a10_uart_tx_byte(data); -} +#endif void uart_tx_flush(void) { } -#endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index c9d8d25..14d140c 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> /* for __console definition */ #include <console/uart.h> #include <arch/io.h> #include "uart.h" @@ -169,21 +168,11 @@ static void exynos5_uart_tx_flush(void) } #if !defined(__PRE_RAM__) - -static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, - .tx_byte = exynos5_uart_tx_byte, - .tx_flush = exynos5_uart_tx_flush, - .rx_byte = exynos5_uart_rx_byte, -// .tst_byte = exynos5_uart_tst_byte, -}; - uint32_t uartmem_getbaseaddr(void) { return base_port; } - -#else +#endif void uart_init(void) { @@ -204,5 +193,3 @@ void uart_tx_flush(void) { exynos5_uart_tx_flush(); } - -#endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index f9dd268..d05adcd 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> /* for __console definition */ #include <console/uart.h> #include <arch/io.h> #include "uart.h" @@ -159,21 +158,11 @@ static void exynos5_uart_tx_byte(unsigned char data) } #if !defined(__PRE_RAM__) - -static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, - .tx_byte = exynos5_uart_tx_byte, -// .tx_flush = exynos5_uart_tx_flush, - .rx_byte = exynos5_uart_rx_byte, -// .tst_byte = exynos5_uart_tst_byte, -}; - uint32_t uartmem_getbaseaddr(void) { return base_port; } - -#else +#endif void uart_init(void) { @@ -193,5 +182,3 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } - -#endif diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index f6f1a8d..27051ea 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -20,9 +20,6 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> - -#include <console/console.h> /* for __console definition */ - #include <cpu/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) @@ -162,28 +159,18 @@ unsigned int uart_platform_refclk(void) return 48000000; } -static void am335x_uart_init_dev(void) -{ - uint16_t div = (uint16_t) uart_baudrate_divisor( - default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); -} - #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } +#endif -static const struct console_driver exynos5_uart_console __console = { - .init = am335x_uart_init_dev, - .tx_byte = am335x_uart_tx_byte, - .rx_byte = am335x_uart_rx_byte, -}; -#else void uart_init(void) { - am335x_uart_init_dev(); + uint16_t div = (uint16_t) uart_baudrate_divisor( + default_baudrate(), uart_platform_refclk(), 16); + am335x_uart_init(div); } unsigned char uart_rx_byte(void) @@ -196,6 +183,6 @@ void uart_tx_byte(unsigned char data) am335x_uart_tx_byte(data); } -void uart_tx_flush(void) { +void uart_tx_flush(void) +{ } -#endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 376e95c..2202de7 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <console/uart.h> static void pl011_uart_tx_byte(unsigned char data) @@ -25,16 +24,12 @@ static void pl011_uart_tx_byte(unsigned char data) } #if !defined(__PRE_RAM__) - -static const struct console_driver pl011_uart_console __console = { - .tx_byte = pl011_uart_tx_byte, -}; - uint32_t uartmem_getbaseaddr(void) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#else +#endif + void uart_init(void) { } @@ -47,4 +42,8 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } -#endif + +unsigned char uart_rx_byte(void) +{ + return 0; +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 17811ca..f0371a2 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -20,6 +20,8 @@ #ifndef CONSOLE_UART_H #define CONSOLE_UART_H +#include <stdint.h> + /* Return the clock frequency UART uses as reference clock for * baudrate generator. */ unsigned int uart_platform_refclk(void);

1 0

Patch set updated for coreboot: 5eed8cd uart: Prepare to support multiple base addresses
by Kyösti Mälkki 27 Feb '14

27 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5309 -gerrit commit 5eed8cdbb54a839749b0861df2213f4b357bf14e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 24 20:51:30 2014 +0200 uart: Prepare to support multiple base addresses Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 15 ++++++++--- src/cpu/samsung/exynos5250/uart.c | 50 +++++++++++++++++------------------- src/cpu/samsung/exynos5420/uart.c | 44 +++++++++++++++---------------- src/cpu/ti/am335x/uart.c | 30 +++++++++++----------- src/drivers/uart/pl011.c | 13 ++++++---- 5 files changed, 78 insertions(+), 74 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index aea1189..5cc1a66 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -43,9 +43,14 @@ unsigned int uart_platform_refclk(void) return 24000000; } +unsigned int uart_platform_base(int idx) +{ + return (unsigned int)get_console_uart_base_addr(); +} + void uart_init(void) { - void *uart_base = get_console_uart_base_addr(); + void *uart_base = (void *) uart_platform_base(0); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -55,18 +60,20 @@ void uart_init(void) unsigned char uart_rx_byte(void) { - return a10_uart_rx_blocking(get_console_uart_base_addr()); + void *uart_base = (void *) uart_platform_base(0); + return a10_uart_rx_blocking(uart_base); } void uart_tx_byte(unsigned char data) { - a10_uart_tx_blocking(get_console_uart_base_addr(), data); + void *uart_base = (void *) uart_platform_base(0); + a10_uart_tx_blocking(uart_base, data); } #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return (uint32_t) get_console_uart_base_addr(); + return uart_platform_base(0); } #endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 14d140c..82e221d 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - // TODO initialize with correct peripheral id by base_port. exynos_pinmux_uart3(); @@ -102,12 +96,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -130,14 +123,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -147,49 +138,54 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } -static void exynos5_uart_tx_flush(void) +static void exynos5_uart_tx_flush(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - while (readl(&uart->ufstat) & 0x1ff0000); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { - exynos5_uart_tx_flush(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_flush(uart); } diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index d05adcd..e3ae88d 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); @@ -99,12 +93,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -127,14 +120,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -144,41 +135,48 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { + /* Exynos5250 implements this too. */ } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 27051ea..faea640 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -35,10 +35,8 @@ * Initialise the serial port with the given baudrate divisor. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void am335x_uart_init(uint16_t div) +static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) { - struct am335x_uart *uart = (struct am335x_uart *) - CONFIG_CONSOLE_SERIAL_UART_ADDRESS; uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ @@ -131,11 +129,8 @@ static void am335x_uart_init(uint16_t div) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char am335x_uart_rx_byte(void) +static unsigned char am335x_uart_rx_byte(struct am335x_uart *uart) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_RXFIFOE)); return read8(&uart->rhr); @@ -144,11 +139,8 @@ static unsigned char am335x_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void am335x_uart_tx_byte(unsigned char data) +static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_TXFIFOE)); return write8(data, &uart->thr); @@ -159,28 +151,36 @@ unsigned int uart_platform_refclk(void) return 48000000; } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + return uart_platform_base(0); } #endif void uart_init(void) { + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); + am335x_uart_init(uart, div); } unsigned char uart_rx_byte(void) { - return am335x_uart_rx_byte(); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + return am335x_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - am335x_uart_tx_byte(data); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + am335x_uart_tx_byte(uart, data); } void uart_tx_flush(void) diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2202de7..2a37d9d 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -15,12 +15,14 @@ #include <console/uart.h> -static void pl011_uart_tx_byte(unsigned char data) +static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *) CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + *uart_base = (unsigned int)data; +} - *uart0_address = (unsigned int)data; +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } #if !defined(__PRE_RAM__) @@ -36,7 +38,8 @@ void uart_init(void) void uart_tx_byte(unsigned char data) { - pl011_uart_tx_byte(data); + unsigned int *uart_base = (unsigned int *) uart_platform_base(0); + pl011_uart_tx_byte(uart_base, data); } void uart_tx_flush(void)

1 0

Patch set updated for coreboot: 9cc057d console uart: Fill coreboot table entries
by Kyösti Mälkki 27 Feb '14

27 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5310 -gerrit commit 9cc057d9b828d7633c69d2fd036ba7f2e4273f5b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 18 11:54:57 2014 +0200 console uart: Fill coreboot table entries Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 18 ++++++--- src/cpu/samsung/exynos5250/uart.c | 21 ++++++---- src/cpu/samsung/exynos5420/uart.c | 21 ++++++---- src/cpu/ti/am335x/uart.c | 21 ++++++---- src/drivers/oxford/oxpcie/oxpcie_early.c | 12 +++++- src/drivers/uart/pl011.c | 21 ++++++---- src/drivers/uart/uart8250io.c | 22 +++++++++++ src/include/boot/coreboot_tables.h | 4 ++ src/include/console/uart.h | 1 - src/lib/coreboot_table.c | 66 +++++++++----------------------- 10 files changed, 122 insertions(+), 85 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index 5cc1a66..0b80938 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -10,6 +10,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/allwinner/a10/uart.h> @@ -70,14 +71,19 @@ void uart_tx_byte(unsigned char data) a10_uart_tx_blocking(uart_base, data); } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) +void uart_tx_flush(void) { - return uart_platform_base(0); } -#endif -void uart_tx_flush(void) +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) { -} + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 82e221d..5458e7b 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -159,13 +160,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); @@ -189,3 +183,16 @@ void uart_tx_flush(void) struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); exynos5_uart_tx_flush(uart); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index e3ae88d..0928111 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -151,13 +152,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); @@ -180,3 +174,16 @@ void uart_tx_flush(void) { /* Exynos5250 implements this too. */ } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index faea640..be41653 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -20,6 +20,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) @@ -156,13 +157,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); @@ -186,3 +180,16 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d7f473e..7de9da6 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -24,7 +24,9 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <console/uart.h> +#include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; @@ -139,9 +141,15 @@ void oxford_remap(u32 new_base) uart1_base = new_base + 0x2000; } -uint32_t uartmem_getbaseaddr(void) +void uart_fill_lb(void *data) { - return uart_platform_base(0); + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2a37d9d..b652f36 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boot/coreboot_tables.h> #include <console/uart.h> static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) @@ -25,13 +26,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; -} -#endif - void uart_init(void) { } @@ -50,3 +44,16 @@ unsigned char uart_rx_byte(void) { return 0; } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e4e8b6c..1eebb18 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -23,6 +23,10 @@ #include <trace.h> #include "uart8250reg.h" +#ifndef __ROMCC__ +#include <boot/coreboot_tables.h> +#endif + /* Should support 8250, 16450, 16550, 16550A type UARTs */ /* Nominal values only, good for the range of choices Kconfig offers for @@ -102,6 +106,11 @@ static void uart8250_init(unsigned base_port, unsigned divisor) */ static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; +unsigned int uart_platform_base(int idx) +{ + return bases[idx]; +} + void uart_init(void) { unsigned int div; @@ -129,3 +138,16 @@ void uart_tx_flush(void) { uart8250_tx_flush(bases[0]); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); +} +#endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 6243d45..49d7adb 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -348,4 +348,8 @@ struct lb_memory *get_lb_mem(void); void fill_lb_gpios(struct lb_gpios *gpios); +void uart_fill_lb(void *data); +void lb_add_serial(struct lb_serial *serial, void *data); +void lb_add_console(uint16_t consoletype, void *data); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index f0371a2..4516b71 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -46,7 +46,6 @@ unsigned char uart_rx_byte(void); int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); -uint32_t uartmem_getbaseaddr(void); void oxford_init(void); void oxford_remap(unsigned int new_base); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 2d84579..1524cb7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -102,43 +102,22 @@ static struct lb_memory *lb_memory(struct lb_header *header) return mem; } -static struct lb_serial *lb_serial(struct lb_header *header) +void lb_add_serial(struct lb_serial *new_serial, void *data) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; + struct lb_header *header = (struct lb_header *)data; struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; + + serial = (struct lb_serial *)lb_new_record(header); serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif + serial->type = new_serial->type; + serial->baseaddr = new_serial->baseaddr; + serial->baud = new_serial->baud; } -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_SERIAL_UART || CONFIG_CONSOLE_USB -static void add_console(struct lb_header *header, u16 consoletype) +void lb_add_console(uint16_t consoletype, void *data) { + struct lb_header *header = (struct lb_header *)data; struct lb_console *console; console = (struct lb_console *)lb_new_record(header); @@ -146,20 +125,6 @@ static void add_console(struct lb_header *header, u16 consoletype) console->size = sizeof(*console); console->type = consoletype; } -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_USB - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} static void lb_framebuffer(struct lb_header *header) { @@ -522,10 +487,15 @@ unsigned long write_coreboot_table( /* Record our motherboard */ lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); + + /* Record the serial ports and consoles */ +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART + uart_fill_lb(head); +#endif +#if CONFIG_CONSOLE_USB + lb_add_console(LB_TAG_CONSOLE_EHCI, head); +#endif + /* Record our various random string information */ lb_strings(head); /* Record our framebuffer */

1 0

Patch set updated for coreboot: c19d6f2 uart: Redefine Kconfig options
by Kyösti Mälkki 27 Feb '14

27 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5311 -gerrit commit c19d6f240ff8c2e86b073552f99ae724472f5828 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 17:16:22 2014 +0200 uart: Redefine Kconfig options Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 4 +-- src/arch/x86/lib/romcc_console.c | 6 ++--- src/arch/x86/lib/romstage_console.c | 10 ++----- src/console/Kconfig | 43 +++++++++++++----------------- src/console/uart_console.c | 2 +- src/cpu/allwinner/a10/Kconfig | 2 +- src/cpu/allwinner/a10/Makefile.inc | 12 ++++----- src/cpu/samsung/exynos5250/Kconfig | 4 +-- src/cpu/samsung/exynos5250/Makefile.inc | 6 ++--- src/cpu/samsung/exynos5420/Kconfig | 4 +-- src/cpu/samsung/exynos5420/Makefile.inc | 6 ++--- src/cpu/ti/am335x/Makefile.inc | 7 +++-- src/cpu/x86/smm/smiutil.c | 10 ++----- src/drivers/Makefile.inc | 2 +- src/drivers/oxford/oxpcie/Kconfig | 2 +- src/drivers/oxford/oxpcie/Makefile.inc | 2 +- src/drivers/uart/Kconfig | 15 ++++++++--- src/drivers/uart/Makefile.inc | 13 ++++----- src/lib/coreboot_table.c | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/samsung/lumpy/romstage.c | 4 +-- src/mainboard/samsung/stumpy/romstage.c | 4 +-- src/mainboard/ti/beaglebone/Kconfig | 4 +-- src/superio/via/vt1211/vt1211.c | 2 +- 24 files changed, 79 insertions(+), 89 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 93ea38d..7614531 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -28,7 +28,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) @@ -38,7 +38,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif } diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 66c81db..4bd3ad4 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -30,7 +30,7 @@ */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" #include "drivers/uart/uart8250io.c" #endif @@ -40,7 +40,7 @@ static void __console_tx_byte(unsigned char byte) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K @@ -61,7 +61,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 5e7923e..0337245 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -31,10 +31,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) @@ -53,10 +50,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/console/Kconfig b/src/console/Kconfig index bb64f29..9377a78 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -29,37 +29,29 @@ config SQUELCH_EARLY_SMP config CONSOLE_SERIAL bool "Serial port console output" default y + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL help - Send coreboot debug output to a serial port (should be one or more of - CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) + Send coreboot debug output to a serial port. -config CONSOLE_SERIAL8250 - bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_IO_MAPPED - default y - help - Send coreboot debug output to an I/O mapped serial port console. + The type of serial port driver selected based on your configuration is + shown on the following menu line. Supporting multiple different types + of UARTs in one build is not supported. -config CONSOLE_SERIAL8250MEM - bool "Serial port console output (memory mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_MEMORY_MAPPED - help - Send coreboot debug output to a memory mapped serial port console. +if CONSOLE_SERIAL + + comment "I/O mapped, 8250-compatible" + depends on DRIVERS_UART_8250IO -config CONSOLE_SERIAL_UART - bool "Serial port console output (device-specific UART)" - depends on CONSOLE_SERIAL + comment "memory mapped, 8250-compatible" + depends on DRIVERS_UART_8250MEM + + comment "device-specific UART" depends on HAVE_UART_SPECIAL - default y - help - Send coreboot debug output to a device-specific serial port console. choice prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO config CONSOLE_SERIAL_COM1 bool "COM1/ttyS0, I/O port 0x3f8" @@ -82,7 +74,7 @@ endchoice config TTYS0_BASE hex - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO default 0x3f8 if CONSOLE_SERIAL_COM1 default 0x2f8 if CONSOLE_SERIAL_COM2 default 0x3e8 if CONSOLE_SERIAL_COM3 @@ -93,7 +85,6 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" @@ -133,7 +124,9 @@ config TTYS0_BAUD config TTYS0_LCS int default 3 - depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM + +endif # CONSOLE_SERIAL config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/console/uart_console.c b/src/console/uart_console.c index e2cd6a8..f5535d7 100644 --- a/src/console/uart_console.c +++ b/src/console/uart_console.c @@ -43,7 +43,7 @@ static unsigned char uartmem_rx_byte(void) /* This only relevant with x86 with GDB_STUB enabled.*/ static int uartmem_tst_byte(void) { -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_DRIVERS_UART_8250IO || CONFIG_DRIVERS_UART_8250MEM return uart_can_rx_byte(); #else return 0; diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 72e3630..8512c38 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -76,7 +76,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a86d719..716e463 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -4,8 +4,6 @@ bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-y += raminit.c bootblock-y += timer.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c romstage-y += cbmem.c @@ -13,8 +11,6 @@ romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c romstage-y += twi.c -romstage-y += uart.c -romstage-y += uart_console.c ramstage-y += bootblock_media.c ramstage-y += cbmem.c @@ -23,8 +19,12 @@ ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c -ramstage-y += uart.c -ramstage-y += uart_console.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c +romstage-y += uart.c uart_console.c +ramstage-y += uart.c uart_console.c +endif real-target: $(obj)/BOOT0 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 63038c3..9320184 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -91,7 +91,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -117,7 +117,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 6d7ae16..3d5b5b4 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index dd35c35..5f78cc5 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -93,7 +93,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -119,7 +119,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 4169a2e..844b835 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..5b10bd8 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,16 +1,19 @@ bootblock-y += dmtimer.c bootblock-y += bootblock_media.c bootblock-y += pinmux.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c -romstage-y += uart.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c ramstage-y += timer.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +romstage-y += uart.c ramstage-y += uart.c +endif $(call add-class,omap-header) diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 3325c32..6e9822e 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -32,10 +32,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif } @@ -45,10 +42,7 @@ void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL8250 - uart_init(); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #endif diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..148e257 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -30,7 +30,7 @@ subdirs-y += parade subdirs-y += realtek subdirs-y += sil subdirs-y += trident -subdirs-y += uart +subdirs-$(CONFIG_DRIVERS_UART) += uart subdirs-y += usb subdirs-y += ics subdirs-y += spi diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 899a153..5ad42aa 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n - select HAVE_UART_MEMORY_MAPPED + select DRIVERS_UART_8250MEM help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 1922425..5e3e6e5 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_CONSOLE_SERIAL),y) ramstage-y += oxpcie_early.c oxpcie.c romstage-y += oxpcie_early.c endif diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 5c9a9d1..889c69a 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,10 +1,19 @@ -# This should default to N and be set by SuperI/O drivers that have an UART -config HAVE_UART_IO_MAPPED +config DRIVERS_UART bool + default y if CONSOLE_SERIAL + default n + +config DRIVERS_UART_8250IO + bool "Serial port on SuperIO" depends on !ARCH_ARMV7 + default n if NO_UART_ON_SUPERIO default y if ARCH_X86 -config HAVE_UART_MEMORY_MAPPED +# Select this for mainboard without SuperIO serial port. +config NO_UART_ON_SUPERIO + def_bool n + +config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 415c5bb..286bff2 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,28 +1,25 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) romstage-y += util.c ramstage-y += util.c bootblock-y += util.c smm-$(CONFIG_DEBUG_SMI) += util.c -endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +# Add the driver, only one can be enabled. The driver files may +# be located in the soc/ or cpu/ directories instead of here. + +ifeq ($(CONFIG_DRIVERS_UART_8250IO),y) romstage-y += uart8250io.c ramstage-y += uart8250io.c smm-$(CONFIG_DEBUG_SMI) += uart8250io.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_DRIVERS_UART_8250MEM),y) romstage-y += uart8250mem.c ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) - ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c ramstage-y += pl011.c endif - -endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 1524cb7..b9d2f5f 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -489,7 +489,7 @@ unsigned long write_coreboot_table( lb_mainboard(head); /* Record the serial ports and consoles */ -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_fill_lb(head); #endif #if CONFIG_CONSOLE_USB diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index edba627..040ed9c 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -50,7 +50,7 @@ config DRAM_SIZE_MB config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x10009000 # Memory map for qemu vexpress-a9: diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9933459..55c1f0a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/msr.h> #include "option_table.h" #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index e5b55b5..3e27a6a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -62,7 +62,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index df7ebeb..c842a5d 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -64,7 +64,7 @@ config CBFS_HEADER_ROM_OFFSET choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -100,7 +100,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x44e09000 if CONSOLE_SERIAL_UART0 default 0x48022000 if CONSOLE_SERIAL_UART1 default 0x48024000 if CONSOLE_SERIAL_UART2 diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 551f6f0..f7a5cd9 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -117,7 +117,7 @@ static void vt1211_pnp_set_resources(struct device *dev) { struct resource *res; -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) {

1 0

Patch set updated for coreboot: d55a57c gma: Add EDID retrieving functions.
by Vladimir Serbinenko 27 Feb '14

27 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5278 -gerrit commit d55a57cd78b4c39a7f3eaa9ba7693119a7678ac4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Feb 21 07:21:00 2014 +0100 gma: Add EDID retrieving functions. Change-Id: I64f2fcc5ad52d6a0188d02b28769001ada718c4f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/Makefile.inc | 2 +- src/drivers/intel/gma/Kconfig | 4 ++ src/drivers/intel/gma/Makefile.inc | 2 +- src/drivers/intel/gma/edid.c | 78 ++++++++++++++++++++++++++++++++++++++ src/drivers/intel/gma/edid.h | 2 + 5 files changed, 86 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index 82d5449..eb8617c 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -1 +1 @@ -subdirs-$(CONFIG_INTEL_DP) += gma +subdirs-y += gma diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 073f708..e26c297 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -28,3 +28,7 @@ config INTEL_DDI default n help helper functions for intel DDI operations + +config INTEL_EDID + bool + default n diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index 0c3f45a..bea597e 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -19,4 +19,4 @@ ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c - +ramstage-$(CONFIG_INTEL_EDID) += edid.c diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c new file mode 100644 index 0000000..0066b6a --- /dev/null +++ b/src/drivers/intel/gma/edid.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2, or (at your option) + * any later verion of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> + +#include "i915_reg.h" +#include "edid.h" + +static void +wait_rdy(u32 mmio) +{ + unsigned try = 100; + + while (try--) { + if (read32(mmio + PCH_GMBUS2) & (1 << 11)) + return; + udelay(10); + } +} + +void +intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) +{ + int i; + + wait_rdy(mmio); + /* 100 KHz, hold 0ns, */ + write32(mmio + PCH_GMBUS0, bus); + wait_rdy(mmio); + /* Ensure index bits are disabled. */ + write32(mmio + PCH_GMBUS5, 0); + write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + wait_rdy(mmio); + /* Ensure index bits are disabled. */ + write32(mmio + PCH_GMBUS5, 0); + write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + for (i = 0; i < 128 / 4; i++) { + u32 reg32; + wait_rdy(mmio); + reg32 = read32(mmio + PCH_GMBUS3); + edid[4 * i] = reg32 & 0xff; + edid[4 * i + 1] = (reg32 >> 8) & 0xff; + edid[4 * i + 2] = (reg32 >> 16) & 0xff; + edid[4 * i + 3] = (reg32 >> 24) & 0xff; + } + wait_rdy(mmio); + write32(mmio + PCH_GMBUS1, 0x4a800000 | (slave << 1)); + wait_rdy(mmio); + write32(mmio + PCH_GMBUS0, 0x48000000); + write32(mmio + PCH_GMBUS2, 0x00008000); + + printk (BIOS_INFO, "EDID:\n"); + for (i = 0; i < 128; i++) { + printk (BIOS_INFO, "%02x ", edid[i]); + if ((i & 0xf) == 0xf) + printk (BIOS_INFO, "\n"); + } +} diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h new file mode 100644 index 0000000..1d91f70 --- /dev/null +++ b/src/drivers/intel/gma/edid.h @@ -0,0 +1,2 @@ +void +intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid);

1 0

Patch set updated for coreboot: a4560cb ivybridge: LVDS gfx init.
by Vladimir Serbinenko 27 Feb '14

27 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5285 -gerrit commit a4560cb42ab912c9ac647b2acf842aba5ef592af Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:10:35 2014 +0100 ivybridge: LVDS gfx init. Change-Id: If71e9c94922cd4283d5e175dfd8757d398a72be1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/i915_reg.h | 5 + src/mainboard/lenovo/x230/Kconfig | 5 + src/mainboard/lenovo/x230/devicetree.cb | 6 + src/northbridge/intel/sandybridge/Kconfig | 4 + src/northbridge/intel/sandybridge/Makefile.inc | 1 + src/northbridge/intel/sandybridge/chip.h | 5 + .../intel/sandybridge/gma_ivybridge_lvds.c | 514 +++++++++++++++++++++ 7 files changed, 540 insertions(+) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8c08d9f..820d10e 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -4049,6 +4049,11 @@ #define PCH_LVDS 0xe1180 #define LVDS_DETECTED (1 << 1) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) /* vlv has 2 sets of panel control regs. */ #define PIPEA_PP_STATUS 0x61200 diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index cd1f761..1e4f90b 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -16,6 +16,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select GFXUMA select EARLY_CBMEM_INIT + select VGA + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select IVYBRIDGE_LVDS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a76de5f..1a93ad8 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -10,6 +10,12 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gpu_use_spread_spectrum_clock" = "1" + register "gpu_lvds_dual_channel" = "0" + register "gpu_link_frequency_270_mhz" = "1" + register "gpu_lvds_num_lanes" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 83da527..fb92e40 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -41,6 +41,10 @@ config CACHE_MRC_SIZE_KB int default 512 +config IVYBRIDGE_LVDS + bool + default n + config MRC_CACHE_SIZE hex depends on !CHROMEOS diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index a201745..6655e2a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -20,6 +20,7 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c +ramstage-$(CONFIG_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 16df91b..e55d593 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -38,5 +38,10 @@ struct northbridge_intel_sandybridge_config { u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + + int gpu_use_spread_spectrum_clock; + int gpu_lvds_dual_channel; + int gpu_link_frequency_270_mhz; + int gpu_lvds_num_lanes; }; diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c new file mode 100644 index 0000000..f90d22a --- /dev/null +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -0,0 +1,514 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013, 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 or (at your option) + * any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <string.h> + +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> +#include "gma.h" +#include "chip.h" +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) + +static void link_train(u32 mmio) +{ + write32(mmio+0xf000c,0x40); + write32(mmio+0x60100,0x40000); + write32(mmio+0xf0018,0x8ff); + write32(mmio+0xf1018,0x8ff); + write32(mmio+0xf000c,0x2040); + mdelay(1); + write32(mmio+0xf000c,0x2050); + write32(mmio+0x60100,0x44000); + mdelay(1); + write32(mmio+0x70008,0x40); + write32(mmio+0xe0300,0x60000418); + write32(mmio+0xf000c,0x22050); + write32(mmio+0x70008,0x50); + write32(mmio+0x70008,0x80000050); +} + +static void link_normal_operation(u32 mmio) +{ + write32(mmio + FDI_TX_CTL(0), 0x80044f02); + write32(mmio + FDI_RX_CTL(0), + FDI_RX_ENABLE | FDI_6BPC + | 0x2f50); +} + +static void enable_port(u32 mmio) +{ + write32(mmio + 0xec008, 0x2c010000); + write32(mmio + 0xec020, 0x2c010000); + write32(mmio + 0xec038, 0x2c010000); + write32(mmio + 0xec050, 0x2c010000); + write32(mmio + 0xec408, 0x2c010000); + write32(mmio + 0xec420, 0x2c010000); + write32(mmio + 0xec438, 0x2c010000); + write32(mmio + 0xec450, 0x2c010000); + write32(mmio + 0xf0010, 0x200090); + write32(mmio + 0xf1010, 0x200090); + write32(mmio + 0xf2010, 0x200090); + write32(mmio + 0xfd034, 0x8420000); + write32(mmio + 0x45010, 0x3); + write32(mmio + 0xf0060, 0x10); + write32(mmio + 0xf1060, 0x10); + write32(mmio + 0xf2060, 0x10); + write32(mmio + 0x9840, 0x0); + write32(mmio + 0x42000, 0xa0000000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4100); + write32(mmio + 0xc4030, 0x10); + write32(mmio + 0xe4110, 0x8004003e); + write32(mmio + 0xe4114, 0x80060000); + write32(mmio + 0xe4118, 0x1000000); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x8054003e); + read32(mmio + 0xe4110); + read32(mmio + 0xe4110); + write32(mmio + 0xe4110, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); + read32(mmio + 0xe1140); + write32(mmio + 0xc4030, 0x10); + read32(mmio + 0xc4000); + write32(mmio + 0xe4f00, 0x100030c); + write32(mmio + 0xe4f04, 0xb8230c); + write32(mmio + 0xe4f08, 0x6f8930c); + write32(mmio + 0xe4f0c, 0x5f8e38e); + write32(mmio + 0xe4f10, 0xb8030c); + write32(mmio + 0xe4f14, 0xb78830c); + write32(mmio + 0xe4f18, 0x9f8d3cf); + write32(mmio + 0xe4f1c, 0x1e8030c); + write32(mmio + 0xe4f20, 0x9f863cf); + write32(mmio + 0xe4f24, 0xff803cf); + read32(mmio + 0xe4200); + write32(mmio + 0xc4030, 0x1010); + write32(mmio + 0xe4210, 0x8004003e); + write32(mmio + 0xe4214, 0x80060000); + write32(mmio + 0xe4218, 0x1002000); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x8054003e); + read32(mmio + 0xe4210); + read32(mmio + 0xe4210); + write32(mmio + 0xe4210, 0x5344003e); + mdelay(1); + read32(mmio + 0xc4000); +} + +void i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 piobase, u32 mmio, u32 lfb) +{ + int i; + u8 edid_data[128]; + struct edid edid; + + write32(mmio + 0x00070080, 0x00000000); + write32(mmio + DSPCNTR(0), 0x00000000); + write32(mmio + 0x00071180, 0x00000000); + write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE); + write32(mmio + 0x0007019c, 0x00000000); + write32(mmio + 0x0007119c, 0x00000000); + write32(mmio + 0x000fc008, 0x2c010000); + write32(mmio + 0x000fc020, 0x2c010000); + write32(mmio + 0x000fc038, 0x2c010000); + write32(mmio + 0x000fc050, 0x2c010000); + write32(mmio + 0x000fc408, 0x2c010000); + write32(mmio + 0x000fc420, 0x2c010000); + write32(mmio + 0x000fc438, 0x2c010000); + write32(mmio + 0x000fc450, 0x2c010000); + vga_gr_write(0x18, 0); + write32(mmio + 0x00042004, 0x02000000); + write32(mmio + 0x000fd034, 0x8421ffe0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + vga_misc_write(0x67); + + u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + enable_port(mmio); + + intel_gmbus_read_edid(mmio, 3, 0x50, edid_data); + decode_edid(edid_data, + sizeof(edid_data), &edid); + + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + u32 hactive = edid.x_resolution; + u32 vactive = edid.y_resolution; + u32 right_border = edid.hborder; + u32 bottom_border = edid.vborder; + int hpolarity = (edid.phsync == '-'); + int vpolarity = (edid.pvsync == '-'); + u32 vsync = edid.vspw; + u32 hsync = edid.hspw; + u32 vblank = edid.vbl; + u32 hblank = edid.hbl; + u32 hfront_porch = edid.hso; + u32 vfront_porch = edid.vso; + + u32 candp1, candn; + u32 best_delta = 0xffffffff; + + u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + +#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + vga_textmode_init(); +#else + vga_sr_write(1, 1); + vga_sr_write(0x2, 0xf); + vga_sr_write(0x3, 0x0); + vga_sr_write(0x4, 0xe); + vga_gr_write(0, 0x0); + vga_gr_write(1, 0x0); + vga_gr_write(2, 0x0); + vga_gr_write(3, 0x0); + vga_gr_write(4, 0x0); + vga_gr_write(5, 0x0); + vga_gr_write(6, 0x5); + vga_gr_write(7, 0xf); + vga_gr_write(0x10, 0x1); + vga_gr_write(0x11, 0); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + + write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888); + write32(mmio + DSPADDR(0), 0); + write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(mmio + DSPSURF(0), 0); + for (i = 0; i < 0x100; i++) + write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); +#endif + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return; + } + + u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; + u32 data_m1; + u32 data_n1 = 0x00800000; + u32 link_m1; + u32 link_n1 = 0x00080000; + + link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; + + data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) + / (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", + right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", + hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", + hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", + hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock + ? "Spread spectrum clock\n" : "DREF clock\n")); + printk(BIOS_DEBUG, + info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", + data_m1, data_n1); + printk(BIOS_DEBUG, "Link frequency %d kHz\n", + link_frequency); + printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", + link_m1, link_n1); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); + write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock + ? 0x1002 : 0x400)); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + _PCH_FP0(0), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + + mdelay(1); + write32(mmio + 0xc7000, 0x8); + + mdelay(1); + write32(mmio + _PCH_DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + /* Re-lock the registers. */ + write32(mmio + PCH_PP_CONTROL, + (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(mmio + PCH_LVDS, + (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + 0xf0008, 0); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1)); + write32(mmio + PF_CTL(0),0); + write32(mmio + PF_WIN_SZ(0), 0); + write32(mmio + PF_WIN_POS(0), 0); +#else + write32(mmio + PIPESRC(0), (719 << 16) | 399); + write32(mmio + PF_WIN_POS(0), 0); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +#endif + + mdelay(1); + + write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); + write32(mmio + PIPE_DATA_N1(0), data_n1); + write32(mmio + PIPE_LINK_M1(0), link_m1); + write32(mmio + PIPE_LINK_N1(0), link_n1); + + link_train(mmio); +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio+CPU_VGACNTRL,0x298e | VGA_DISP_DISABLE); +#else + write32(mmio+CPU_VGACNTRL,0x298e); +#endif + write32(mmio+0x60100,0x44300); + write32(mmio+0x60100,0x80044f00); + + mdelay(1); + read32(mmio + 0x000f0014); // = 0x00000600 + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); +#endif + + write32(mmio + TRANS_HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + TRANS_HBLANK(0), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(mmio + TRANS_HSYNC(0), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(mmio + TRANS_VTOTAL(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(mmio + TRANS_VBLANK(0), + ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + TRANS_VSYNC(0), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + link_normal_operation(mmio); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + + mdelay(1); + + write32(mmio + PCH_TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + | TRANS_STATE_MASK +#endif + ); + write32(mmio + PCH_LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_DETECTED); + + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) + { + u32 reg32; + reg32 = read32(mmio + PCH_PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); + +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); + set_vbe_mode_info_valid(&edid, lfb); +#endif +} + +#endif

1 0

Patch set updated for coreboot: bc911a8 sandybridge: Pass chip info to i915lightup.
by Vladimir Serbinenko 27 Feb '14

27 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5284 -gerrit commit bc911a80d94c7d7a68333fedd3f6161c6a5da204 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 00:09:48 2014 +0100 sandybridge: Pass chip info to i915lightup. Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/link/i915.c | 8 +++----- src/northbridge/intel/sandybridge/gma.c | 4 ++-- src/northbridge/intel/sandybridge/gma.h | 5 +++++ 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index a38760b..1f36bd1 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -35,6 +35,7 @@ #include "onboard.h" #include "ec.h" #include <southbridge/intel/bd82x6x/pch.h> +#include <northbridge/intel/sandybridge/gma.h> #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> @@ -236,11 +237,8 @@ static int run(int index) return i+1; } -int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, - unsigned int gfx); - -int i915lightup(unsigned int pphysbase, unsigned int piobase, - unsigned int pmmio, unsigned int pgfx) +void intel_gma_init(const struct northbridge_intel_sandybridge_config *info, + u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) { static struct edid edid; int edid_ok; diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..d049a80 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -643,13 +643,13 @@ static void gma_func0_init(struct device *dev) /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); u32 iobase, mmiobase, physbase, graphics_base; + struct northbridge_intel_sandybridge_config *conf = dev->chip_info; iobase = dev->resource_list[2].base; mmiobase = dev->resource_list[0].base; physbase = pci_read_config32(dev, 0x5c) & ~0xf; graphics_base = dev->resource_list[1].base; - int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); - i915lightup(physbase, iobase, mmiobase, graphics_base); + i915lightup(conf, physbase, iobase, mmiobase, graphics_base); #endif } diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index bfa43ef..f128412 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -166,3 +166,8 @@ typedef struct { #define VBT_SIGNATURE 0x54425624 +struct northbridge_intel_sandybridge_config; + +void i915lightup(const struct northbridge_intel_sandybridge_config *info, + u32 physbase, u16 pio, u32 mmio, u32 lfb); +

1 0

Patch set updated for coreboot: 419b904 nehalem: Remove SSKPD.
by Vladimir Serbinenko 27 Feb '14

27 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5268 -gerrit commit 419b90417eac34f4516488e41f0b4fa93f4b7459 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 19 22:10:03 2014 +0100 nehalem: Remove SSKPD. Not really used and conflicts with SSKPD from i915_regs.h Change-Id: I1462457f656310df99e78aee8cbfe0206f6e2a1e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/nehalem.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index e79a343..60cafdf 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -504,7 +504,6 @@ void init_iommu(void); #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) -#define SSKPD 0x5d14 /* 16bit (scratchpad) */ #define BIOS_RESET_CPL 0x5da8 /* 8bit */ /*

1 0

Patch set updated for coreboot: 14c9872 console: Use single driver entry for UARTs
by Kyösti Mälkki 27 Feb '14

27 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5308 -gerrit commit 14c9872e4ac1a21fa9af5d0f661fa19a1517105f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 10:31:38 2014 +0200 console: Use single driver entry for UARTs UARTs now have unified prototypes and can use a single entry in the list of drivers for ramstage. Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Makefile.inc | 3 +- src/console/uart8250_console.c | 54 --------------------------------- src/console/uart8250mem_console.c | 54 --------------------------------- src/console/uart_console.c | 59 ++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/uart_console.c | 33 +++----------------- src/cpu/samsung/exynos5250/uart.c | 15 +-------- src/cpu/samsung/exynos5420/uart.c | 15 +-------- src/cpu/ti/am335x/uart.c | 25 ++++----------- src/drivers/uart/pl011.c | 10 ++---- 9 files changed, 75 insertions(+), 193 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index f158670..df08e80 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -17,8 +17,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c bootblock-y += console.c bootblock-y += die.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem_console.c +ramstage-$(CONFIG_CONSOLE_SERIAL) += uart_console.c ramstage-$(CONFIG_SPKMODEM) += spkmodem_console.c ramstage-$(CONFIG_CONSOLE_USB) += usbdebug_console.c ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c deleted file mode 100644 index 52f59f6..0000000 --- a/src/console/uart8250_console.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -static void ttyS0_init(void) -{ - uart_init(); -} - -static void ttyS0_tx_byte(unsigned char data) -{ - uart_tx_byte(data); -} - -static void ttyS0_tx_flush(void) -{ - uart_tx_flush(); -} - -static unsigned char ttyS0_rx_byte(void) -{ - return uart_rx_byte(); -} - -static int ttyS0_tst_byte(void) -{ - return uart_can_rx_byte(); -} - -static const struct console_driver uart8250_console __console = { - .init = ttyS0_init, - .tx_byte = ttyS0_tx_byte, - .tx_flush = ttyS0_tx_flush, - .rx_byte = ttyS0_rx_byte, - .tst_byte = ttyS0_tst_byte, -}; diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c deleted file mode 100644 index 7e52aed..0000000 --- a/src/console/uart8250mem_console.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <console/uart.h> - -static void uartmem_init(void) -{ - uart_init(); -} - -static void uartmem_tx_byte(unsigned char data) -{ - uart_tx_byte(data); -} - -static void uartmem_tx_flush(void) -{ - uart_tx_flush(); -} - -static unsigned char uartmem_rx_byte(void) -{ - return uart_rx_byte(); -} - -static int uartmem_tst_byte(void) -{ - return uart_can_rx_byte(); -} - -static const struct console_driver uart8250mem_console __console = { - .init = uartmem_init, - .tx_byte = uartmem_tx_byte, - .tx_flush = uartmem_tx_flush, - .rx_byte = uartmem_rx_byte, - .tst_byte = uartmem_tst_byte, -}; diff --git a/src/console/uart_console.c b/src/console/uart_console.c new file mode 100644 index 0000000..e2cd6a8 --- /dev/null +++ b/src/console/uart_console.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <console/uart.h> + +static void uartmem_init(void) +{ + uart_init(); +} + +static void uartmem_tx_byte(unsigned char data) +{ + uart_tx_byte(data); +} + +static void uartmem_tx_flush(void) +{ + uart_tx_flush(); +} + +static unsigned char uartmem_rx_byte(void) +{ + return uart_rx_byte(); +} + +/* This only relevant with x86 with GDB_STUB enabled.*/ +static int uartmem_tst_byte(void) +{ +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM + return uart_can_rx_byte(); +#else + return 0; +#endif +} + +static const struct console_driver uart_console __console = { + .init = uartmem_init, + .tx_byte = uartmem_tx_byte, + .tx_flush = uartmem_tx_flush, + .rx_byte = uartmem_rx_byte, + .tst_byte = uartmem_tst_byte, +}; diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index af66cb7..aea1189 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -11,7 +11,6 @@ #include <console/uart.h> #include <arch/io.h> -#include <console/console.h> #include <cpu/allwinner/a10/uart.h> static void *get_console_uart_base_addr(void) @@ -44,7 +43,7 @@ unsigned int uart_platform_refclk(void) return 24000000; } -static void a10_uart_init_dev(void) +void uart_init(void) { void *uart_base = get_console_uart_base_addr(); @@ -54,46 +53,24 @@ static void a10_uart_init_dev(void) a10_uart_enable_fifos(uart_base); } -static unsigned char a10_uart_rx_byte(void) +unsigned char uart_rx_byte(void) { return a10_uart_rx_blocking(get_console_uart_base_addr()); } -static void a10_uart_tx_byte(unsigned char data) +void uart_tx_byte(unsigned char data) { a10_uart_tx_blocking(get_console_uart_base_addr(), data); } +#if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { return (uint32_t) get_console_uart_base_addr(); } - -#if !defined(__PRE_RAM__) -static const struct console_driver a10_uart_console __console = { - .init = a10_uart_init_dev, - .tx_byte = a10_uart_tx_byte, - .rx_byte = a10_uart_rx_byte, -}; -#else - -void uart_init(void) -{ - a10_uart_init_dev(); -} - -unsigned char uart_rx_byte(void) -{ - return a10_uart_rx_byte(); -} - -void uart_tx_byte(unsigned char data) -{ - a10_uart_tx_byte(data); -} +#endif void uart_tx_flush(void) { } -#endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index c9d8d25..14d140c 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> /* for __console definition */ #include <console/uart.h> #include <arch/io.h> #include "uart.h" @@ -169,21 +168,11 @@ static void exynos5_uart_tx_flush(void) } #if !defined(__PRE_RAM__) - -static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, - .tx_byte = exynos5_uart_tx_byte, - .tx_flush = exynos5_uart_tx_flush, - .rx_byte = exynos5_uart_rx_byte, -// .tst_byte = exynos5_uart_tst_byte, -}; - uint32_t uartmem_getbaseaddr(void) { return base_port; } - -#else +#endif void uart_init(void) { @@ -204,5 +193,3 @@ void uart_tx_flush(void) { exynos5_uart_tx_flush(); } - -#endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index f9dd268..d05adcd 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> /* for __console definition */ #include <console/uart.h> #include <arch/io.h> #include "uart.h" @@ -159,21 +158,11 @@ static void exynos5_uart_tx_byte(unsigned char data) } #if !defined(__PRE_RAM__) - -static const struct console_driver exynos5_uart_console __console = { - .init = exynos5_init_dev, - .tx_byte = exynos5_uart_tx_byte, -// .tx_flush = exynos5_uart_tx_flush, - .rx_byte = exynos5_uart_rx_byte, -// .tst_byte = exynos5_uart_tst_byte, -}; - uint32_t uartmem_getbaseaddr(void) { return base_port; } - -#else +#endif void uart_init(void) { @@ -193,5 +182,3 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } - -#endif diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index f6f1a8d..27051ea 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -20,9 +20,6 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> - -#include <console/console.h> /* for __console definition */ - #include <cpu/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) @@ -162,28 +159,18 @@ unsigned int uart_platform_refclk(void) return 48000000; } -static void am335x_uart_init_dev(void) -{ - uint16_t div = (uint16_t) uart_baudrate_divisor( - default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); -} - #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } +#endif -static const struct console_driver exynos5_uart_console __console = { - .init = am335x_uart_init_dev, - .tx_byte = am335x_uart_tx_byte, - .rx_byte = am335x_uart_rx_byte, -}; -#else void uart_init(void) { - am335x_uart_init_dev(); + uint16_t div = (uint16_t) uart_baudrate_divisor( + default_baudrate(), uart_platform_refclk(), 16); + am335x_uart_init(div); } unsigned char uart_rx_byte(void) @@ -196,6 +183,6 @@ void uart_tx_byte(unsigned char data) am335x_uart_tx_byte(data); } -void uart_tx_flush(void) { +void uart_tx_flush(void) +{ } -#endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 376e95c..2bca796 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <console/uart.h> static void pl011_uart_tx_byte(unsigned char data) @@ -25,16 +24,12 @@ static void pl011_uart_tx_byte(unsigned char data) } #if !defined(__PRE_RAM__) - -static const struct console_driver pl011_uart_console __console = { - .tx_byte = pl011_uart_tx_byte, -}; - uint32_t uartmem_getbaseaddr(void) { return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#else +#endif + void uart_init(void) { } @@ -47,4 +42,3 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } -#endif

1 0

Patch set updated for coreboot: 97ed20b uart: Prepare to support multiple base addresses
by Kyösti Mälkki 27 Feb '14

27 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5309 -gerrit commit 97ed20b193af19ace17829270e6ce1ae194027b8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 24 20:51:30 2014 +0200 uart: Prepare to support multiple base addresses Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 15 ++++++++--- src/cpu/samsung/exynos5250/uart.c | 50 +++++++++++++++++------------------- src/cpu/samsung/exynos5420/uart.c | 44 +++++++++++++++---------------- src/cpu/ti/am335x/uart.c | 30 +++++++++++----------- src/drivers/uart/pl011.c | 13 ++++++---- 5 files changed, 78 insertions(+), 74 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index aea1189..5cc1a66 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -43,9 +43,14 @@ unsigned int uart_platform_refclk(void) return 24000000; } +unsigned int uart_platform_base(int idx) +{ + return (unsigned int)get_console_uart_base_addr(); +} + void uart_init(void) { - void *uart_base = get_console_uart_base_addr(); + void *uart_base = (void *) uart_platform_base(0); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -55,18 +60,20 @@ void uart_init(void) unsigned char uart_rx_byte(void) { - return a10_uart_rx_blocking(get_console_uart_base_addr()); + void *uart_base = (void *) uart_platform_base(0); + return a10_uart_rx_blocking(uart_base); } void uart_tx_byte(unsigned char data) { - a10_uart_tx_blocking(get_console_uart_base_addr(), data); + void *uart_base = (void *) uart_platform_base(0); + a10_uart_tx_blocking(uart_base, data); } #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return (uint32_t) get_console_uart_base_addr(); + return uart_platform_base(0); } #endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 14d140c..82e221d 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - // TODO initialize with correct peripheral id by base_port. exynos_pinmux_uart3(); @@ -102,12 +96,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -130,14 +123,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -147,49 +138,54 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } -static void exynos5_uart_tx_flush(void) +static void exynos5_uart_tx_flush(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - while (readl(&uart->ufstat) & 0x1ff0000); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { - exynos5_uart_tx_flush(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_flush(uart); } diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index d05adcd..e3ae88d 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); @@ -99,12 +93,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -127,14 +120,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -144,41 +135,48 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { + /* Exynos5250 implements this too. */ } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 27051ea..faea640 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -35,10 +35,8 @@ * Initialise the serial port with the given baudrate divisor. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void am335x_uart_init(uint16_t div) +static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) { - struct am335x_uart *uart = (struct am335x_uart *) - CONFIG_CONSOLE_SERIAL_UART_ADDRESS; uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ @@ -131,11 +129,8 @@ static void am335x_uart_init(uint16_t div) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char am335x_uart_rx_byte(void) +static unsigned char am335x_uart_rx_byte(struct am335x_uart *uart) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_RXFIFOE)); return read8(&uart->rhr); @@ -144,11 +139,8 @@ static unsigned char am335x_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void am335x_uart_tx_byte(unsigned char data) +static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_TXFIFOE)); return write8(data, &uart->thr); @@ -159,28 +151,36 @@ unsigned int uart_platform_refclk(void) return 48000000; } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + return uart_platform_base(0); } #endif void uart_init(void) { + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); + am335x_uart_init(uart, div); } unsigned char uart_rx_byte(void) { - return am335x_uart_rx_byte(); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + return am335x_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - am335x_uart_tx_byte(data); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + am335x_uart_tx_byte(uart, data); } void uart_tx_flush(void) diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2bca796..c8b7415 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -15,12 +15,14 @@ #include <console/uart.h> -static void pl011_uart_tx_byte(unsigned char data) +static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *) CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + *uart_base = (unsigned int)data; +} - *uart0_address = (unsigned int)data; +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } #if !defined(__PRE_RAM__) @@ -36,7 +38,8 @@ void uart_init(void) void uart_tx_byte(unsigned char data) { - pl011_uart_tx_byte(data); + unsigned int *uart_base = (unsigned int *) uart_platform_base(0); + pl011_uart_tx_byte(uart_base, data); } void uart_tx_flush(void)

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2014