coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

1 participants
1135 discussions

Patch merged into coreboot/master: 2212219 rambi: Enable SATA port
by gerrit＠coreboot.org 27 Feb '14

27 Feb '14

the following patch was just integrated into master: commit 22122194881449384ec739c2edb27c4bb42ddfdf Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Oct 28 16:43:17 2013 -0700 rambi: Enable SATA port Enable first SATA port in Rambi device tree. BUG=chrome-os-partner:23643 TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174916 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4914 for details. -gerrit

1 0

Patch set updated for coreboot: b0b77d0 x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5305 -gerrit commit b0b77d0f281b72d602cc264cae1da26713c3c455 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 20:36:56 2014 -0600 x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 11 ++++++ src/cpu/x86/Makefile.inc | 1 + src/cpu/x86/mirror_payload.c | 71 ++++++++++++++++++++++++++++++++++ src/include/payload_loader.h | 3 ++ src/lib/loaders/load_and_run_payload.c | 7 ++++ 5 files changed, 93 insertions(+) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 19fa246..9737e23 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -121,3 +121,14 @@ config BACKUP_DEFAULT_SMM_REGION help The cpu support will select this option if the default SMM region needs to be backed up for suspend/resume purposes. + +config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING + bool "Copy payload contents to ram before loading to final destination." + depends on EXPERT + default n + help + On certain platforms a boot speed gain can be realized if mirroring + the payload data stored in non-volatile storage. On x86 systems the + payload would typically live in a memory-mapped SPI part. Copying + the SPI contents to ram before performing the load can speed up + the boot process. diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index d5bc2fd..277ba48 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -3,6 +3,7 @@ romstage-$(CONFIG_HAVE_ACPI_RESUME) += car.c subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c +ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf SIPI_BIN=$(SIPI_ELF:.elf=) diff --git a/src/cpu/x86/mirror_payload.c b/src/cpu/x86/mirror_payload.c new file mode 100644 index 0000000..edd2641 --- /dev/null +++ b/src/cpu/x86/mirror_payload.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <console/console.h> +#include <bootmem.h> +#include <payload_loader.h> + +void mirror_payload(struct payload *payload) +{ + char *buffer; + size_t size; + char *src; + uintptr_t alignment_diff; + const unsigned long cacheline_size = 64; + const uintptr_t intra_cacheline_mask = cacheline_size - 1; + const uintptr_t cacheline_mask = ~intra_cacheline_mask; + + src = payload->backing_store.data; + size = payload->backing_store.size; + + /* + * Adjust size so that the start and end points are aligned to a + * cacheline. The SPI hardware controllers on Intel machines should + * cache full length cachelines as well as prefetch data. Once the + * data is mirrored in memory all accesses should hit the CPU's cache. + */ + alignment_diff = (intra_cacheline_mask & (uintptr_t)src); + size += alignment_diff; + + size = ALIGN(size, cacheline_size); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%zx\n", size); + + buffer = bootmem_allocate_buffer(size); + + if (buffer == NULL) { + printk(BIOS_DEBUG, "No buffer for mirroring payload.\n"); + return; + } + + src = (void *)(cacheline_mask & (uintptr_t)src); + + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(buffer, src, size); + + /* Update the payload's backing store. */ + payload->backing_store.data = &buffer[alignment_diff]; +} diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7ef5806..7a3f045 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -44,6 +44,9 @@ struct payload *payload_load(void); /* Run the loaded payload. */ void payload_run(const struct payload *payload); +/* Mirror the payload to be loaded. */ +void mirror_payload(struct payload *payload); + /* architecture specific function to run payload. */ void arch_payload_run(const struct payload *payload); diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 7e1383e..2204090 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -39,6 +39,11 @@ static struct payload global_payload = { .name = CONFIG_CBFS_PREFIX "/payload", }; +void __attribute__((weak)) mirror_payload(struct payload *payload) +{ + return; +} + struct payload *payload_load(void) { int i; @@ -62,6 +67,8 @@ struct payload *payload_load(void) if (i == ARRAY_SIZE(payload_ops)) return NULL; + mirror_payload(payload); + entry = selfload(payload); if (entry == NULL)

1 0

Patch merged into coreboot/master: 037df2c baytrail: Add SATA driver
by gerrit＠coreboot.org 27 Feb '14

27 Feb '14

the following patch was just integrated into master: commit 037df2cb648852977ba3eb3fa90557ee58795bbb Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Oct 28 16:15:02 2013 -0700 baytrail: Add SATA driver Add SATA driver for baytrail platform. BUG=chrome-os-partner:23643 TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174914 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4913 for details. -gerrit

1 0

Patch merged into coreboot/master: 246c674 rambi: add all on-board devices
by gerrit＠coreboot.org 27 Feb '14

27 Feb '14

the following patch was just integrated into master: commit 246c674b93f22d58996c763753cb9e0ec9fcbc52 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 17:00:07 2013 -0500 rambi: add all on-board devices Add the on-board devices in the SoC to the device tree. Also, disable the unused devices aside from TXE and HDA. Those particular devices cause the system to shut down when they are disabled. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Noted the calls to the southcluster disable function. Change-Id: I482c1c9609833054aeb2948144af54b57d3df086 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174645 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4912 for details. -gerrit

1 0

Patch merged into coreboot/master: 631312a baytrail: add support for disabling south cluster pci devices
by gerrit＠coreboot.org 27 Feb '14

27 Feb '14

the following patch was just integrated into master: commit 631312a2ea9256d793aa005a025eb7bf40bf1e27 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 16:37:10 2013 -0500 baytrail: add support for disabling south cluster pci devices When the southcluster pci devices are listed in the devicetree add the ability to perform the proper disabling sequence for turning off devices. This only turns off the pci device interface as well as put the device into D3Hot. It is not yet known how to put the TXE device into D3Hot so it's currently not possible to disable that device. Also, expose the southcluster_enable_dev() function so that other devices can call this if they require doing specific things before disabling the device. The southcluster_enable_dev() is only called on devices found in the devicetree and if they currently have no ops associated with them. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Interrogated output to ensure devices were being properly disabled. Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174644 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4911 for details. -gerrit

1 0

Patch merged into coreboot/master: 7ab6ae8 baytrail: use MCRX in iosf access functions
by gerrit＠coreboot.org 27 Feb '14

27 Feb '14

the following patch was just integrated into master: commit 7ab6ae80f87c217f14769c841ab69c179bdcfe20 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 10:57:31 2013 -0500 baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4909 for details. -gerrit

1 0

Patch set updated for coreboot: ffb9dcb baytrail: use common code for iosf accessors
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4922 -gerrit commit ffb9dcb06582b1ae84bb9dc72f8cc9946998441d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 31 11:58:32 2013 -0500 baytrail: use common code for iosf accessors The same sequence is used regardless of the port being read or written. Therefore, use the same implementation for reading or writing to a port. BUG=None BRANCH=None TEST=Built and booted through depthcharge. Dev and recovery screens still work. Nothing bizarre in console output. Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175441 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/iosf.c | 115 +++++++++++++++--------------------------- 1 file changed, 41 insertions(+), 74 deletions(-) diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 8016446..a7f7a90 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -42,35 +42,42 @@ static inline uint32_t read_iosf_reg(int reg) } #endif -uint32_t iosf_bunit_read(int reg) +/* Common sequences for all the port accesses. */ +static uint32_t iosf_read_port(uint32_t cr, int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; - + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } -void iosf_bunit_write(int reg, uint32_t val) +static void iosf_write_port(uint32_t cr, int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; - + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } +uint32_t iosf_bunit_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | + IOSF_PORT(IOSF_PORT_BUNIT); + return iosf_read_port(cr, reg); +} + +void iosf_bunit_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | + IOSF_PORT(IOSF_PORT_BUNIT); + iosf_write_port(cr, reg, val); +} + uint32_t iosf_dunit_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_SYSMEMC); + return iosf_read_port(cr, reg); } uint32_t iosf_dunit_ch0_read(int reg) @@ -81,109 +88,69 @@ uint32_t iosf_dunit_ch0_read(int reg) uint32_t iosf_dunit_ch1_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_DUNIT_CH1); + return iosf_read_port(cr, reg); } void iosf_dunit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_SYSMEMC); + iosf_write_port(cr, reg, val); } uint32_t iosf_punit_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) | - IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_PMC); + return iosf_read_port(cr, reg); } void iosf_punit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | - IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_PMC); + iosf_write_port(cr, reg, val); } uint32_t iosf_usbphy_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_USBPHY); + return iosf_read_port(cr, reg); } void iosf_usbphy_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_USBPHY); + return iosf_write_port(cr, reg, val); } uint32_t iosf_ushphy_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_USHPHY); + return iosf_read_port(cr, reg); } void iosf_ushphy_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_USHPHY); + return iosf_write_port(cr, reg, val); } uint32_t iosf_lpss_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_LPSS); + return iosf_read_port(cr, reg); } void iosf_lpss_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_LPSS); + return iosf_write_port(cr, reg, val); }

1 0

Patch set updated for coreboot: 3f97d19 baytrail: add lpss iosf functions and regs
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4921 -gerrit commit 3f97d190322e44c584e1d08a09096410617469d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 31 10:46:56 2013 -0500 baytrail: add lpss iosf functions and regs The low power subsystem devices have a lot of their configuration done in the IOSF sideband message space. Add support for these access methods. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted through depthcharge. Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636 Signed-off-by: Aaron Durbin <adurbin(a)chromum.org> Reviewed-on: https://chromium-review.googlesource.com/175440 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 29 +++++++++++++++++++++++++++++ src/soc/intel/baytrail/iosf.c | 22 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index b234552..9b59fbc 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -68,6 +68,8 @@ uint32_t iosf_usbphy_read(int reg); void iosf_usbphy_write(int reg, uint32_t val); uint32_t iosf_ushphy_read(int reg); void iosf_ushphy_write(int reg, uint32_t val); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -81,6 +83,7 @@ void iosf_ushphy_write(int reg, uint32_t val); #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -103,6 +106,8 @@ void iosf_ushphy_write(int reg, uint32_t val); #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) #define IOSF_OP_READ_USHPHY 0x06 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_LPSS 0x06 +#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) #define IOSF_OP_READ_SATAPHY 0x00 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 @@ -167,4 +172,28 @@ void iosf_ushphy_write(int reg, uint32_t val); #define PUNIT_PWRGT_STATUS 0x61 #define PUNIT_GPU_EC_VIRUS 0xd2 +/* + * LPSS Registers + */ +#define LPSS_SIO_DMA1_CTL 0x280 +#define LPSS_I2C1_CTL 0x288 +#define LPSS_I2C2_CTL 0x290 +#define LPSS_I2C3_CTL 0x298 +#define LPSS_I2C4_CTL 0x2a0 +#define LPSS_I2C5_CTL 0x2a8 +#define LPSS_I2C6_CTL 0x2b0 +#define LPSS_I2C7_CTL 0x2b8 +#define LPSS_SIO_DMA2_CTL 0x240 +#define LPSS_PWM1_CTL 0x248 +#define LPSS_PWM2_CTL 0x250 +#define LPSS_HSUART1_CTL 0x258 +#define LPSS_HSUART2_CTL 0x260 +#define LPSS_SPI_CTL 0x268 +# define LPSS_CTL_ACPI_INT_EN (1 << 21) +# define LPSS_CTL_PCI_CFG_DIS (1 << 20) +# define LPSS_CTL_SNOOP (1 << 18) +# define LPSS_CTL_NOSNOOP (1 << 19) +# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) + + #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 7d420cc..8016446 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -165,3 +165,25 @@ void iosf_ushphy_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_lpss_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_lpss_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +}

1 0

Patch set updated for coreboot: a6a1adc baytrail: Fix EHCI function number and XHCI typo
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4920 -gerrit commit a6a1adc3d16d13354fbd36982b2af10d94842dcd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 1 07:55:07 2013 -0700 baytrail: Fix EHCI function number and XHCI typo BUG=chrome-os-partner:23635 BRANCH=rambi TEST=successfully disable EHCI controller in devicetree.cb Change-Id: I8a22e25a9f7c263d2a6debf0cd1606cb0f6f7645 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175403 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 6b38a71..96e9547 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -53,7 +53,7 @@ /* xHCI */ #define XHCI_DEV 20 #define XHCI_FUNC 0 -# define XCHI_DEVID 0x0f35 +# define XHCI_DEVID 0x0f35 /* LPE Audio */ #define LPE_DEV 21 @@ -119,7 +119,7 @@ /* EHCI */ #define EHCI_DEV 29 -#define EHCI_FUNC 29 +#define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 /* Serial IO 2 */

1 0

Patch set updated for coreboot: 4025b3e rambi: Enable internal keyboard
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4915 -gerrit commit 4025b3e5a85a79309f04c2fa917683c6035a03cb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 31 10:10:20 2013 -0700 rambi: Enable internal keyboard The EC LPC init function needs to run to enable the internal keyboard. I needed this to confirm that it is just USB keyboards that are causing all sorts of issues. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=boot to recovery screen and hit tab Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175207 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 10 +++++++++- src/soc/intel/baytrail/southcluster.c | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index e7f86ce..66d98ed 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -38,7 +38,15 @@ chip soc/intel/baytrail device pci 1e.3 off end # HSUART1 device pci 1e.4 on end # HSUART2 device pci 1e.5 on end # SPI - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge device pci 1f.3 off end # SMBus end end diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b58f0e0..eacabf3 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -385,7 +385,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = NULL, .enable = southcluster_enable_dev, - .scan_bus = NULL, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, };

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
114
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2014