coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2212219 rambi: Enable SATA port
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4914 -gerrit commit 22122194881449384ec739c2edb27c4bb42ddfdf Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Oct 28 16:43:17 2013 -0700 rambi: Enable SATA port Enable first SATA port in Rambi device tree. BUG=chrome-os-partner:23643 TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174916 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 3086ebf..e7f86ce 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -1,4 +1,10 @@ chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + device cpu_cluster 0 on device lapic 0 on end end

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Patch set updated for coreboot: 037df2c baytrail: Add SATA driver
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4913 -gerrit commit 037df2cb648852977ba3eb3fa90557ee58795bbb Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Oct 28 16:15:02 2013 -0700 baytrail: Add SATA driver Add SATA driver for baytrail platform. BUG=chrome-os-partner:23643 TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174914 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/pci_devs.h | 6 +- src/soc/intel/baytrail/baytrail/sata.h | 26 ++++ src/soc/intel/baytrail/chip.h | 10 +- src/soc/intel/baytrail/sata.c | 240 +++++++++++++++++++++++++++++ 5 files changed, 279 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 3e62ccf..ad3f94f 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -33,6 +33,7 @@ smm-y += smihandler.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c +ramstage-y += sata.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index f20102a..6b38a71 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -45,8 +45,10 @@ /* SATA */ #define SATA_DEV 19 #define SATA_FUNC 0 -# define ACHI1_DEVID 0x0f22 -# define ACHI2_DEVID 0x0f23 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 /* xHCI */ #define XHCI_DEV 20 diff --git a/src/soc/intel/baytrail/baytrail/sata.h b/src/soc/intel/baytrail/baytrail/sata.h new file mode 100644 index 0000000..7704c18 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/sata.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_SATA_H +#define BAYTRAIL_SATA_H + +#define SATA_SIRI 0xa0 +#define SATA_SIRD 0xa4 + +#endif diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index b6d3f84..d17474f 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -17,12 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_CHIP_H_ -#define _BAYTRAIL_CHIP_H_ /* The devicetree parser expects chip.h to reside directly in the path * specified by the devicetree. */ +#ifndef _BAYTRAIL_CHIP_H_ +#define _BAYTRAIL_CHIP_H_ + +#include <stdint.h> + struct soc_intel_baytrail_config { + uint8_t sata_port_map; + uint8_t sata_ahci; + uint8_t ide_legacy_combined; }; extern struct chip_operations soc_intel_baytrail_ops; diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c new file mode 100644 index 0000000..28a2f8c --- /dev/null +++ b/src/soc/intel/baytrail/sata.c @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <baytrail/sata.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include "chip.h" + +typedef struct soc_intel_baytrail_config config_t; + +static inline void sir_write(struct device *dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + +static void sata_init(struct device *dev) +{ + config_t *config = dev->chip_info; + u32 reg32; + u16 reg16; + u8 reg8; + + printk(BIOS_DEBUG, "SATA: Initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); + return; + } + + if (!config->sata_ahci) { + /* Set legacy or native decoding mode */ + if (config->ide_legacy_combined) { + reg8 = pci_read_config8(dev, 0x09); + reg8 &= ~0x5; + pci_write_config8(dev, 0x09, reg8); + } else { + reg8 = pci_read_config8(dev, 0x09); + reg8 |= 0x5; + pci_write_config8(dev, 0x09, reg8); + } + + /* Set capabilities pointer */ + pci_write_config8(dev, 0x34, 0x70); + reg16 = pci_read_config16(dev, 0x70); + reg16 &= ~0xFF00; + pci_write_config16(dev, 0x70, reg16); + } + + /* Primary timing - decode enable */ + reg16 = pci_read_config16(dev, 0x40); + reg16 |= 1 << 15; + pci_write_config16(dev, 0x40, reg16); + + /* Secondary timing - decode enable */ + reg16 = pci_read_config16(dev, 0x42); + reg16 |= 1 << 15; + pci_write_config16(dev, 0x42, reg16); + + /* Port mapping enables */ + reg16 = pci_read_config16(dev, 0x90); + reg16 |= (config->sata_port_map ^ 0x3) << 8; + pci_write_config16(dev, 0x90, reg16); + + /* Port control enables */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x003f; + reg16 |= config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + + if (config->sata_ahci) { + u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + /* Enable CR memory space decoding */ + reg16 = pci_read_config16(dev, 0x04); + reg16 |= 0x2; + pci_write_config16(dev, 0x04, reg16); + + /* Set capability register */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM + reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits + reg32 |= (0x3 << 20); // Gen3 SATA + write32(abar + 0x00, reg32); + + /* Ports enabled */ + reg32 = read32(abar + 0x0c); + reg32 &= (u32)(~0x3f); + reg32 |= config->sata_port_map; + write32(abar + 0xc, reg32); + /* Two extra reads to latch */ + read32(abar + 0x0c); + read32(abar + 0x0c); + + /* Set cap2 - Support devslp */ + reg32 = (1 << 5) | (1 << 4) | (1 << 3); + write32(abar + 0x24, reg32); + + /* Set PxCMD registers */ + reg32 = read32(abar + 0x118); + reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | + (1 << 19) | (1 << 18) | (1 << 1)); + reg32 |= 2; + write32(abar + 0x118, reg32); + + reg32 = read32(abar + 0x198); + reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | + (1 << 19) | (1 << 18) | (1 << 1)); + reg32 |= 2; + write32(abar + 0x198, reg32); + + /* Clear reset features */ + write32(abar + 0xc8, 0); + + /* Enable interrupts */ + reg8 = read8(abar + 0x04); + reg8 |= 0x02; + write8(abar + 0x04, reg8); + + } else { + /* TODO(shawnn): Configure IDE SATA speed regs */ + } + + /* 1.4 us delay after configuring port / enable bits */ + udelay(2); + + /* Enable clock for ports */ + reg32 = pci_read_config32(dev, 0x94); + reg32 |= 0x3f << 24; + pci_write_config32(dev, 0x94, reg32); + reg32 &= (config->sata_port_map ^ 0x3) << 24; + pci_write_config32(dev, 0x94, reg32); + + /* Lock SataGc register */ + reg32 = (0x1 << 31) | (0x7 << 12); + pci_write_config32(dev, 0x98, reg32); +} + +static void sata_enable(device_t dev) +{ + config_t *config = dev->chip_info; + u8 reg8; + u16 reg16; + u32 reg32; + + southcluster_enable_dev(dev); + if (!config) + return; + + /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ + reg16 = pci_read_config16(dev, 0x90); + reg16 &= ~0x03e0; + reg16 |= (config->sata_port_map ^ 0x3) << 8; + if(config->sata_ahci) + reg16 |= 0x60; + pci_write_config16(dev, 0x90, reg16); + + /* Set reg 0x94 before starting configuration */ + reg32 = pci_read_config32(dev, 0x94); + reg32 &= (u32)(~0x1ff); + reg32 |= 0x183; + pci_write_config32(dev, 0x94, reg32); + + /* Set ORM bit */ + reg16 = pci_read_config16(dev, 0x92); + reg16 |= (1 << 15); + pci_write_config16(dev, 0x92, reg16); + + /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ + reg32 = pci_read_config32(dev, 0x98); + reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); + reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | + (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); + pci_write_config32(dev, 0x98, reg32); + + /* CMD reg - set bus master enable (BME) */ + reg8 = pci_read_config8(dev, 0x04); + reg8 |= (1 << 2); + pci_write_config8(dev, 0x04, reg8); + + /* "Test mode registers" */ + sir_write(dev, 0x70, 0x00288301); + sir_write(dev, 0x54, 0x00000300); + sir_write(dev, 0x58, 0x50000000); + /* "OOB Detection Margin */ + sir_write(dev, 0x6c, 0x130C0603); + /* "Gasket Control" */ + sir_write(dev, 0xf4, 0); + + /* PCS - Enable requested SATA ports */ + reg8 = pci_read_config8(dev, 0x92); + reg8 &= ~0x03; + reg8 |= config->sata_port_map; + pci_write_config8(dev, 0x92, reg8); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = sata_enable, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + IDE1_DEVID, IDE2_DEVID, /* IDE */ + AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ + 0, +}; + +static const struct pci_driver baytrail_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: 246c674 rambi: add all on-board devices
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4912 -gerrit commit 246c674b93f22d58996c763753cb9e0ec9fcbc52 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 17:00:07 2013 -0500 rambi: add all on-board devices Add the on-board devices in the SoC to the device tree. Also, disable the unused devices aside from TXE and HDA. Those particular devices cause the system to shut down when they are disabled. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Noted the calls to the southcluster disable function. Change-Id: I482c1c9609833054aeb2948144af54b57d3df086 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174645 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 34 +++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index c6ea97c..3086ebf 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -3,8 +3,36 @@ chip soc/intel/baytrail device lapic 0 on end end device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 1f.0 on end # LPC Bridge + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 on end # HSUART2 + device pci 1e.5 on end # SPI + device pci 1f.0 on end # LPC Bridge + device pci 1f.3 off end # SMBus end end

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Patch set updated for coreboot: 78d8a31 baytrail: increment boot count for elog
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4919 -gerrit commit 78d8a3146be8f39e05fe0677001f45b24e9982fc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 15:46:07 2013 -0500 baytrail: increment boot count for elog The elog boot counter in cmos was not being initialized nor incremented. Start doing that in romstage. Since S3 resume is not detected yet the increment is unconditional. BUG=None BRANCH=None TEST=Built and booted through depthcharge multiple times. Noted output such as 'Boot Count incremented to 4'. Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174717 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/romstage/romstage.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 9752363..5af9bf4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -28,6 +28,7 @@ #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> #endif +#include <elog.h> #include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> @@ -145,6 +146,10 @@ void romstage_common(struct romstage_params *params) mark_ts(params, timestamp_get()); +#if CONFIG_ELOG_BOOT_COUNT + boot_count_increment(); +#endif + /* Initialize RAM */ raminit(params->mrc_params, 5);

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Patch set updated for coreboot: eea7d58 baytrail: add GNVS to cbmem and set acpi_slp_type
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4918 -gerrit commit eea7d58c694fdf8913137abb3f4fcd9fbbf8e417 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 15:25:42 2013 -0500 baytrail: add GNVS to cbmem and set acpi_slp_type The ACPI code was previously complaining about not being able to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix this by adding GNVS area early in start up. This is also the appropriate place to set the acpi_slp_type variable to indicate an S3 resume or not. BUG=chrome-os-partner:22867 BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS' entry. Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174647 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/ramstage.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 896ecfe..ab29190 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -18,6 +18,8 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -25,14 +27,16 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <romstage_handoff.h> #include <stdlib.h> -#include <baytrail/pattrs.h> +#include <baytrail/gpio.h> #include <baytrail/lpc.h> #include <baytrail/msr.h> +#include <baytrail/nvs.h> +#include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> -#include <baytrail/gpio.h> /* Global PATTRS */ DEFINE_PATTRS; @@ -103,6 +107,31 @@ static void fill_in_pattrs(void) fill_in_msr(&attrs->iacore_vids, MSR_IACORE_VIDS); } +static inline void set_acpi_sleep_type(int val) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = val; +#endif +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) { + memset(gnvs, 0, sizeof(global_nvs_t)); + } + set_acpi_sleep_type(0); + return; + } + + set_acpi_sleep_type(3); +} void baytrail_init_pre_device(void) { @@ -119,4 +148,7 @@ void baytrail_init_pre_device(void) /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); + + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); }

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Patch set updated for coreboot: 306ef11 baytrail: fix uninitialized acpi structures
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4917 -gerrit commit 306ef11b6851f921a62753d8f343567c5aade2dc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 14:36:11 2013 -0500 baytrail: fix uninitialized acpi structures The callers of the following functions assume the storage area provided by the pointers is initialized. That's not the case as these were just place holders. - void acpi_create_intel_hpet(acpi_hpet_t * hpet); - void acpi_create_serialio_ssdt(acpi_header_t *ssdt); To fix this properly initialize the hpet entry, and just remove the serialio_ssdt function entirely. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge on rambi. Noted no more ACPI errors relating to invalid length. Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174716 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/acpi_tables.c | 7 ---- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/acpi.c | 58 ++++++++++++++++++++++++++++++++ src/soc/intel/baytrail/baytrail/acpi.h | 1 - src/soc/intel/baytrail/baytrail/iomap.h | 1 + src/soc/intel/baytrail/placeholders.c | 4 --- 6 files changed, 60 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 3723021..0b96228 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -274,13 +274,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); ALIGN_CURRENT; - printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); - ssdt = (acpi_header_t *)current; - acpi_create_serialio_ssdt(ssdt); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - printk(BIOS_DEBUG, "current = %lx\n", current); printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index ad3f94f..d414057 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += smm.c ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c +ramstage-y += acpi.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c new file mode 100644 index 0000000..84d125a --- /dev/null +++ b/src/soc/intel/baytrail/acpi.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <types.h> +#include <string.h> + +#include <baytrail/acpi.h> +#include <baytrail/iomap.h> + +void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; + addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h index 917eb26..b269e44 100644 --- a/src/soc/intel/baytrail/baytrail/acpi.h +++ b/src/soc/intel/baytrail/baytrail/acpi.h @@ -23,7 +23,6 @@ #include <arch/acpi.h> void acpi_create_intel_hpet(acpi_hpet_t * hpet); -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h index 9fc8da7..fa34105 100644 --- a/src/soc/intel/baytrail/baytrail/iomap.h +++ b/src/soc/intel/baytrail/baytrail/iomap.h @@ -30,6 +30,7 @@ #define MPHY_BASE_ADDRESS 0xfef00000 #define PUNIT_BASE_ADDRESS 0xfed05000 #define RCBA_BASE_ADDRESS 0xfed1c000 +#define HPET_BASE_ADDRESS 0xfed00000 /* IO Port base */ #define ACPI_BASE_ADDRESS 0x0400 diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c index 63f0fb3..5267927 100644 --- a/src/soc/intel/baytrail/placeholders.c +++ b/src/soc/intel/baytrail/placeholders.c @@ -7,10 +7,6 @@ void generate_cpu_entries(void) {} -void acpi_create_intel_hpet(acpi_hpet_t * hpet) {} - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} - unsigned long acpi_fill_mcfg(unsigned long current) { return current; } void smm_init(void) {}

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Patch set updated for coreboot: 5701787 baytrail: Add IOSF functions for USBPHY and USHPHY
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4916 -gerrit commit 570178797f6d18868b8980e4a2ff47897a6612fa Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 31 08:20:48 2013 -0700 baytrail: Add IOSF functions for USBPHY and USHPHY These are needed for USB2 and USB3 PHY init sequences. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175227 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 7 ++++++ src/soc/intel/baytrail/iosf.c | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 7f0c7f5..b234552 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -64,6 +64,10 @@ uint32_t iosf_dunit_ch0_read(int reg); uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); +uint32_t iosf_ushphy_read(int reg); +void iosf_ushphy_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -76,6 +80,7 @@ void iosf_punit_write(int reg, uint32_t val); #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -96,6 +101,8 @@ void iosf_punit_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) #define IOSF_OP_READ_USBPHY 0x06 #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_USHPHY 0x06 +#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) #define IOSF_OP_READ_SATAPHY 0x00 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index b050eba..7d420cc 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -121,3 +121,47 @@ void iosf_punit_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_usbphy_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | + IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | + IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} + +uint32_t iosf_ushphy_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | + IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_ushphy_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | + IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +}

1 0

Patch set updated for coreboot: 631312a baytrail: add support for disabling south cluster pci devices
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4911 -gerrit commit 631312a2ea9256d793aa005a025eb7bf40bf1e27 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 16:37:10 2013 -0500 baytrail: add support for disabling south cluster pci devices When the southcluster pci devices are listed in the devicetree add the ability to perform the proper disabling sequence for turning off devices. This only turns off the pci device interface as well as put the device into D3Hot. It is not yet known how to put the TXE device into D3Hot so it's currently not possible to disable that device. Also, expose the southcluster_enable_dev() function so that other devices can call this if they require doing specific things before disabling the device. The southcluster_enable_dev() is only called on devices found in the devicetree and if they currently have no ops associated with them. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Interrogated output to ensure devices were being properly disabled. Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174644 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 4 + src/soc/intel/baytrail/baytrail/pmc.h | 33 ++++ src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.c | 8 +- src/soc/intel/baytrail/southcluster.c | 268 ++++++++++++++++++++++++++++- 5 files changed, 311 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 8b0335e..f20102a 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -102,12 +102,16 @@ /* PCIe Ports */ #define PCIE_DEV 28 +# define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 # define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 # define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 # define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index e0e5cff..51f8887 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -33,6 +33,39 @@ # define IGNORE_HPET (1 << 21) # define CF9GR (1 << 20) # define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index eaa8f6b..4fa6ddd 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -27,6 +27,7 @@ void baytrail_init_pre_device(void); void baytrail_init_cpus(device_t dev); void set_max_freq(void); +void southcluster_enable_dev(device_t dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 0f686fa..eedae39 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -53,13 +53,17 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(device_t dev) { - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } } } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 32b8799..b58f0e0 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <arch/io.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -29,6 +30,7 @@ #include <baytrail/lpc.h> #include <baytrail/nvs.h> #include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> #include <baytrail/ramstage.h> static inline void @@ -113,12 +115,276 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +/* + * Common code for the south cluster devices. + */ + +/* Set bit in function disble register to hide this device. */ +static void sc_disable_devfn(device_t dev) +{ + const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; + const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t mask = 0; + uint32_t mask2 = 0; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + mask |= SDIO_DIS; + break; + case PCI_DEVFN(SD_DEV, SD_FUNC): + mask |= SD_DIS; + break; + case PCI_DEVFN(SATA_DEV, SATA_FUNC): + mask |= SATA_DIS; + break; + case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + mask |= XHCI_DIS; + /* Disable super speed PHY when XHCI is not available. */ + mask2 |= USH_SS_PHY_DIS; + break; + case PCI_DEVFN(LPE_DEV, LPE_FUNC): + mask |= LPE_DIS; + break; + case PCI_DEVFN(MMC_DEV, MMC_FUNC): + mask |= MMC_DIS; + break; + case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): + mask |= SIO_DMA1_DIS; + break; + case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): + mask |= I2C1_DIS; + break; + case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): + mask |= I2C1_DIS; + break; + case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): + mask |= I2C3_DIS; + break; + case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): + mask |= I2C4_DIS; + break; + case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): + mask |= I2C5_DIS; + break; + case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): + mask |= I2C6_DIS; + break; + case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): + mask |= I2C7_DIS; + break; + case PCI_DEVFN(TXE_DEV, TXE_FUNC): + mask |= TXE_DIS; + break; + case PCI_DEVFN(HDA_DEV, HDA_FUNC): + mask |= HDA_DIS; + break; + case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): + mask |= PCIE_PORT1_DIS; + break; + case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): + mask |= PCIE_PORT2_DIS; + break; + case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): + mask |= PCIE_PORT3_DIS; + break; + case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + mask |= PCIE_PORT4_DIS; + break; + case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): + mask |= EHCI_DIS; + break; + case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): + mask |= SIO_DMA2_DIS; + break; + case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): + mask |= PWM1_DIS; + break; + case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): + mask |= PWM2_DIS; + break; + case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): + mask |= HSUART1_DIS; + break; + case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): + mask |= HSUART2_DIS; + break; + case PCI_DEVFN(SPI_DEV, SPI_FUNC): + mask |= SPI_DIS; + break; + case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): + mask2 |= SMBUS_DIS; + break; + } + + if (mask != 0) { + write32(func_dis, read32(func_dis) | mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (mask2 != 0) { + write32(func_dis2, read32(func_dis2) | mask2); + /* Ensure posted write hits. */ + read32(func_dis2); + } +} + +static inline void set_d3hot_bits(device_t dev, int offset) +{ + uint32_t reg8; + printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); + reg8 = pci_read_config8(dev, offset + 4); + reg8 |= 0x3; + pci_write_config8(dev, offset + 4, reg8); +} + +static int place_device_in_d3hot(device_t dev) +{ + unsigned offset; + + offset = pci_find_capability(dev, PCI_CAP_ID_PM); + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + /* For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. */ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SD_DEV, SD_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(MMC_DEV, MMC_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(LPE_DEV, LPE_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SPI_DEV, SPI_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SATA_DEV, SATA_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(HDA_DEV, HDA_FUNC): + offset = 0x50; + break; + case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): + offset = 0x50; + break; + case PCI_DEVFN(TXE_DEV, TXE_FUNC): + break; + case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + offset = 0xa0; + break; + } + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + return -1; +} + +/* Common PCI device function disable. */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Place device in D3Hot */ + if (place_device_in_d3hot(dev) < 0) { + printk(BIOS_WARNING, + "Could not place %02x.%01x into D3Hot. " + "Keeping device visible.\n", slot, func); + return; + } + /* Disable this device if possible */ + sc_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, .init = NULL, - .enable = NULL, + .enable = southcluster_enable_dev, .scan_bus = NULL, .ops_pci = &soc_pci_ops, };

1 0

Patch set updated for coreboot: d450932 baytrail: add support for disabling south cluster pci devices
by Aaron Durbin 27 Feb '14

27 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4911 -gerrit commit d450932e9f125113ce1861b448476bb2c235ea45 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 16:37:10 2013 -0500 baytrail: add support for disabling south cluster pci devices When the southcluster pci devices are listed in the devicetree add the ability to perform the proper disabling sequence for turning off devices. This only turns off the pci device interface as well as put the device into D3Hot. It is not yet known how to put the TXE device into D3Hot so it's currently not possible to disable that device. Also, expose the southcluster_enable_dev() function so that other devices can call this if they require doing specific things before disabling the device. The southcluster_enable_dev() is only called on devices found in the devicetree and if they currently have no ops associated with them. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Interrogated output to ensure devices were being properly disabled. Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174644 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 4 + src/soc/intel/baytrail/baytrail/pmc.h | 33 ++++ src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.c | 8 +- src/soc/intel/baytrail/southcluster.c | 268 ++++++++++++++++++++++++++++- 5 files changed, 311 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 8b0335e..f20102a 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -102,12 +102,16 @@ /* PCIe Ports */ #define PCIE_DEV 28 +# define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 # define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 # define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 # define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index e0e5cff..51f8887 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -33,6 +33,39 @@ # define IGNORE_HPET (1 << 21) # define CF9GR (1 << 20) # define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index eaa8f6b..4fa6ddd 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -27,6 +27,7 @@ void baytrail_init_pre_device(void); void baytrail_init_cpus(device_t dev); void set_max_freq(void); +void southcluster_enable_dev(device_t dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 0f686fa..eedae39 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -53,13 +53,17 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(device_t dev) { - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } } } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 32b8799..761b7c6 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <arch/io.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -29,6 +30,7 @@ #include <baytrail/lpc.h> #include <baytrail/nvs.h> #include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> #include <baytrail/ramstage.h> static inline void @@ -113,12 +115,276 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +/* + * Common code for the south cluster devices. + */ + +/* Set bit in function disble register to hide this device. */ +static void sc_disable_devfn(device_t dev) +{ + const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; + const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t mask = 0; + uint32_t mask2 = 0; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + mask |= SDIO_DIS; + break; + case PCI_DEVFN(SD_DEV, SD_FUNC): + mask |= SD_DIS; + break; + case PCI_DEVFN(SATA_DEV, SATA_FUNC): + mask |= SATA_DIS; + break; + case PCI_DEVFN(XHCI_DEV, XHCI_FUN): + mask |= XHCI_DIS; + /* Disable super speed PHY when XHCI is not available. */ + mask2 |= USH_SS_PHY_DIS: + break; + case PCI_DEVFN(LPE_DEV, LPE_FUNC): + mask |= LPE_DIS; + break; + case PCI_DEVFN(MMC_DEV, MMC_FUNC): + mask |= MMC_DIS; + break; + case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): + mask |= SIO_DMA1_DIS; + break; + case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): + mask |= I2C1_DIS; + break; + case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): + mask |= I2C1_DIS; + break; + case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): + mask |= I2C3_DIS; + break; + case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): + mask |= I2C4_DIS; + break; + case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): + mask |= I2C5_DIS; + break; + case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): + mask |= I2C6_DIS; + break; + case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): + mask |= I2C7_DIS; + break; + case PCI_DEVFN(TXE_DEV, TXE_FUNC): + mask |= TXE_DIS; + break; + case PCI_DEVFN(HDA_DEV, HDA_FUNC): + mask |= HDA_DIS; + break; + case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): + mask |= PCIE_PORT1_DIS; + break; + case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): + mask |= PCIE_PORT2_DIS; + break; + case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): + mask |= PCIE_PORT3_DIS; + break; + case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + mask |= PCIE_PORT4_DIS; + break; + case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): + mask |= EHCI_DIS; + break; + case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): + mask |= SIO_DMA2_DIS; + break; + case PCI_DEVFN(PWM1_DEV, PM1_FUNC): + mask |= PWM1_DIS; + break; + case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): + mask |= PWM2_DIS; + break; + case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): + mask |= HSUART1_DIS; + break; + case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): + mask |= HSUART2_DIS; + break; + case PCI_DEVFN(SPI_DEV, SPI_FUNC): + mask |= SPI_DIS; + break; + case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): + mask2 |= SMBUS_DIS; + break; + } + + if (mask != 0) { + write32(func_dis, read32(func_dis) | mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (mask2 != 0) { + write32(func_dis2, read32(func_dis2) | mask2); + /* Ensure posted write hits. */ + read32(func_dis2); + } +} + +static inline void set_d3hot_bits(device_t dev, int offset) +{ + uint32_t reg8; + printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); + reg8 = pci_read_config8(dev, offset + 4); + reg8 |= 0x3; + pci_write_config8(dev, offset + 4, reg8); +} + +static int place_device_in_d3hot(device_t dev) +{ + unsigned offset; + + offset = pci_find_capability(dev, PCI_CAP_ID_PM); + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + /* For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. */ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SD_DEV, SD_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(MMC_DEV, MMC_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(LPE_DEV, LPE_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SPI_DEV, SPI_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SATA_DEV, SATA_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(HDA_DEV, HDA_FUNC): + offset = 0x50; + break; + case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): + offset = 0x50; + break; + case PCI_DEVFN(TXE_DEV, TXE_FUNC): + break; + case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + offset = 0xa0; + break; + } + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + return -1; +} + +/* Common PCI device function disable. */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Place device in D3Hot */ + if (place_device_in_d3hot(dev) < 0) { + printk(BIOS_WARNING, + "Could not place %02x.%01x into D3Hot. " + "Keeping device visible.\n", slot, func); + return; + } + /* Disable this device if possible */ + sc_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, .init = NULL, - .enable = NULL, + .enable = southcluster_enable_dev, .scan_bus = NULL, .ops_pci = &soc_pci_ops, };

1 0

Patch set updated for coreboot: 6c49095 coreboot: remove unused get_lb_mem() function
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5304 -gerrit commit 6c49095e7400746a0679018a19a11ca58bc74c35 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 00:24:22 2014 -0600 coreboot: remove unused get_lb_mem() function The get_lb_mem() is no longer used. Therefore, remove it. Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 5 ----- src/lib/coreboot_table.c | 15 +-------------- 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 9b87f3d..c4ad572 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -338,11 +338,6 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - void fill_lb_gpios(struct lb_gpios *gpios); #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index cb7179d..667c685 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -354,18 +354,6 @@ static unsigned long lb_table_fini(struct lb_header *head) return (unsigned long)rec + rec->size; } -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementation. - */ -static struct lb_memory *mem_ranges = NULL; - -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) @@ -430,8 +418,7 @@ unsigned long write_coreboot_table( /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ - mem_ranges = lb_memory(head); - bootmem_write_memory_table(mem_ranges); + bootmem_write_memory_table(lb_memory(head)); /* Record our motherboard */ lb_mainboard(head);

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coreboot-gerrit February 2014