coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

New patch to review for coreboot: 2cb3e3b lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode
by Duncan Laurie 11 Feb '14

11 Feb '14

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5193 -gerrit commit 2cb3e3b828285dc7b390d7af1a2917bb9fa6af3f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Feb 11 10:34:06 2014 -0800 lynxpoint: Do not put SerialIO devices into D3Hot in ACPI mode Remove the bit of code that was putting the SerialIO devices into D3Hot state when they are switched from PCI to ACPI mode. Instead, add the appropriate ACPI Methods to allow the kernel to control the power state of the device. The problem seems to be that if the device is put in D3Hot state before it is switched from PCI to ACPI mode then it does not properly export its PCI configuration space and cannot be woken back up. Adding the ACPI Methods for _PS0/_PS3 allows the kernel to transition the device into D0 state only when it is necessary to communicate with the device, then put it back into D3Hot state. Change-Id: I2384ba10bf47750d1c1a35216169ddeee26881df Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 44 +++++++++++++++++++++++ src/southbridge/intel/lynxpoint/serialio.c | 10 ------ 2 files changed, 44 insertions(+), 10 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 4c0d36b..59228d6 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -211,6 +211,28 @@ Device (I2C0) Return (0xF) } } + + // Access to PCI Config in ACPI mode + OperationRegion (KEYS, SystemMemory, \S1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, Preserve) + { + Offset (0x84), + PSAT, 32, + } + + // Put controller in D0 state + Method (_PS0, 0, Serialized) + { + And (^PSAT, 0xfffffffc, ^PSAT) + Store (^PSAT, Local0) + } + + // Put controller in D3Hot state + Method (_PS3, 0, Serialized) + { + Or (^PSAT, 0x00000003, ^PSAT) + Store (^PSAT, Local0) + } } Device (I2C1) @@ -262,6 +284,28 @@ Device (I2C1) Return (0xF) } } + + // Access to PCI Config in ACPI mode + OperationRegion (KEYS, SystemMemory, \S2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, Preserve) + { + Offset (0x84), + PSAT, 32, + } + + // Put controller in D0 state + Method (_PS0, 0, Serialized) + { + And (^PSAT, 0xfffffffc, ^PSAT) + Store (^PSAT, Local0) + } + + // Put controller in D3Hot state + Method (_PS3, 0, Serialized) + { + Or (^PSAT, 0x00000003, ^PSAT) + Store (^PSAT, Local0) + } } Device (SPI0) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 8257cc2..75edf5c 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -29,14 +29,6 @@ #include "pch.h" #include "nvs.h" -/* Set D3Hot Power State in ACPI mode */ -static void serialio_enable_d3hot(struct device *dev) -{ - u32 reg32 = pci_read_config32(dev, PCH_PCS); - reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); -} - /* Enable clock in PCI mode */ static void serialio_enable_clock(struct resource *bar0) { @@ -178,8 +170,6 @@ static void serialio_init(struct device *dev) if (!config->sio_acpi_mode) serialio_enable_clock(bar0); - else if (dev->path.pci.devfn != PCI_DEVFN(21, 0)) - serialio_enable_d3hot(dev); /* all but SDMA */ switch (dev->path.pci.devfn) { case PCI_DEVFN(21, 0): /* SDMA */

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Patch set updated for coreboot: 0a92c8a Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5177 -gerrit commit 0a92c8a84e246d31884e91339ce4b7a1e1eb4e78 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 9 14:50:50 2014 -0600 Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs" This reverts commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce. This commit changed the board status script to describe all boards in terms of x86 terminology, such as CPU->southbridge->northbridge. This terminology does not apply to a number of SoCs, in which the buses are not connected via successive bridges, and as such it is misleading and misguided to describe ideas of southbridge and northbridge for these devices. Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 675b5d5..5d2c6b0 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -224,8 +224,6 @@ EOF case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" - northbridge_nice="Allwinner A10" - southbridge_nice="Allwinner A10" socket_nice="?";; AMD_GEODE_*) cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; @@ -274,32 +272,22 @@ EOF socket_nice="Socket 939" ;; AMD_SC520) - cpu_nice="AMD Élan™ SC520"; - northbridge_nice="AMD Élan™ SC520"; - southbridge_nice="AMD Élan™ SC520"; + cpu_nice="AMD Élan™SC520"; socket_nice="—";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; - northbridge_nice="ARM Cortex A9"; - southbridge_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; - northbridge_nice="Samsung Exynos 5420"; - southbridge_nice="Samsung Exynos 5420"; socket_nice="?";; SAMSUNG_EXYNOS5250) cpu_nice="Samsung Exynos 5250"; - northbridge_nice="Samsung Exynos 5250"; - southbridge_nice="Samsung Exynos 5250"; socket_nice="?";; TI_AM335X) cpu_nice="TI AM335X"; - southbridge_nice="TI AM335X"; - northbridge_nice="TI AM335X"; socket_nice="?";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; @@ -390,16 +378,6 @@ EOF socket_nice="$cpu";; esac - if [ x"$northbridge_nice" = x ]; then - if grep 'select SOC_INTEL_BAYTRAIL' "$vendor_board_dir/Kconfig" > /dev/null ; then - southbridge_nice="Intel® Baytrail" - northbridge_nice="Intel® Baytrail" - cpu_nice="Intel® Baytrail" - socket_nice="—" - fi - fi - - echo "|- bgcolor=\"#$color\"" echo "| $vendor_nice" echo -n "| [[Board:$vendor/$board|$board_nice]]"

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Patch set updated for coreboot: 506d618 option: Add arch-agnostic get_option()
by Kyösti Mälkki 11 Feb '14

11 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5157 -gerrit commit 506d618593e55911ea1be2d7dcf581522923dd24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 10:02:53 2014 +0200 option: Add arch-agnostic get_option() We should not have pc80/ includes in UARTs or generally in lib/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 13 +------------ src/console/uart8250_console.c | 1 - src/console/uart8250mem_console.c | 1 - src/include/option.h | 19 +++++++++++++++++++ src/lib/uart8250.c | 2 +- src/lib/uart8250mem.c | 2 +- src/mainboard/intel/jarrell/watchdog.c | 1 + 7 files changed, 23 insertions(+), 16 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index a31e293..83db91c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -25,18 +25,7 @@ #ifndef __PRE_RAM__ #include <string.h> #include <types.h> - -/* - * FIXME: get_option() needs to be abstracted better so that other non-volatile - * storage can be used. This will benefit machines without CMOS as well as those - * without a battery-backed CMOS (e.g. some laptops). - */ -#if CONFIG_USE_OPTION_TABLE -#include <pc80/mc146818rtc.h> -#else -static inline enum cb_err get_option(void *dest, const char *name) - { return CB_CMOS_OTABLE_DISABLED; } -#endif +#include <option.h> /* initialize the console */ void console_init(void) diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..196412c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static void ttyS0_init(void) { diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0; diff --git a/src/include/option.h b/src/include/option.h new file mode 100644 index 0000000..83f3a84 --- /dev/null +++ b/src/include/option.h @@ -0,0 +1,19 @@ +#ifndef _OPTION_H_ +#define _OPTION_H_ + +/* + * FIXME: get_option() needs to be abstracted better so that other non-volatile + * storage can be used. This will benefit machines without CMOS as well as those + * without a battery-backed CMOS (e.g. some laptops). + */ +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#else +#include <types.h> +static inline enum cb_err get_option(void *dest, const char *name) +{ + return CB_CMOS_OTABLE_DISABLED; +} +#endif + +#endif /* _OPTION_H_ */ diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index aa18d2a..b253ea4 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <trace.h> #if CONFIG_USE_OPTION_TABLE diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..c2298a8 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..7f7a039 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -1,4 +1,5 @@ #include <device/pnp_def.h> +#include <pc80/mc146818rtc.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) #define NSC_WDBASE 0x600

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Patch set updated for coreboot: 02e0d68 nvram: Add arch-agnostic get_option()
by Kyösti Mälkki 11 Feb '14

11 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5157 -gerrit commit 02e0d68d1f4a3ecd9023f6ef2693ea62c3221022 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 10:02:53 2014 +0200 nvram: Add arch-agnostic get_option() We should not have pc80/ includes in UARTs or generally in lib/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 13 +------------ src/console/uart8250_console.c | 1 - src/console/uart8250mem_console.c | 1 - src/include/option.h | 19 +++++++++++++++++++ src/lib/uart8250.c | 2 +- src/lib/uart8250mem.c | 2 +- src/mainboard/intel/jarrell/watchdog.c | 1 + 7 files changed, 23 insertions(+), 16 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index a31e293..83db91c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -25,18 +25,7 @@ #ifndef __PRE_RAM__ #include <string.h> #include <types.h> - -/* - * FIXME: get_option() needs to be abstracted better so that other non-volatile - * storage can be used. This will benefit machines without CMOS as well as those - * without a battery-backed CMOS (e.g. some laptops). - */ -#if CONFIG_USE_OPTION_TABLE -#include <pc80/mc146818rtc.h> -#else -static inline enum cb_err get_option(void *dest, const char *name) - { return CB_CMOS_OTABLE_DISABLED; } -#endif +#include <option.h> /* initialize the console */ void console_init(void) diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..196412c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static void ttyS0_init(void) { diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0; diff --git a/src/include/option.h b/src/include/option.h new file mode 100644 index 0000000..83f3a84 --- /dev/null +++ b/src/include/option.h @@ -0,0 +1,19 @@ +#ifndef _OPTION_H_ +#define _OPTION_H_ + +/* + * FIXME: get_option() needs to be abstracted better so that other non-volatile + * storage can be used. This will benefit machines without CMOS as well as those + * without a battery-backed CMOS (e.g. some laptops). + */ +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#else +#include <types.h> +static inline enum cb_err get_option(void *dest, const char *name) +{ + return CB_CMOS_OTABLE_DISABLED; +} +#endif + +#endif /* _OPTION_H_ */ diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index aa18d2a..b253ea4 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <trace.h> #if CONFIG_USE_OPTION_TABLE diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..c2298a8 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..7f7a039 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -1,4 +1,5 @@ #include <device/pnp_def.h> +#include <pc80/mc146818rtc.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) #define NSC_WDBASE 0x600

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Patch set updated for coreboot: 8c768d6 nvram: Add arch-agnostic get_option()
by Kyösti Mälkki 11 Feb '14

11 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5157 -gerrit commit 8c768d60d813d4c63a8ec876c619d131bf2d692a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 10:02:53 2014 +0200 nvram: Add arch-agnostic get_option() We should not have pc80/ includes in UARTs or generally in lib/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 13 +------------ src/console/uart8250_console.c | 1 - src/console/uart8250mem_console.c | 1 - src/include/nvram.h | 19 +++++++++++++++++++ src/lib/uart8250.c | 2 +- src/lib/uart8250mem.c | 2 +- src/mainboard/intel/jarrell/watchdog.c | 1 + 7 files changed, 23 insertions(+), 16 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index a31e293..83db91c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -25,18 +25,7 @@ #ifndef __PRE_RAM__ #include <string.h> #include <types.h> - -/* - * FIXME: get_option() needs to be abstracted better so that other non-volatile - * storage can be used. This will benefit machines without CMOS as well as those - * without a battery-backed CMOS (e.g. some laptops). - */ -#if CONFIG_USE_OPTION_TABLE -#include <pc80/mc146818rtc.h> -#else -static inline enum cb_err get_option(void *dest, const char *name) - { return CB_CMOS_OTABLE_DISABLED; } -#endif +#include <option.h> /* initialize the console */ void console_init(void) diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..196412c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static void ttyS0_init(void) { diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0; diff --git a/src/include/nvram.h b/src/include/nvram.h new file mode 100644 index 0000000..83f3a84 --- /dev/null +++ b/src/include/nvram.h @@ -0,0 +1,19 @@ +#ifndef _OPTION_H_ +#define _OPTION_H_ + +/* + * FIXME: get_option() needs to be abstracted better so that other non-volatile + * storage can be used. This will benefit machines without CMOS as well as those + * without a battery-backed CMOS (e.g. some laptops). + */ +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#else +#include <types.h> +static inline enum cb_err get_option(void *dest, const char *name) +{ + return CB_CMOS_OTABLE_DISABLED; +} +#endif + +#endif /* _OPTION_H_ */ diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index aa18d2a..b253ea4 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <trace.h> #if CONFIG_USE_OPTION_TABLE diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..c2298a8 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..7f7a039 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -1,4 +1,5 @@ #include <device/pnp_def.h> +#include <pc80/mc146818rtc.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) #define NSC_WDBASE 0x600

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New patch to review for coreboot: 39051bc intel/fsp_sandybridge/acpi/sandybridge.asl: Increase range length of buffer to 0x8000
by Paul Menzel 11 Feb '14

11 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5192 -gerrit commit 39051bc1d37a1922e0d68d00c0ff93d2e3582b3b Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Feb 11 10:38:27 2014 +0100 intel/fsp_sandybridge/acpi/sandybridge.asl: Increase range length of buffer to 0x8000 Linux kernel 2.6.31 reports the following warning. resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01 Indeed `src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl` contains OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) so instead of 256 kB specify that 512 kB are decoded in that memory range. Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f Reported-by: Norwich in #coreboot on <irc.freenode.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl index 7d51135..e6012ff 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl @@ -30,7 +30,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)

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Patch set updated for coreboot: 8cf9223 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4
by Paul Menzel 11 Feb '14

11 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit 8cf9223e84dd3f3bd3dc48e30e5a75ce0e8e6fe5 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/external/SeaBIOS: Upgrade stable from 1.7.2.2 to 1.7.4 On Monday, 12/23/2013, 12:34 -0500 Kevin O'Connor wrote: > The 1.7.4 version of SeaBIOS has now been released. For more > information on the release, please see: > > http://seabios.org/Releases > > > New in this release: > > * Support for obtaining ACPI tables directly from QEMU. > * Initial support for XHCI USB controllers (initially for QEMU only). > * Support for booting from "pvscsi" devices on QEMU. > * Enhanced floppy driver - improved support for real hardware. > * coreboot cbmem console support. > * Optional support for using the 9-segment instead of the e-segment > for local variables. > * Improved internal timer code and accuracy. > * SeaVGABIOS improvements > * Better support for legacy X.org releases with incomplete x86emu > emulation. > * Support for using an internal stack to reduce caller's stack > usage. > * Back port of new "bochs dispi" interface video modes. > * Several bug fixes and code cleanups > * Source code separated out into additional hardware and firmware > directories. > * Update to latest version of Kconfig > > > For information on obtaining SeaBIOS, please see: > > http://seabios.org/Download Successfully tested on the Asus M2V-MX SE. ----- [ SeaBIOS rel-1.7.4-0-g96917a8-20140201_152655-my-asus-m2v-mx_se ] ----- Found coreboot cbmem console @ 7dec0400 Found mainboard ASUS M2V-MX SE Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- src/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..291b166 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -617,7 +617,7 @@ choice depends on PAYLOAD_SEABIOS config SEABIOS_STABLE - bool "1.7.2.1" + bool "1.7.4" help Stable SeaBIOS version config SEABIOS_MASTER

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Patch set updated for coreboot: 16fdec8 cubieboard: Enable the SD controller and mux SD pins
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4745 -gerrit commit 16fdec8d35f6568f1fd510d4cf4f4e5bd6edfc16 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Dec 28 15:10:28 2013 -0500 cubieboard: Enable the SD controller and mux SD pins This step needs to be done before calling any MMC functionality. Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/clock.h | 10 ++++++++++ src/mainboard/cubietech/cubieboard/bootblock.c | 15 +++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/src/cpu/allwinner/a10/clock.h b/src/cpu/allwinner/a10/clock.h index 0be736c..0a9cfd6 100644 --- a/src/cpu/allwinner/a10/clock.h +++ b/src/cpu/allwinner/a10/clock.h @@ -66,6 +66,16 @@ /* DRAM_CLK values*/ #define DRAM_CTRL_DCLK_OUT (1 << 15) +/* SDx_CLK values */ +#define SDx_CLK_GATE (1 << 31) +#define SDx_CLK_SRC_MASK (3 << 24) +#define SDx_CLK_SRC_OSC24M (0 << 24) +#define SDx_CLK_SRC_PLL6 (1 << 24) +#define SDx_CLK_SRC_PLL5 (2 << 24) +#define SDx_RAT_EXP_N_MASK (3 << 16) +#define SDx_RAT_EXP_N(n) (((n) << 16) & SDx_RAT_EXP_N_MASK) +#define SDx_RAT_M_MASK (0xf << 0) +#define SDx_RAT_M(m) ((((m) - 1) << 0) & SDx_RAT_M_MASK) /** * \brief Clock gating definitions * diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 2e5929c..c994c57 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -27,6 +27,10 @@ #define GPB_UART0_FUNC 2 #define GPB_UART0_PINS ((1 << 22) | (1 << 23)) +#define GPF_SD0_FUNC 2 +#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */ +#define GPH1_SD0_DET_FUNC 5 + static void cubieboard_set_sys_clock(void) { u32 reg32; @@ -60,6 +64,13 @@ static void cubieboard_setup_clocks(void) write32(APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0), &ccm->apb1_clk_div_cfg); + /* Configure the clock for SD0 */ + write32(SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) + | SDx_RAT_M(1), &ccm->sd0_clk_cfg); + + /* Enable clock to SD0 */ + a1x_periph_clock_enable(A1X_CLKEN_MMC0); + } static void cubieboard_setup_gpios(void) @@ -71,6 +82,10 @@ static void cubieboard_setup_gpios(void) /* Mux UART pins */ gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC); + + /* Mux SD pins */ + gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC); + gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC); } static void cubieboard_enable_uart(void)

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Patch set updated for coreboot: 76009e3 cpu/allwinner/a10: Add minimal ramstage driver
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4698 -gerrit commit 76009e3a111241d76b8bb5b6312340dc621195cf Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 3 04:24:35 2014 -0500 cpu/allwinner/a10: Add minimal ramstage driver Change-Id: I857755976b17b0e492c086162f395a77933eeed8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 3 +++ src/cpu/allwinner/a10/cbmem.c | 26 +++++++++++++++++++++ src/cpu/allwinner/a10/chip.h | 11 +++++++++ src/cpu/allwinner/a10/cpu.c | 48 ++++++++++++++++++++++++++++++++++++++ src/cpu/allwinner/a10/ram_segs.h | 30 ++++++++++++++++++++++++ 5 files changed, 118 insertions(+) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 1b720bf..a86d719 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -8,6 +8,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c +romstage-y += cbmem.c romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c @@ -16,7 +17,9 @@ romstage-y += uart.c romstage-y += uart_console.c ramstage-y += bootblock_media.c +ramstage-y += cbmem.c ramstage-y += clock.c +ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c diff --git a/src/cpu/allwinner/a10/cbmem.c b/src/cpu/allwinner/a10/cbmem.c new file mode 100644 index 0000000..c6a6502 --- /dev/null +++ b/src/cpu/allwinner/a10/cbmem.c @@ -0,0 +1,26 @@ +/* + * Provides cbmem utilities for romstage and ramstage + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "ram_segs.h" +#include <cbmem.h> + +#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) + +void *cbmem_top(void) +{ + return a1x_get_cbmem_top(); +} + +#else + +void get_cbmem_table(u64 *base, u64 *size) +{ + *size = CONFIG_COREBOOT_TABLES_SIZE; + *base = (unsigned)a1x_get_cbmem_top() - CONFIG_COREBOOT_TABLES_SIZE; +} + +#endif diff --git a/src/cpu/allwinner/a10/chip.h b/src/cpu/allwinner/a10/chip.h new file mode 100644 index 0000000..16f60c0 --- /dev/null +++ b/src/cpu/allwinner/a10/chip.h @@ -0,0 +1,11 @@ +/* + * Allwinnwer A10 devicetree config struct + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> + +struct cpu_allwinner_a10_config { +}; diff --git a/src/cpu/allwinner/a10/cpu.c b/src/cpu/allwinner/a10/cpu.c new file mode 100644 index 0000000..e0d4cdf --- /dev/null +++ b/src/cpu/allwinner/a10/cpu.c @@ -0,0 +1,48 @@ +/* + * Ramstage initialization for Allwinner CPUs + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <console/console.h> +#include <device/device.h> +#include <cpu/cpu.h> +#include <cbmem.h> + + +static void cpu_enable_resources(device_t dev) +{ + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE >> 10, + CONFIG_DRAM_SIZE_MB << 10); + /* TODO: Declare CBFS cache as reserved? There's no guarantee we won't + * overwrite it. It seems to stay intact, being so high in RAM + */ +} + +static void cpu_init(device_t dev) +{ + /* TODO: Check if anything else needs to be explicitly initialized */ +} + +static void cpu_noop(device_t dev) +{ +} + +static struct device_operations cpu_ops = { + .read_resources = cpu_noop, + .set_resources = cpu_noop, + .enable_resources = cpu_enable_resources, + .init = cpu_init, + .scan_bus = NULL, +}; + +static void a1x_cpu_enable_dev(device_t dev) +{ + dev->ops = &cpu_ops; +} + +struct chip_operations cpu_allwinner_a10_ops = { + CHIP_NAME("CPU Allwinner A10") + .enable_dev = a1x_cpu_enable_dev, +}; diff --git a/src/cpu/allwinner/a10/ram_segs.h b/src/cpu/allwinner/a10/ram_segs.h new file mode 100644 index 0000000..45141fe --- /dev/null +++ b/src/cpu/allwinner/a10/ram_segs.h @@ -0,0 +1,30 @@ +/* + * How we use DRAM on Allwinner CPUs + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <config.h> + +/* + * Put CBMEM at top of RAM + */ +static inline void *a1x_get_cbmem_top(void) +{ + return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20); +} + +/* + * By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region. + */ +static inline void *a1x_get_cbfs_cache_top(void) +{ + /* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */ + return a1x_get_cbmem_top() - (16 << 20); +} + +static inline void *a1x_get_cbfs_cache_base(void) +{ + return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE; +}

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Patch set updated for coreboot: 98fd240 fintek/f81865f: Deprecate the C inclusion of early_serial.c
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4807 -gerrit commit 98fd240b92a4d9d7acabfde6817e7cb8f8be5075 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Jan 25 09:40:54 2014 -0600 fintek/f81865f: Deprecate the C inclusion of early_serial.c Including "early_serial.c" directly in romstage.c rather than compiling and linking it is a remnant of ROMCC. Modernize this by declaring "early_serial.c" as a Makefile.inc object, and no longer use it by direct inclusion. Change-Id: I40a6646fedaad5371983bfc6e6e990c4932ec9bd Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/amd/persimmon/romstage.c | 2 +- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/via/epia-m850/Makefile.inc | 22 +---------- src/mainboard/via/epia-m850/romstage.c | 4 +- src/superio/fintek/f81865f/Makefile.inc | 1 + src/superio/fintek/f81865f/early_serial.c | 48 +++++++++++++++++++++++ src/superio/fintek/f81865f/f81865f.h | 2 + src/superio/fintek/f81865f/f81865f_early_serial.c | 47 ---------------------- 8 files changed, 56 insertions(+), 72 deletions(-) diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 98c64ed..e082f60 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -31,7 +31,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 20c973c..5614f88 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,7 +32,7 @@ #include <cpu/x86/mtrr.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/via/epia-m850/Makefile.inc b/src/mainboard/via/epia-m850/Makefile.inc index 9c6d31f..e9a0b69 100644 --- a/src/mainboard/via/epia-m850/Makefile.inc +++ b/src/mainboard/via/epia-m850/Makefile.inc @@ -1,21 +1 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> -## -## This program is free software: you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation, either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program. If not, see <http://www.gnu.org/licenses/>. -## - -#romstage-y += ./../../../superio/fintek/f81865f/f81865f_early_serial.c - +# Nothing interesting here yet diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 262bee7..1114cf4 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -33,11 +33,11 @@ #include <string.h> #include <timestamp.h> #include <console/cbmem_console.h> +#include <superio/fintek/f81865f/f81865f.h> #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" -/* FIXME: This is the only .c include we couldn't get rid of */ -#include "superio/fintek/f81865f/f81865f_early_serial.c" + #define SERIAL_DEV PNP_DEV(0x4e, 0x10) diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index 1700f7c..8afb286 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/early_serial.c b/src/superio/fintek/f81865f/early_serial.c new file mode 100644 index 0000000..29b5f9d --- /dev/null +++ b/src/superio/fintek/f81865f/early_serial.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ + +#include <arch/io.h> +#include <device/pnp.h> +#include "f81865f.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void f81865f_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 0c36571..7269b59 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -35,4 +35,6 @@ #define F81865F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F81865F_PME 0x0a /* Power Management Events (PME) */ +void f81865f_enable_serial(device_t dev, u16 iobase); + #endif diff --git a/src/superio/fintek/f81865f/f81865f_early_serial.c b/src/superio/fintek/f81865f/f81865f_early_serial.c deleted file mode 100644 index 2989b5f..0000000 --- a/src/superio/fintek/f81865f/f81865f_early_serial.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Pre-RAM driver for the Fintek F81865F/FG Super I/O chip. */ - -#include <arch/io.h> -#include "f81865f.h" - -static void pnp_enter_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_conf_state(device_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -static void f81865f_enable_serial(device_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -}

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coreboot-gerrit February 2014