coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 402a3e5 google mainboards: Guard APCI TPM Device with CONFIG_CHROMEOS
by Duncan Laurie 10 Feb '14

10 Feb '14

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5184 -gerrit commit 402a3e5fd834941008430ec0851b8914cba5fdc0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Feb 10 12:17:30 2014 -0800 google mainboards: Guard APCI TPM Device with CONFIG_CHROMEOS The TPM is currently only configured/enabled/used if CONFIG_CHROMEOS is enabled, but the ACPI TPM device is defined always. If CONFIG_CHROMEOS is not defined then the Linux kernel will timeout trying to talk to the TPM on resume because it expects a defined TPM to be sent the TPM Resume command before returning to the OS. Change-Id: Ia1e88d52b94e74b0011810db24b114c1c7ff0cd8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/bolt/dsdt.asl | 2 ++ src/mainboard/google/falco/dsdt.asl | 2 ++ src/mainboard/google/peppy/dsdt.asl | 2 ++ src/mainboard/google/rambi/dsdt.asl | 2 ++ src/mainboard/google/slippy/dsdt.asl | 2 ++ 5 files changed, 10 insertions(+) diff --git a/src/mainboard/google/bolt/dsdt.asl b/src/mainboard/google/bolt/dsdt.asl index 1316ebf..d976e7c 100644 --- a/src/mainboard/google/bolt/dsdt.asl +++ b/src/mainboard/google/bolt/dsdt.asl @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_CHROMEOS #define ENABLE_TPM +#endif DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/google/falco/dsdt.asl b/src/mainboard/google/falco/dsdt.asl index 1316ebf..d976e7c 100644 --- a/src/mainboard/google/falco/dsdt.asl +++ b/src/mainboard/google/falco/dsdt.asl @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_CHROMEOS #define ENABLE_TPM +#endif DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/google/peppy/dsdt.asl b/src/mainboard/google/peppy/dsdt.asl index 1316ebf..d976e7c 100644 --- a/src/mainboard/google/peppy/dsdt.asl +++ b/src/mainboard/google/peppy/dsdt.asl @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_CHROMEOS #define ENABLE_TPM +#endif DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 172aaf4..3ebb60a 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_CHROMEOS #define ENABLE_TPM +#endif DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 1316ebf..d976e7c 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#if CONFIG_CHROMEOS #define ENABLE_TPM +#endif DefinitionBlock( "dsdt.aml",

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New patch to review for coreboot: c7e5fed haswell: Fix compile when early console is disabled
by Duncan Laurie 10 Feb '14

10 Feb '14

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5183 -gerrit commit c7e5fedb87470999d0f4236fd893f79cad001f2e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Feb 10 11:43:26 2014 -0800 haswell: Fix compile when early console is disabled The System Agent binary can be passed a pointer to the console transmit byte function, but if the early console feature is disabled then the function is not defined. Change-Id: I46b84b42491b911f832a089c094b0724ca9ebe97 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/northbridge/intel/haswell/raminit.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 316f7fd..15cc22f 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -165,8 +165,10 @@ void sdram_initialize(struct pei_data *pei_data) } } +#if CONFIG_EARLY_CONSOLE /* Pass console handler in pei_data */ pei_data->tx_byte = console_tx_byte; +#endif /* Locate and call UEFI System Agent binary. */ entry = (unsigned long)cbfs_get_file_content(

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New patch to review for coreboot: 7414c5f lynxpoint: Fix SerialIO ACPI compile issue with recent IASL
by Duncan Laurie 10 Feb '14

10 Feb '14

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5182 -gerrit commit 7414c5f6e8bb9e585f6f604143c1d21732c69d47 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Feb 10 11:37:45 2014 -0800 lynxpoint: Fix SerialIO ACPI compile issue with recent IASL The SerialIO DwordIo() definition is fixed up before returning it in the serialio device _CRS method, so the values that are set in the raw ASL are not actually used. However modern versions of IASL do not like that the RangeLength is set to zero and will fail to compile. Set this value to 1 to make IASL stop complaining, but the real value is still fixed up in _CRS so this has no real effect on the end result. Change-Id: Iceb888e54dd4d627c12d078915108a11f45b1a2d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 4c0d36b..697548e 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -498,7 +498,7 @@ Device (GPIO) 0x00000000, // AddressMinimum 0x00000000, // AddressMaximum 0x00000000, // AddressTranslation - 0x00000000, // RangeLength + 0x00000001, // RangeLength , // ResourceSourceIndex , // ResourceSource BAR0)

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New patch to review for coreboot: 01fddb1 lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS
by Duncan Laurie 10 Feb '14

10 Feb '14

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5181 -gerrit commit 01fddb11d492d00dfc8b1f42e6969838ad6db04d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Feb 10 11:34:27 2014 -0800 lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS The Chrome OS environment sends an SMI to finalize the chipset/board at the end of the "depthcharge" payload, but there is no facility to send this command if not using the full ChromeOS firmware stack. This commit adds a callback before booting the payload that will issue this SMI which will lock down the chipset and route USB devices to the XHCI controller. Change-Id: I2db9c44d61ebf8fa28a8a2b260a63d4aa4d75842 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/southbridge/intel/lynxpoint/smi.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 75c3e66..af40eaf 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ - +#include <bootstate.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> @@ -124,3 +124,20 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) "d" (APM_CNT) ); } + +/* + * Finalize system before payload boot if not in ChromeOS environment. + */ +#if !CONFIG_CHROMEOS + +static void finalize_boot(void *unused) +{ + outb(0xcb, 0xb2); +} + +BOOT_STATE_INIT_ENTRIES(finalize) = { + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, + finalize_boot, NULL), +}; + +#endif

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New patch to review for coreboot: d0b3fbe haswell: Fix issues building without CONFIG_CHROMEOS
by Duncan Laurie 10 Feb '14

10 Feb '14

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5180 -gerrit commit d0b3fbe8ff4cc3abff39cc4b13ca0bc6cce2ca9a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Feb 10 11:33:01 2014 -0800 haswell: Fix issues building without CONFIG_CHROMEOS There are some places that make assumptions about ChromeOS and/or Verified Boot environment and should be guarded with an appropriate #ifdef CONFIG_CHROMEOS. Without this change builds will fail if CONFIG_CHROMEOS is not defined. Change-Id: I4077e19e4dc0cdbfa35c9b92ea9a1ed3c5483fdc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/cpu/intel/haswell/romstage.c | 2 ++ src/ec/google/chromeec/ec.c | 5 ++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..c28cfed 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,7 +309,9 @@ void romstage_after_car(void) prepare_for_resume(handoff); +#if CONFIG_CHROMEOS vboot_verify_firmware(handoff); +#endif /* Load the ramstage. */ copy_and_run(); diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index f1cefae..d512cec 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -113,6 +113,7 @@ void google_chromeec_early_init(void) cec_cmd.cmd_size_out = sizeof(cec_resp); google_chromeec_command(&cec_cmd); +#if CONFIG_CHROMEOS if (cec_cmd.cmd_code || (recovery_mode_enabled() && (cec_resp.current_image != EC_IMAGE_RO))) { @@ -131,6 +132,7 @@ void google_chromeec_early_init(void) hard_reset(); hlt(); } +#endif } u16 google_chromeec_get_board_version(void) @@ -394,6 +396,7 @@ void google_chromeec_init(void) ec_image_type = cec_resp.current_image; } +#if CONFIG_CHROMEOS if (cec_cmd.cmd_code || (recovery_mode_enabled() && (cec_resp.current_image != EC_IMAGE_RO))) { @@ -412,7 +415,7 @@ void google_chromeec_init(void) hard_reset(); hlt(); } - +#endif } int google_ec_running_ro(void)

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Patch set updated for coreboot: 9cd47c2 payloads/seabios: Upgrade stable from 1.7.2.2 to 1.7.4
by Alexandru Gagniuc 10 Feb '14

10 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5093 -gerrit commit 9cd47c2958c72a3856e43f834b27016951b8f83e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 11:23:26 2014 +0100 payloads/seabios: Upgrade stable from 1.7.2.2 to 1.7.4 Successfully tested on the Asus M2V-MX SE. Change-Id: I675a50532735b4921a664e4b24d98be17b9a1002 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/external/SeaBIOS/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 84f1515..23b064c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +TAG-$(CONFIG_SEABIOS_STABLE)=96917a8ed761f017fc8c72ba3b9181fbac03ac59 unexport KCONFIG_AUTOCONFIG

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Patch merged into coreboot/master: a0cabe9 usbdebug: Split PCI EHCI part
by gerrit＠coreboot.org 10 Feb '14

10 Feb '14

the following patch was just integrated into master: commit a0cabe945ecc455dc1cc5be77adb20b8e623723b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 7 19:24:23 2014 +0200 usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5175 for details. -gerrit

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Patch merged into coreboot/master: 97ae5bd usbdebug: Fix data toggle on receive
by gerrit＠coreboot.org 10 Feb '14

10 Feb '14

the following patch was just integrated into master: commit 97ae5bd0e871cb5af7957336973144f9b73b0de3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 21 10:44:08 2014 +0200 usbdebug: Fix data toggle on receive USB device end toggles data PID when we ACK'd the zero-length data packet. As USB host we need to toggle data PID too or the next data received would get discarded. Change-Id: I3203bc874c7ded9244c7548a666d7041a0fbb379 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4775 for details. -gerrit

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Patch merged into coreboot/master: 42bf709 usbdebug: Remove duplicate port claim
by gerrit＠coreboot.org 10 Feb '14

10 Feb '14

the following patch was just integrated into master: commit 42bf709756f132b654bab64700606cca0aa2678d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 18 12:26:13 2014 +0200 usbdebug: Remove duplicate port claim This claim is useless when done before EHCI controller reset. Code in usbdebug_init_() already sets this properly after reset, see use of DBGP_OWNER. Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4709 for details. -gerrit

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Patch merged into coreboot/master: 023dbab usbdebug: Improve receive speed
by gerrit＠coreboot.org 10 Feb '14

10 Feb '14

the following patch was just integrated into master: commit 023dbabc458b13441a54bcea7f3bc433c1dd7de2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jan 15 22:26:03 2014 +0200 usbdebug: Improve receive speed Read from USB endpoint_in 8 bytes at a time, the maximum what EHCI debug port capability has to offer. Change-Id: I3d012d758a24b24f894e587b301f620933331407 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4700 for details. -gerrit

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coreboot-gerrit February 2014