coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: a71d224 device_util: Make device in dev_find_slot_pnp u16.
by gerrit＠coreboot.org 09 Feb '14

09 Feb '14

the following patch was just integrated into master: commit a71d2247991583fe559e98c3dbed6b75e9b2da3c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 8 18:58:39 2014 +0100 device_util: Make device in dev_find_slot_pnp u16. LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field. Increase to 16-bit to handle this. Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5165 for details. -gerrit

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Patch set updated for coreboot: 4ac4178 NOTFORMERGE: lenovo/t60: Enable Infrared port.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5174 -gerrit commit 4ac4178d199be45959b4b84710789b5992ec150a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 9 12:34:02 2014 +0100 NOTFORMERGE: lenovo/t60: Enable Infrared port. Change-Id: I4d49ee83c8135de503dcfb84b950f98c2a2306c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/acpi/superio.asl | 16 ++++++++++++++++ src/mainboard/lenovo/t60/devicetree.cb | 3 +++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl index e69de29..a0d8e0a 100644 --- a/src/mainboard/lenovo/t60/acpi/superio.asl +++ b/src/mainboard/lenovo/t60/acpi/superio.asl @@ -0,0 +1,16 @@ + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..63e10dd 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -148,6 +148,9 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + irq 0xf0 = 0x82 end device pnp 164e.3 off # Serial Port

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Patch set updated for coreboot: e5ba1b4 NOTFORMERGE: lenovo/x60: Enable Infrared port.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5170 -gerrit commit e5ba1b4c2019812e882f2efce121a02e42bdd93f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 9 02:17:26 2014 +0100 NOTFORMERGE: lenovo/x60: Enable Infrared port. Change-Id: I251031086dd5ac012e3dc2e8fed816a8ca629f15 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x60/devicetree.cb | 3 +++ 2 files changed, 21 insertions(+) diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl index 4e994ba..ddba679 100644 --- a/src/mainboard/lenovo/x60/acpi/superio.asl +++ b/src/mainboard/lenovo/x60/acpi/superio.asl @@ -15,6 +15,24 @@ } } + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + #if IS_ENABLED(CONFIG_BOARD_LENOVO_X60T) Device (DTR) // Digitizer { diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 5b4e37f..2388917 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -125,6 +125,9 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + irq 0xf0 = 0x82 end device pnp 164e.3 on # Digitizer

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Patch set updated for coreboot: a71d224 device_util: Make device in dev_find_slot_pnp u16.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5165 -gerrit commit a71d2247991583fe559e98c3dbed6b75e9b2da3c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 8 18:58:39 2014 +0100 device_util: Make device in dev_find_slot_pnp u16. LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field. Increase to 16-bit to handle this. Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/device_util.c | 2 +- src/include/device/device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 83decc1..dc43b9a 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -100,7 +100,7 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) * @param device Logical device number. * @return Pointer to the device structure (if found), 0 otherwise. */ -struct device *dev_find_slot_pnp(u16 port, u8 device) +struct device *dev_find_slot_pnp(u16 port, u16 device) { struct device *dev; diff --git a/src/include/device/device.h b/src/include/device/device.h index f05ddea..74bdbd7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -169,7 +169,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); -device_t dev_find_slot_pnp(u16 port, u8 device); +device_t dev_find_slot_pnp(u16 port, u16 device); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void);

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Patch set updated for coreboot: 3bfa7b0 lenovo/x60: Support digitizer on X60T variant.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5113 -gerrit commit 3bfa7b0d831ca46d56ec99a5e8991d950186d69c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Feb 4 15:01:04 2014 +0100 lenovo/x60: Support digitizer on X60T variant. Change-Id: If2e699cfa5d11f2cb2b9c254fc6fc71781dce228 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x60/Kconfig | 6 +++++- src/mainboard/lenovo/x60/acpi/superio.asl | 34 +++++++++++++++++++++++++++++++ src/mainboard/lenovo/x60/devicetree.cb | 7 +++++-- src/mainboard/lenovo/x60/mainboard.c | 5 +++++ src/mainboard/lenovo/x60t/Kconfig | 10 +++++++++ src/mainboard/lenovo/x60t/board_info.txt | 7 +++++++ 7 files changed, 72 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..b16ef7d 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -12,6 +12,11 @@ config BOARD_LENOVO_X60 ThinkPad X60s (Model 1702, 1703) ThinkPad X60 (Model 1709) +config BOARD_LENOVO_X60T + bool "ThinkPad X60 Tablet" + help + Lenovo X60 convertible tablet + config BOARD_LENOVO_X201 bool "ThinkPad X201" help @@ -33,6 +38,7 @@ config BOARD_LENOVO_T60 endchoice source "src/mainboard/lenovo/x60/Kconfig" +source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..36c00bc 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X60 +if BOARD_LENOVO_X60 || BOARD_LENOVO_X60T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -39,10 +39,14 @@ config DCACHE_RAM_SIZE hex default 0x8000 +if BOARD_LENOVO_X60 + config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +endif + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl index e69de29..4e994ba 100644 --- a/src/mainboard/lenovo/x60/acpi/superio.asl +++ b/src/mainboard/lenovo/x60/acpi/superio.asl @@ -0,0 +1,34 @@ + Device (COMA) // Serial + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x3f8, 0x3f8, 0x01, 0x08) + IRQNoFlags () {4} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X60T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..5b4e37f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -127,8 +127,11 @@ chip northbridge/intel/i945 io 0x60 = 0x2f8 end - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 end device pnp 164e.7 on # GPIO diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index d1fcb7b..be39674 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -150,8 +150,13 @@ static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *curre static void mainboard_enable(device_t dev) { + device_t devwacom; dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X60T); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x60t/Kconfig b/src/mainboard/lenovo/x60t/Kconfig new file mode 100644 index 0000000..57c99ca --- /dev/null +++ b/src/mainboard/lenovo/x60t/Kconfig @@ -0,0 +1,10 @@ +if BOARD_LENOVO_X60T + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad X60 Tablet" + +endif diff --git a/src/mainboard/lenovo/x60t/board_info.txt b/src/mainboard/lenovo/x60t/board_info.txt new file mode 100644 index 0000000..6ecdbd5 --- /dev/null +++ b/src/mainboard/lenovo/x60t/board_info.txt @@ -0,0 +1,7 @@ +Board name: X60 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lenovo/x60

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Patch set updated for coreboot: d256ba8 lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096 -gerrit commit d256ba8b9518a5b46c78794d9093bf1b6f606862 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 1 18:39:26 2014 +0100 lenovo/x201: Support digitizer on x201t variant Since ACPI declaration of Wacom tablet when there is none causes hangs, split x201 port to x201 and x201t. Thanks to Peter Stuge for his helpful insights Thanks to Carl-Daniel Hailfinger for info on PnP superio. Thanks to Jens Erat for letting me to experiment with his X201t. Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/acpi/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 4 ++-- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 6 +++++- src/mainboard/lenovo/x201/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 14 ++++++++++++++ src/mainboard/lenovo/x201/mainboard.c | 12 ++++++++++-- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201t/Kconfig | 22 ++++++++++++++++++++++ src/mainboard/lenovo/x201t/board_info.txt | 6 ++++++ 11 files changed, 86 insertions(+), 7 deletions(-) diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..3b5712b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_X201T) += ec.c diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 4b3fb12..9e983f0 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -227,7 +227,7 @@ Device(EC) ^HKEY.RHK (0x18) } -#if CONFIG_BOARD_LENOVO_X201 +#if CONFIG_BOARD_LENOVO_X201 || CONFIG_BOARD_LENOVO_X201T Method (_Q1C, 0, NotSerialized) { ^HKEY.RHK (0x19) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..cecf520 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,6 +1,6 @@ Scope(\_TZ) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) Name (MEBT, 0) #endif @@ -24,7 +24,7 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED (CONFIG_BOARD_LENOVO_X201T) /* Avoid tripping alarm if ME isn't booted at all yet */ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { Return (C2K(40)) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index b16ef7d..55dbb05 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X201T + bool "ThinkPad X201 Tablet" + help + Lenovo X201 convertible tablet. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -40,6 +45,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x201t/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..344aa40 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X201 +if BOARD_LENOVO_X201 || BOARD_LENOVO_X201T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -23,6 +23,8 @@ config MAINBOARD_DIR string default lenovo/x201 +if BOARD_LENOVO_X201 + config MAINBOARD_PART_NUMBER string default "3626EN1" @@ -31,6 +33,8 @@ config MAINBOARD_VERSION string default "ThinkPad X201" +endif + config MAINBOARD_VENDOR string default "LENOVO" diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..19bb4c5 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,19 @@ #include "../../../../drivers/pc80/ps2_controller.asl" + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..0b978de 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..775583a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -90,7 +90,11 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "Lenovo X201"; +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + return "ThinkPad X201 Tablet"; +#else + return "ThinkPad X201"; +#endif } /* Audio Setup */ @@ -106,7 +110,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, devwacom; u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -153,6 +157,10 @@ static void mainboard_enable(device_t dev) if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X201T); + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f0874d3..9b99c4e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x201t/Kconfig b/src/mainboard/lenovo/x201t/Kconfig new file mode 100644 index 0000000..45e30a2 --- /dev/null +++ b/src/mainboard/lenovo/x201t/Kconfig @@ -0,0 +1,22 @@ +if BOARD_LENOVO_X201T + +config TABLET_SPECIFIC_OPTIONS # dummy + def_bool y + select SUPERIO_NSC_PC87382 + # Following ones are for scripts benefit + select ARCH_X86 + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + +config MAINBOARD_PART_NUMBER + string + default "0831CTO" + +config MAINBOARD_VERSION + string + default "ThinkPad X201 Tablet" + +endif diff --git a/src/mainboard/lenovo/x201t/board_info.txt b/src/mainboard/lenovo/x201t/board_info.txt new file mode 100644 index 0000000..6a168fe --- /dev/null +++ b/src/mainboard/lenovo/x201t/board_info.txt @@ -0,0 +1,6 @@ +Board name: X201 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n

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Patch merged into coreboot/master: 05efa9e mtrr: only add prefetchable resources as WRCOMB for VGA devices
by gerrit＠coreboot.org 09 Feb '14

09 Feb '14

the following patch was just integrated into master: commit 05efa9e58f2488fa611257c6296d10f20d06bca0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Feb 8 15:41:52 2014 -0600 mtrr: only add prefetchable resources as WRCOMB for VGA devices Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory was added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function is added to provide additional filtering on device and resource. Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5169 for details. -gerrit

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Patch set updated for coreboot: 05efa9e mtrr: only add prefetchable resources as WRCOMB for VGA devices
by Aaron Durbin 09 Feb '14

09 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5169 -gerrit commit 05efa9e58f2488fa611257c6296d10f20d06bca0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Feb 8 15:41:52 2014 -0600 mtrr: only add prefetchable resources as WRCOMB for VGA devices Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory was added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function is added to provide additional filtering on device and resource. Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 19 +++++++++++++++++-- src/include/memrange.h | 13 +++++++++++++ src/lib/memrange.c | 19 +++++++++++++++---- 3 files changed, 45 insertions(+), 6 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..d85a869 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -30,6 +30,7 @@ #include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_ids.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -154,6 +155,20 @@ static inline int range_entry_mtrr_type(struct range_entry *r) return range_entry_tag(r) & MTRR_TAG_MASK; } +static int filter_vga_wrcomb(struct device *dev, struct resource *res) +{ + /* Only handle PCI devices. */ + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + + /* Only handle VGA class devices. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return 0; + + /* Add resource as write-combining in the address space. */ + return 1; +} + static struct memranges *get_physical_address_space(void) { static struct memranges *addr_space; @@ -181,8 +196,8 @@ static struct memranges *get_physical_address_space(void) * resources are appropriate for this MTRR type. */ match = IORESOURCE_PREFETCH; mask |= match; - memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB, + filter_vga_wrcomb); #if CONFIG_CACHE_ROM /* Add a write-protect region covering the ROM size diff --git a/src/include/memrange.h b/src/include/memrange.h index 4f094f5..ba85bef 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -94,6 +94,19 @@ void memranges_add_resources(struct memranges *ranges, unsigned long mask, unsigned long match, unsigned long tag); +/* Add memory resources that match with the corresponding mask and match but + * also provide filter as additional check. The filter will return non-zero + * to add the resource or zero to not add the resource. Each entry will be + * tagged with the provided tag. e.g. To populate all cacheable memory + * resources in the range with a filter: + * memranges_add_resources_filter(range, IORESOURCE_CACHEABLE, + * IORESROUCE_CACHEABLE, my_cacheable_tag, filter); */ +typedef int (*memrange_filter_t)(struct device *dev, struct resource *res); +void memranges_add_resources_filter(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag, + memrange_filter_t filter); + /* Fill all address ranges up to limit (exclusive) not covered by an entry by * inserting new entries with the provided tag. */ void memranges_fill_holes_up_to(struct memranges *ranges, diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 7fb6ef7..a85bc01 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -252,6 +252,7 @@ void memranges_insert(struct memranges *ranges, struct collect_context { struct memranges *ranges; unsigned long tag; + memrange_filter_t filter; }; static void collect_ranges(void *gp, struct device *dev, struct resource *res) @@ -261,12 +262,14 @@ static void collect_ranges(void *gp, struct device *dev, struct resource *res) if (res->size == 0) return; - memranges_insert(ctx->ranges, res->base, res->size, ctx->tag); + if (ctx->filter == NULL || ctx->filter(dev, res)) + memranges_insert(ctx->ranges, res->base, res->size, ctx->tag); } -void memranges_add_resources(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) +void memranges_add_resources_filter(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag, + memrange_filter_t filter) { struct collect_context context; @@ -276,9 +279,17 @@ void memranges_add_resources(struct memranges *ranges, context.ranges = ranges; context.tag = tag; + context.filter = filter; search_global_resources(mask, match, collect_ranges, &context); } +void memranges_add_resources(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag) +{ + memranges_add_resources_filter(ranges, mask, match, tag, NULL); +} + void memranges_init(struct memranges *ranges, unsigned long mask, unsigned long match, unsigned long tag)

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New patch to review for coreboot: fcb54bf Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
by Alexandru Gagniuc 09 Feb '14

09 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5177 -gerrit commit fcb54bf3f32cbbd020444118c9c8d241f929f652 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 9 14:50:50 2014 -0600 Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs" This reverts commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce. This commit changed the board status script to describe all boards in terms of x86 terminology, such as CPU->southbridge->northbridge. This terminology does not apply to a number of SoCs, in which the buses are not connected via successive bridges, and as such it is misleading and misguided to describe ideas of southbridge and northbridge for these devices. Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 675b5d5..5d2c6b0 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -224,8 +224,6 @@ EOF case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" - northbridge_nice="Allwinner A10" - southbridge_nice="Allwinner A10" socket_nice="?";; AMD_GEODE_*) cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; @@ -274,32 +272,22 @@ EOF socket_nice="Socket 939" ;; AMD_SC520) - cpu_nice="AMD Élan™ SC520"; - northbridge_nice="AMD Élan™ SC520"; - southbridge_nice="AMD Élan™ SC520"; + cpu_nice="AMD Élan™SC520"; socket_nice="—";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; - northbridge_nice="ARM Cortex A9"; - southbridge_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; - northbridge_nice="Samsung Exynos 5420"; - southbridge_nice="Samsung Exynos 5420"; socket_nice="?";; SAMSUNG_EXYNOS5250) cpu_nice="Samsung Exynos 5250"; - northbridge_nice="Samsung Exynos 5250"; - southbridge_nice="Samsung Exynos 5250"; socket_nice="?";; TI_AM335X) cpu_nice="TI AM335X"; - southbridge_nice="TI AM335X"; - northbridge_nice="TI AM335X"; socket_nice="?";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; @@ -390,16 +378,6 @@ EOF socket_nice="$cpu";; esac - if [ x"$northbridge_nice" = x ]; then - if grep 'select SOC_INTEL_BAYTRAIL' "$vendor_board_dir/Kconfig" > /dev/null ; then - southbridge_nice="Intel® Baytrail" - northbridge_nice="Intel® Baytrail" - cpu_nice="Intel® Baytrail" - socket_nice="—" - fi - fi - - echo "|- bgcolor=\"#$color\"" echo "| $vendor_nice" echo -n "| [[Board:$vendor/$board|$board_nice]]"

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Patch set updated for coreboot: 7d173c0 usbdebug: Remove EHCI_DEBUG_OFFSET
by Kyösti Mälkki 09 Feb '14

09 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5176 -gerrit commit 7d173c01f578d2741cd8791005ffe262c804d71e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 9 19:21:30 2014 +0200 usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 9 ++++++--- src/drivers/usb/ehci_debug.h | 2 +- src/drivers/usb/pci_ehci.c | 32 +++++++++++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/Kconfig | 4 ---- src/southbridge/amd/cimx/sb700/Kconfig | 4 ---- src/southbridge/amd/cimx/sb800/Kconfig | 4 ---- src/southbridge/amd/sb600/Kconfig | 4 ---- src/southbridge/amd/sb700/Kconfig | 4 ---- src/southbridge/amd/sb800/Kconfig | 4 ---- src/southbridge/intel/bd82x6x/Kconfig | 4 ---- src/southbridge/intel/fsp_bd82x6x/Kconfig | 4 ---- src/southbridge/intel/i82801dx/Kconfig | 4 ---- src/southbridge/intel/i82801ex/Kconfig | 4 ---- src/southbridge/intel/i82801gx/Kconfig | 4 ---- src/southbridge/intel/i82801ix/Kconfig | 4 ---- src/southbridge/intel/ibexpeak/Kconfig | 4 ---- src/southbridge/intel/lynxpoint/Kconfig | 4 ---- src/southbridge/intel/sch/Kconfig | 4 ---- src/southbridge/nvidia/ck804/Kconfig | 4 ---- src/southbridge/nvidia/mcp55/Kconfig | 4 ---- src/southbridge/sis/sis966/Kconfig | 3 --- 21 files changed, 37 insertions(+), 77 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 26d61fb..beb553e 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -588,6 +588,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ int port_map_tried; int playtimes = 3; + dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset); + ehci_caps = (struct ehci_caps *)ehci_bar; ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); @@ -608,7 +610,6 @@ try_next_port: debug_port = HCS_DEBUG_PORT(hcs_params); n_ports = HCS_N_PORTS(hcs_params); - dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar); dprintk(BIOS_INFO, "debug_port: %d\n", debug_port); dprintk(BIOS_INFO, "n_ports: %d\n", n_ports); @@ -985,11 +986,13 @@ struct dbgp_pipe *dbgp_console_input(void) int usbdebug_init(void) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); + unsigned int ehci_base, dbg_offset; #if !defined(__PRE_RAM__) && !defined(__SMM__) if (!get_usbdebug_from_cbmem(dbg_info)) return 0; #endif - ehci_debug_hw_enable(); - return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); + if (ehci_debug_hw_enable(&ehci_base, &dbg_offset)) + return -1; + return usbdebug_init_(ehci_base, dbg_offset, dbg_info); } diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index 462eb23..2e549d2 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -24,7 +24,7 @@ void usbdebug_re_enable(unsigned ehci_base); void usbdebug_disable(void); -void ehci_debug_hw_enable(void); +int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset); void ehci_debug_select_port(unsigned int port); #endif /* _EHCI_DEBUG_H_ */ diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 7c715f6..b7b7df1 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -34,12 +34,40 @@ static struct device_operations *ehci_drv_ops; static struct device_operations ehci_dbg_ops; #endif -void ehci_debug_hw_enable(void) +int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { -#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); + +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = dbg_dev; +#else + device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev)); #endif + + u16 status = pci_read_config16(dev, PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 1; + + /* Scan capabilities list. */ + u8 pos = pci_read_config8(dev, PCI_CAPABILITY_LIST); + int i; + for (i=0; pos >= 0x40 && i < 48; i++) { + u32 cap = pci_read_config32(dev, pos); + if ((u8) cap != PCI_CAP_ID_EHCI_DEBUG) { + pos = (cap >> 8) & 0xfc; + continue; + } + + /* FIXME: We should remove static EHCI_BAR_INDEX. */ + u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1); + if (dbg_bar != EHCI_BAR_INDEX) + break; + *base = CONFIG_EHCI_BAR; + *dbg_offset = (cap>>16) & 0x1ffc; + return 0; + } + return 1; } void ehci_debug_select_port(unsigned int port) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 1550cb4..dd5120d 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -43,10 +43,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" default y diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 4304357..d8bad86 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -54,10 +54,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb700/bootblock.c" diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 37aff9e..832655d 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -209,10 +209,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - choice prompt "Fan Control" default SB800_NO_FAN_CONTROL diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index fe9468d..4d5fff4 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -32,10 +32,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - choice prompt "SATA Mode" default SATA_MODE_IDE diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index b0c92dc..e391fc8 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -45,8 +45,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - endif # SOUTHBRIDGE_AMD_SB700 diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 9547d3e..24dc007 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -37,8 +37,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - endif # SOUTHBRIDGE_AMD_SB800 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index d060dae..9cfa5d5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,10 +41,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 1a8e80a..b2b4929 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -37,10 +37,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/fsp_bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index f7f93a7..8ef778f 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -33,8 +33,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x80 - endif diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig index e4e9160..caa5c79 100644 --- a/src/southbridge/intel/i82801ex/Kconfig +++ b/src/southbridge/intel/i82801ex/Kconfig @@ -11,8 +11,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - endif diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 62c6b43..777b69b 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -32,10 +32,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801gx/bootblock.c" diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8a4a53e..493be60 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -33,10 +33,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801ix/bootblock.c" diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 97d5883..c05fe43 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -39,10 +39,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..bfb7b73 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -44,10 +44,6 @@ config EHCI_BAR hex default 0xe8000000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/lynxpoint/bootblock.c" diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index 432fb8d..d320a53 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -30,10 +30,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config HAVE_CMC bool "Add a CMC state machine binary" help diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index b6f718e..e21f79e 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -14,10 +14,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x98 - config CK804_USE_NIC bool default n diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..89aa452 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -14,10 +14,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x98 - config MCP55_USE_NIC bool default n diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..1fbd57d 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -12,6 +12,3 @@ config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 -config EHCI_DEBUG_OFFSET - hex - default 0x98 if SOUTHBRIDGE_SIS_SIS966

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coreboot-gerrit February 2014