coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d74bd07 mtrr: only add prefetchable resources as WRCOMB for VGA devices
by Aaron Durbin 08 Feb '14

08 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5168 -gerrit commit d74bd07cb3f2d277880599d471f2fadddc38831e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Feb 8 15:41:52 2014 -0600 mtrr: only add prefetchable resources as WRCOMB for VGA devices Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Previously all prefetchable memory as added as a write-combining memory type. Some hardware incorrectly advertises its BAR as prefetchable when it shouldn't be. A new memranges_add_resources_filter() function was added to provide additional filtering on device and resource. Change-Id: Id3d54a573a75b883286ef47759fbffa922b4a791 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 19 +++++++++++++++++-- src/include/memrange.h | 13 +++++++++++++ src/lib/memrange.c | 18 ++++++++++++++---- 3 files changed, 44 insertions(+), 6 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..d85a869 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -30,6 +30,7 @@ #include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_ids.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -154,6 +155,20 @@ static inline int range_entry_mtrr_type(struct range_entry *r) return range_entry_tag(r) & MTRR_TAG_MASK; } +static int filter_vga_wrcomb(struct device *dev, struct resource *res) +{ + /* Only handle PCI devices. */ + if (dev->path.type != DEVICE_PATH_PCI) + return 0; + + /* Only handle VGA class devices. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return 0; + + /* Add resource as write-combining in the address space. */ + return 1; +} + static struct memranges *get_physical_address_space(void) { static struct memranges *addr_space; @@ -181,8 +196,8 @@ static struct memranges *get_physical_address_space(void) * resources are appropriate for this MTRR type. */ match = IORESOURCE_PREFETCH; mask |= match; - memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB, + filter_vga_wrcomb); #if CONFIG_CACHE_ROM /* Add a write-protect region covering the ROM size diff --git a/src/include/memrange.h b/src/include/memrange.h index 4f094f5..ba85bef 100644 --- a/src/include/memrange.h +++ b/src/include/memrange.h @@ -94,6 +94,19 @@ void memranges_add_resources(struct memranges *ranges, unsigned long mask, unsigned long match, unsigned long tag); +/* Add memory resources that match with the corresponding mask and match but + * also provide filter as additional check. The filter will return non-zero + * to add the resource or zero to not add the resource. Each entry will be + * tagged with the provided tag. e.g. To populate all cacheable memory + * resources in the range with a filter: + * memranges_add_resources_filter(range, IORESOURCE_CACHEABLE, + * IORESROUCE_CACHEABLE, my_cacheable_tag, filter); */ +typedef int (*memrange_filter_t)(struct device *dev, struct resource *res); +void memranges_add_resources_filter(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag, + memrange_filter_t filter); + /* Fill all address ranges up to limit (exclusive) not covered by an entry by * inserting new entries with the provided tag. */ void memranges_fill_holes_up_to(struct memranges *ranges, diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 7fb6ef7..f0ff865 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -261,12 +261,14 @@ static void collect_ranges(void *gp, struct device *dev, struct resource *res) if (res->size == 0) return; - memranges_insert(ctx->ranges, res->base, res->size, ctx->tag); + if (ctx->filter == NULL || ctx->filter(dev, res)) + memranges_insert(ctx->ranges, res->base, res->size, ctx->tag); } -void memranges_add_resources(struct memranges *ranges, - unsigned long mask, unsigned long match, - unsigned long tag) +void memranges_add_resources_filter(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag, + memrange_filter_t filter) { struct collect_context context; @@ -276,9 +278,17 @@ void memranges_add_resources(struct memranges *ranges, context.ranges = ranges; context.tag = tag; + context.filter = filter; search_global_resources(mask, match, collect_ranges, &context); } +void memranges_add_resources(struct memranges *ranges, + unsigned long mask, unsigned long match, + unsigned long tag) +{ + memranges_add_resources_filter(ranges, mask, match, tag, NULL); +} + void memranges_init(struct memranges *ranges, unsigned long mask, unsigned long match, unsigned long tag)

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Patch set updated for coreboot: fe423d5 mtrr: only add prefetchable resources as WRCOMB for VGA devices
by Aaron Durbin 08 Feb '14

08 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5168 -gerrit commit fe423d57f9f87696d3bc0e2f387e02b85771a734 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Feb 8 15:41:52 2014 -0600 mtrr: only add prefetchable resources as WRCOMB for VGA devices Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Change-Id: Id3d54a573a75b883286ef47759fbffa922b4a791 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..6835d9a 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -30,6 +30,7 @@ #include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci_ids.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -154,6 +155,22 @@ static inline int range_entry_mtrr_type(struct range_entry *r) return range_entry_tag(r) & MTRR_TAG_MASK; } +static void add_vga_wrcomb(void *gp, struct device *dev, struct resource *res) +{ + struct memranges *addr_space = gp; + + /* Only handle PCI devices. */ + if (dev->path.type != DEVICE_PATH_PCI) + return; + + /* Only handle VGA class devices. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + /* Add resource as write-combining in the address space. */ + memranges_insert(addr_space, res->base, res->size, MTRR_TYPE_WRCOMB); +} + static struct memranges *get_physical_address_space(void) { static struct memranges *addr_space; @@ -181,8 +198,7 @@ static struct memranges *get_physical_address_space(void) * resources are appropriate for this MTRR type. */ match = IORESOURCE_PREFETCH; mask |= match; - memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + search_global_resources(mask, match, add_vga_wrcomb, addr_space); #if CONFIG_CACHE_ROM /* Add a write-protect region covering the ROM size

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New patch to review for coreboot: d0b4a1d mtrr: only add prefetchable resources as WRCOMB for VGA devices
by Aaron Durbin 08 Feb '14

08 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5168 -gerrit commit d0b4a1d220b706e512adfdf60090fac9b840ba93 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Feb 8 15:41:52 2014 -0600 mtrr: only add prefetchable resources as WRCOMB for VGA devices Be more conservative and only add VGA devices' prefetchable resources as write-combining in the address space. Change-Id: Id3d54a573a75b883286ef47759fbffa922b4a791 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/mtrr/mtrr.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..ab9e5b2 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -154,6 +154,22 @@ static inline int range_entry_mtrr_type(struct range_entry *r) return range_entry_tag(r) & MTRR_TAG_MASK; } +static void add_vga_wrcomb(void *gp, struct device *dev, struct resource *res) +{ + struct memranges *addr_space = gp; + + /* Only handle PCI devices. */ + if (dev->path.type != DEVICE_PATH_PCI) + return; + + /* Only handle VGA class devices. */ + if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) + return; + + /* Add resource as write-combining in the address space. */ + memranges_insert(add_space, res->base, res->size, MTRR_TYPE_WRCOMB); +} + static struct memranges *get_physical_address_space(void) { static struct memranges *addr_space; @@ -181,8 +197,7 @@ static struct memranges *get_physical_address_space(void) * resources are appropriate for this MTRR type. */ match = IORESOURCE_PREFETCH; mask |= match; - memranges_add_resources(addr_space, mask, match, - MTRR_TYPE_WRCOMB); + search_global_resources(mask, match, add_vga_wrcomb, addr_space); #if CONFIG_CACHE_ROM /* Add a write-protect region covering the ROM size

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Patch set updated for coreboot: f797a19 lenovo/x60: Support digitizer on X60T variant.
by Vladimir Serbinenko 08 Feb '14

08 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5113 -gerrit commit f797a19998c281bfd3c65c0571698d5c9b853271 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Feb 4 15:01:04 2014 +0100 lenovo/x60: Support digitizer on X60T variant. Change-Id: If2e699cfa5d11f2cb2b9c254fc6fc71781dce228 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x60/Kconfig | 6 +++++- src/mainboard/lenovo/x60/acpi/superio.asl | 17 +++++++++++++++++ src/mainboard/lenovo/x60/devicetree.cb | 7 +++++-- src/mainboard/lenovo/x60/mainboard.c | 5 +++++ src/mainboard/lenovo/x60t/Kconfig | 10 ++++++++++ src/mainboard/lenovo/x60t/board_info.txt | 7 +++++++ 7 files changed, 55 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..b16ef7d 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -12,6 +12,11 @@ config BOARD_LENOVO_X60 ThinkPad X60s (Model 1702, 1703) ThinkPad X60 (Model 1709) +config BOARD_LENOVO_X60T + bool "ThinkPad X60 Tablet" + help + Lenovo X60 convertible tablet + config BOARD_LENOVO_X201 bool "ThinkPad X201" help @@ -33,6 +38,7 @@ config BOARD_LENOVO_T60 endchoice source "src/mainboard/lenovo/x60/Kconfig" +source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..36c00bc 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X60 +if BOARD_LENOVO_X60 || BOARD_LENOVO_X60T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -39,10 +39,14 @@ config DCACHE_RAM_SIZE hex default 0x8000 +if BOARD_LENOVO_X60 + config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +endif + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl index e69de29..31ffb7b 100644 --- a/src/mainboard/lenovo/x60/acpi/superio.asl +++ b/src/mainboard/lenovo/x60/acpi/superio.asl @@ -0,0 +1,17 @@ +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X60T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..5b4e37f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -127,8 +127,11 @@ chip northbridge/intel/i945 io 0x60 = 0x2f8 end - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 end device pnp 164e.7 on # GPIO diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index d1fcb7b..be39674 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -150,8 +150,13 @@ static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *curre static void mainboard_enable(device_t dev) { + device_t devwacom; dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X60T); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x60t/Kconfig b/src/mainboard/lenovo/x60t/Kconfig new file mode 100644 index 0000000..57c99ca --- /dev/null +++ b/src/mainboard/lenovo/x60t/Kconfig @@ -0,0 +1,10 @@ +if BOARD_LENOVO_X60T + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad X60 Tablet" + +endif diff --git a/src/mainboard/lenovo/x60t/board_info.txt b/src/mainboard/lenovo/x60t/board_info.txt new file mode 100644 index 0000000..6ecdbd5 --- /dev/null +++ b/src/mainboard/lenovo/x60t/board_info.txt @@ -0,0 +1,7 @@ +Board name: X60 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lenovo/x60

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Patch set updated for coreboot: ee43be7 lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 08 Feb '14

08 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096 -gerrit commit ee43be73e997625ff2da145ccc1cbc64a2dfa285 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 1 18:39:26 2014 +0100 lenovo/x201: Support digitizer on x201t variant Since ACPI declaration of Wacom tablet when there is none causes hangs, split x201 port to x201 and x201t. Thanks to Peter Stuge for his helpful insights Thanks to Carl-Daniel Hailfinger for info on PnP superio. Thanks to Jens Erat for letting me to experiment with his X201t. Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/acpi/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 4 ++-- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 6 +++++- src/mainboard/lenovo/x201/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 14 ++++++++++++++ src/mainboard/lenovo/x201/mainboard.c | 12 ++++++++++-- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201t/Kconfig | 22 ++++++++++++++++++++++ src/mainboard/lenovo/x201t/board_info.txt | 6 ++++++ 11 files changed, 86 insertions(+), 7 deletions(-) diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..3b5712b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_X201T) += ec.c diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 4b3fb12..9e983f0 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -227,7 +227,7 @@ Device(EC) ^HKEY.RHK (0x18) } -#if CONFIG_BOARD_LENOVO_X201 +#if CONFIG_BOARD_LENOVO_X201 || CONFIG_BOARD_LENOVO_X201T Method (_Q1C, 0, NotSerialized) { ^HKEY.RHK (0x19) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..cecf520 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,6 +1,6 @@ Scope(\_TZ) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) Name (MEBT, 0) #endif @@ -24,7 +24,7 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED (CONFIG_BOARD_LENOVO_X201T) /* Avoid tripping alarm if ME isn't booted at all yet */ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { Return (C2K(40)) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index b16ef7d..55dbb05 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X201T + bool "ThinkPad X201 Tablet" + help + Lenovo X201 convertible tablet. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -40,6 +45,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x201t/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..344aa40 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X201 +if BOARD_LENOVO_X201 || BOARD_LENOVO_X201T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -23,6 +23,8 @@ config MAINBOARD_DIR string default lenovo/x201 +if BOARD_LENOVO_X201 + config MAINBOARD_PART_NUMBER string default "3626EN1" @@ -31,6 +33,8 @@ config MAINBOARD_VERSION string default "ThinkPad X201" +endif + config MAINBOARD_VENDOR string default "LENOVO" diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..19bb4c5 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,19 @@ #include "../../../../drivers/pc80/ps2_controller.asl" + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..0b978de 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..775583a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -90,7 +90,11 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "Lenovo X201"; +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + return "ThinkPad X201 Tablet"; +#else + return "ThinkPad X201"; +#endif } /* Audio Setup */ @@ -106,7 +110,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, devwacom; u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -153,6 +157,10 @@ static void mainboard_enable(device_t dev) if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X201T); + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f0874d3..9b99c4e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x201t/Kconfig b/src/mainboard/lenovo/x201t/Kconfig new file mode 100644 index 0000000..45e30a2 --- /dev/null +++ b/src/mainboard/lenovo/x201t/Kconfig @@ -0,0 +1,22 @@ +if BOARD_LENOVO_X201T + +config TABLET_SPECIFIC_OPTIONS # dummy + def_bool y + select SUPERIO_NSC_PC87382 + # Following ones are for scripts benefit + select ARCH_X86 + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + +config MAINBOARD_PART_NUMBER + string + default "0831CTO" + +config MAINBOARD_VERSION + string + default "ThinkPad X201 Tablet" + +endif diff --git a/src/mainboard/lenovo/x201t/board_info.txt b/src/mainboard/lenovo/x201t/board_info.txt new file mode 100644 index 0000000..6a168fe --- /dev/null +++ b/src/mainboard/lenovo/x201t/board_info.txt @@ -0,0 +1,6 @@ +Board name: X201 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n

1 0

New patch to review for coreboot: 78a421a NOTFORMERGE: lenovo/x201: Fix order of SPI init.
by Vladimir Serbinenko 08 Feb '14

08 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5167 -gerrit commit 78a421a772cefb1b9ca4a8f36768cdf481c8a289 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 8 19:00:54 2014 +0100 NOTFORMERGE: lenovo/x201: Fix order of SPI init. The lock bit for UVSVC/LVSVC was set before both registers were programmed. Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..628c872 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -128,9 +128,9 @@ static void mainboard_enable(device_t dev) RCBA32(0x389c) = 0x0601209f; RCBA32(0x38b0) = 0x00000004; RCBA32(0x38b4) = 0x03040002; - RCBA32(0x38c0) = 0x00000007; - RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; RCBA32(0x3804) = 0x3f04e008; printk(BIOS_SPEW, "SPI configured\n");

1 0

New patch to review for coreboot: 0066538 NOTFORMERGE: lenovo/x201: change to new mp code.
by Vladimir Serbinenko 08 Feb '14

08 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5166 -gerrit commit 006653880ffc18ba1d80ea325a5f6a455ab07172 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 8 19:00:14 2014 +0100 NOTFORMERGE: lenovo/x201: change to new mp code. Change-Id: Ia596e493f7314b9435ae8b03f7888bf828488eb2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/devicetree.cb | 9 ++++ src/mainboard/lenovo/x201/mptable.c | 83 +-------------------------------- 2 files changed, 10 insertions(+), 82 deletions(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..daccbbb 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -146,6 +146,15 @@ chip northbridge/intel/nehalem device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x2167 # eeprom, 8 virtual devices, same chip + chip drivers/generic/ioapic + register "have_isa_interrupts" = "1" + register "irq_on_fsb" = "1" + register "enable_virtual_wire" = "1" + register "base" = "0xfec00000" + register "version" = "0x20" + device ioapic 2 on end + end + chip drivers/i2c/at24rf08c device i2c 54 on end device i2c 55 on end diff --git a/src/mainboard/lenovo/x201/mptable.c b/src/mainboard/lenovo/x201/mptable.c index 84364a0..f1839f0 100644 --- a/src/mainboard/lenovo/x201/mptable.c +++ b/src/mainboard/lenovo/x201/mptable.c @@ -1,82 +1 @@ -/* generated by MPTable, version 2.0.15*/ -/* as modified by RGM for coreboot */ -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -#define INTA 0x00 -#define INTB 0x01 -#define INTC 0x02 -#define INTD 0x03 - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int isa_bus; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - /* I/O APICs: APIC ID Version State Address */ - smp_write_ioapic(mc, 0x2, 0x20, 0xfec00000); - - mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); - - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0, - 0x2, 0x0); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x1, 0x2, 0x1); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x0, 0x2, 0x2); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x3, 0x2, 0x3); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x4, 0x2, 0x4); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x5, 0x2, 0x5); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x6, 0x2, 0x6); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x7, 0x2, 0x7); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x8, 0x2, 0x8); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0x9, 0x2, 0x9); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0xa, 0x2, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0xb, 0x2, 0xb); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0xc, 0x2, 0xc); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0xd, 0x2, 0xd); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0xe, 0x2, 0xe); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, - 0x3, 0xf, 0x2, 0xf); - /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - smp_write_lintsrc(mc, mp_ExtINT, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0, - MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, - MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x3, 0x0, - MP_APIC_ALL, 0x1); - - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} +/* dummy file */

1 0

New patch to review for coreboot: 72d9b79 device_util: Make device in dev_find_slot_pnp u16.
by Vladimir Serbinenko 08 Feb '14

08 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5165 -gerrit commit 72d9b79e0799f9af03ced89e5f3c52aaaacea086 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 8 18:58:39 2014 +0100 device_util: Make device in dev_find_slot_pnp u16. LDN is 8-bit but coreboot squeezes unrelated info: VLDN in this field. Increase to 16-bit to handle this. Change-Id: I97af1b32dcfaed84980fa3aa4c317dfab6fad6d8 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/device_util.c | 2 +- src/include/device/device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 83decc1..dc43b9a 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -100,7 +100,7 @@ struct device *dev_find_slot_on_smbus(unsigned int bus, unsigned int addr) * @param device Logical device number. * @return Pointer to the device structure (if found), 0 otherwise. */ -struct device *dev_find_slot_pnp(u16 port, u8 device) +struct device *dev_find_slot_pnp(u16 port, u16 device) { struct device *dev; diff --git a/src/include/device/device.h b/src/include/device/device.h index f05ddea..74bdbd7 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -169,7 +169,7 @@ device_t dev_find_device (u16 vendor, u16 device, device_t from); device_t dev_find_class (unsigned int class, device_t from); device_t dev_find_slot (unsigned int bus, unsigned int devfn); device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); -device_t dev_find_slot_pnp(u16 port, u8 device); +device_t dev_find_slot_pnp(u16 port, u16 device); device_t dev_find_lapic(unsigned apic_id); int dev_count_cpu(void);

1 0

New patch to review for coreboot: 4924914 Revert "MTRR: Mark all prefetchable resources as WRCOMB."
by Kyösti Mälkki 08 Feb '14

08 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5164 -gerrit commit 4924914b3b40aca7d1fcada0a6800aa444377e48 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 8 16:01:11 2014 +0100 Revert "MTRR: Mark all prefetchable resources as WRCOMB." This reverts commit 30fe6120ca8d7211f0055e47d3ecd569a628f2aa. Commit resulted with broken RTL8168 ethernet on samsung/lumpy, with errors like this in dmesg: [ 3.725703] r8169 0000:02:00.0 eth0: rtl_eriar_cond == 1 (loop: 100, delay: 100). Core issue is RTL8168 PCI function rev 06 reporting both its MMIO BARs as prefetchable. 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168 PCI Express Gigabit Ethernet controller (rev 06) Subsystem: Realtek Semiconductor Co., Ltd. RTL8111/8168 PCI Express Gigabit Ethernet controller Flags: bus master, fast devsel, latency 0, IRQ 42 I/O ports at 1000 [size=256] Memory at e0504000 (64-bit, prefetchable) [size=4K] Memory at e0500000 (64-bit, prefetchable) [size=16K] Capabilities: <access denied> Kernel driver in use: r8169 I found lspci for rev 0c with first MMIO BAR as 64-bit, non-prefetchable. Change-Id: I83aabddd806ff3615d3d6451c462a2de9d5ab781 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Kconfig | 8 ++++++++ src/cpu/x86/mtrr/mtrr.c | 5 +++-- src/include/device/resource.h | 1 + src/mainboard/google/bolt/Kconfig | 1 + src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/link/Kconfig | 1 + src/mainboard/google/peppy/Kconfig | 1 + src/mainboard/google/rambi/Kconfig | 1 + src/mainboard/google/slippy/Kconfig | 1 + src/mainboard/intel/wtm2/Kconfig | 1 + src/northbridge/intel/haswell/gma.c | 19 ++++++++++++++++++- src/northbridge/intel/nehalem/gma.c | 3 +++ src/northbridge/intel/sandybridge/gma.c | 19 ++++++++++++++++++- 13 files changed, 58 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 8854e6b..0a21fcc 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -7,6 +7,14 @@ config X86_ARCH_OPTIONS select HAVE_ARCH_MEMCPY select HAVE_ARCH_MEMMOVE +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..cdaa791 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -178,8 +178,9 @@ static struct memranges *get_physical_address_space(void) MTRR_TYPE_UNCACHEABLE); /* Handle any write combining resources. Only prefetchable - * resources are appropriate for this MTRR type. */ - match = IORESOURCE_PREFETCH; + * resources with the IORESOURCE_WRCOMB flag are appropriate + * for this MTRR type. */ + match = IORESOURCE_PREFETCH | IORESOURCE_WRCOMB; mask |= match; memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); diff --git a/src/include/device/resource.h b/src/include/device/resource.h index 2d64c80..4bd9698 100644 --- a/src/include/device/resource.h +++ b/src/include/device/resource.h @@ -21,6 +21,7 @@ * to the bus below. */ #define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */ +#define IORESOURCE_WRCOMB 0x00100000 /* Write combining resource. */ #define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..1d2b259 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..b372c47 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index efe9519..d1e809e 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT + select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..7a406e1 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 292d321..4d149c9 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select CHROMEOS + select MARK_GRAPHICS_MEM_WRCOMB config MAINBOARD_DIR string diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..065830a 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..99ed53c 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select CACHE_ROM + select MARK_GRAPHICS_MEM_WRCOMB select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 2ceffe4..00d7583 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -429,12 +429,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 2f13a6b..c7a0e9b 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -703,6 +703,9 @@ static void gma_read_resources(struct device *dev) 0xd0000001); pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + res->flags |= IORESOURCE_WRCOMB; +#endif res->base = (resource_t) 0xd0000000; res->size = (resource_t) 0x10000000; } diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2..853139e 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,12 +664,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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Patch merged into coreboot/master: 5b5f490 boardstatus/towiki: Fix 1st gen i3/i5/i7 codename
by gerrit＠coreboot.org 07 Feb '14

07 Feb '14

the following patch was just integrated into master: commit 5b5f490383b543d222ed2d9cd9823287361336d9 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 13:01:47 2014 +0100 boardstatus/towiki: Fix 1st gen i3/i5/i7 codename It was a typo. Change-Id: I82964b5ed7e7749ba141aeb3ee8dc4c107bcd7a9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5127 for details. -gerrit

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coreboot-gerrit February 2014