coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 2c41dc9 baytrail: make default GPIO configs closer to power-on defaults
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4866 -gerrit commit 2c41dc9a1035fdc8a4f961bbca6e06011f3bd4df Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Oct 4 11:47:21 2013 -0700 baytrail: make default GPIO configs closer to power-on defaults - Set config0 defaults for hysteresis disable, pad bypass, etc. - Set config1 power-on defaults. - Set pad_val for input as default. BUG=chrome-os-partner:22863 TEST=Manual. Enable GPIO_DEBUG and verify pad registers are set according to expectation. Also verify bayleybay still boots to payload loading. Change-Id: I0f1c9e4d4f39c5c56d7e14a82eb4825612e19420 Reviewed-on: https://chromium-review.googlesource.com/171903 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 113 +++++++++++++++++++++++++-------- 1 file changed, 86 insertions(+), 27 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index 32b991e..aae41a4 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -27,9 +27,9 @@ /* #define GPIO_DEBUG */ /* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE IO_BASE_ADDRESS + 0x0000 -#define GPNCORE_PAD_BASE IO_BASE_ADDRESS + 0x1000 -#define GPSSUS_PAD_BASE IO_BASE_ADDRESS + 0x2000 +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + 0x0000) +#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + 0x1000) +#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + 0x2000) /* Pad register offset */ #define PAD_CONF0_REG 0x0 @@ -37,8 +37,8 @@ #define PAD_VAL_REG 0x8 /* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE GPIO_BASE_ADDRESS + 0x00 -#define GPSSUS_LEGACY_BASE GPIO_BASE_ADDRESS + 0x80 +#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) +#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) /* Some banks have no legacy GPIO interface */ #define GP_LEGACY_BASE_NONE 0xFFFF @@ -71,19 +71,45 @@ #define GPIO_NEDGE_DISABLE 0 #define GPIO_NEDGE_ENABLE 1 -/* PAD_CONF0 settings */ +/* config0[29] - Disable second mask */ +#define PAD_MASK2_DISABLE (1 << 29) + +/* config0[27] - Direct Irq En */ #define PAD_IRQ_EN (1 << 27) + +/* config0[24] - Gd Level */ #define PAD_LEVEL_IRQ (1 << 24) +#define PAD_EDGE_IRQ (0 << 24) + +/* config0[17] - Slow clkgate / glitch filter */ +#define PAD_SLOWGF_ENABLE (1 << 17) + +/* config0[16] - Fast clkgate / glitch filter */ +#define PAD_FASTGF_ENABLE (1 << 16) +/* config0[15] - Hysteresis enable (inverted) */ +#define PAD_HYST_DISABLE (1 << 15) +#define PAD_HYST_ENABLE (0 << 15) + +/* config0[14:13] - Hysteresis control */ +#define PAD_HYST_CTRL_DEFAULT (2 << 13) + +/* config0[11] - Bypass Flop */ +#define PAD_FLOP_BYPASS (1 << 11) +#define PAD_FLOP_ENABLE (0 << 11) + +/* config0[10:9] - Pull str */ #define PAD_PU_2K (0 << 9) #define PAD_PU_10K (1 << 9) #define PAD_PU_20K (2 << 9) #define PAD_PU_40K (3 << 9) +/* config0[8:7] - Pull assign */ #define PAD_PU_DISABLE (0 << 7) #define PAD_PU_UP (1 << 7) #define PAD_PU_DOWN (2 << 7) +/* config0[2:0] - Func. pin mux */ #define PAD_FUNC0 0x0 #define PAD_FUNC1 0x1 #define PAD_FUNC2 0x2 @@ -92,68 +118,101 @@ #define PAD_FUNC5 0x5 #define PAD_FUNC6 0x6 -/* PAD_VAL settings */ -#define PAD_INPUT_ENABLE (1 << 2) -#define PAD_OUTPUT_ENABLE (1 << 1) +/* pad config0 power-on values - We will not often want to change these */ +#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ + PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ + PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) -/* End marker */ -#define GPIO_LIST_END 0xffffffff +/* pad config1 reg power-on values - Shouldn't need to change this */ +#define PAD_CONFIG1_DEFAULT 0x8000 + +/* pad_val[2] - Iinenb - active low */ +#define PAD_VAL_INPUT_DISABLE (1 << 2) +#define PAD_VAL_INPUT_ENABLE (0 << 2) + +/* pad_val[1] - Ioutenb - active low */ +#define PAD_VAL_OUTPUT_DISABLE (1 << 1) +#define PAD_VAL_OUTPUT_ENABLE (0 << 1) + +/* pad_val reg power-on default varies by pad, and apparently can cause issues + * if not set correctly, even if the pin isn't configured as GPIO. */ +#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) #define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_UP, \ - .pad_val = PAD_INPUT_ENABLE, \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } #define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PU_DISABLE, \ - .pad_val = PAD_OUTPUT_ENABLE, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_LOW } #define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PU_DISABLE, \ - .pad_val = PAD_OUTPUT_ENABLE, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } #define GPIO_FUNC0 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC0 } + .pad_conf0 = PAD_FUNC0 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC1 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC1 } + .pad_conf0 = PAD_FUNC1 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC2 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC2 } + .pad_conf0 = PAD_FUNC2 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC3 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC3 } + .pad_conf0 = PAD_FUNC3 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC4 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC4 } + .pad_conf0 = PAD_FUNC4 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC5 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC5 } + .pad_conf0 = PAD_FUNC5 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } #define GPIO_FUNC6 \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC6 } + .pad_conf0 = PAD_FUNC6 | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } + +/* End marker */ +#define GPIO_LIST_END 0xffffffff #define GPIO_END \ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_PU_10K -#define GPIO_UNUSED GPIO_INPUT_PU_10K -#define GPIO_DEFAULT GPIO_FUNC0 +#define GPIO_INPUT GPIO_INPUT_PU_10K +#define GPIO_UNUSED GPIO_INPUT_PU_10K +#define GPIO_DEFAULT GPIO_FUNC0 struct soc_gpio_map { u32 pad_conf0;

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Patch set updated for coreboot: 50285b8 baytrail: add punit access functions
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4867 -gerrit commit 50285b862ea931e97d22ecdd9f0523b6402f0f43 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 4 15:23:31 2013 -0500 baytrail: add punit access functions Like the bunit and dunit, add the punit accessor functions. BUG=chrome-os-partner:23085 BRANCH=None TEST=Built. Change-Id: Ifd7184dfca8c0491c107bc1c562ea1ded444e372 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171931 --- src/soc/intel/baytrail/baytrail/iosf.h | 2 ++ src/soc/intel/baytrail/iosf.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index b1f28da..cf7e559 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -58,6 +58,8 @@ uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); uint32_t iosf_dunit_read(int reg); void iosf_dunit_write(int reg, uint32_t val); +uint32_t iosf_punit_read(int reg); +void iosf_punit_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 2373d81..00a3269 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -76,6 +76,25 @@ void iosf_dunit_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCR_REG, cr); + write_iosf_reg(MDR_REG, val); +} + +uint32_t iosf_punit_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) | + IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_punit_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | + IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | + IOSF_BYTE_EN; write_iosf_reg(MCR_REG, cr); write_iosf_reg(MDR_REG, val);

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Patch set updated for coreboot: 0ed3ab7 baytrail: adjust cache policy during romstage
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4868 -gerrit commit 0ed3ab7d8619eb3fb0fe61d3990f2d2a91f3b00b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 7 16:24:44 2013 -0500 baytrail: adjust cache policy during romstage The caching policy for romstage was previously using a 32KiB of cache-as-ram for both the MRC wrapper and the romstage stack/data. It also used a 32KiB code cache region. The BWG's limitations for the code and data region before memory is up was wrong. It consists of a 16-way set associative 1MiB cache. As long as enough addresses are not read there isn't a risk of evicting the data/stack. Now create a 64KiB cache-as-ram region split evenly between romstage and the MRC wrapper. Additionally cache the memory just below 4GiB in CBFS size. This will cover any code and read-only data needed. BUG=chrome-os-partner:22858 BRANCH=None TEST=Built and booted quickly with corresponding changes to MRC warpper. CQ-DEPEND=CL:*146175 Change-Id: I021cecb886a9c0622005edc389136d22905d4520 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172150 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 15 +++------------ src/soc/intel/baytrail/romstage/cache_as_ram.inc | 14 +++++++------- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..4cd2133 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -92,15 +92,6 @@ endif # CACHE_MRC_SETTINGS endif # HAVE_MRC -config CAR_TILE_SIZE - hex - default 0x8000 - help - The tile size is the limit that can be assigned to cache-as-ram - region as well as the amount of code cache used during cache-as-ram. - Also note that (DCACHE_RAM_BASE ^ MRC_BIN_ADDRESS) & CAR_TILE_SIZE == - CAR_TILE_SIZE. - # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE @@ -123,11 +114,11 @@ config CAR_TILE_SIZE config DCACHE_RAM_BASE hex - default 0xff7f8000 + default 0xff800000 config DCACHE_RAM_SIZE hex - default 0x1000 + default 0x8000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE @@ -135,7 +126,7 @@ config DCACHE_RAM_SIZE config DCACHE_RAM_MRC_VAR_SIZE hex - default 0x7000 + default 0x8000 help The amount of cache-as-ram region required by the reference code. diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 82c77e2..f6e029d 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -31,10 +31,10 @@ (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -/* Enough room to cache CAR_TILE_SIZE starting at MRC_BIN_ADDRESS */ -#define CACHE_MRC_BASE (CONFIG_MRC_BIN_ADDRESS) -#define CACHE_MRC_MASK (~(CONFIG_CAR_TILE_SIZE - 1)) - +/* Cache all of CBFS just below 4GiB as Write-Protect type. */ +#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE) +#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) +#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) #define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) #define NoEvictMod_MSR 0x2e0 @@ -109,14 +109,14 @@ wait_for_sipi: wrmsr post_code(0x25) - /* Set Cache-as-RAM base address. */ + /* Set code caching up for romstage. */ movl $(MTRRphysBase_MSR(1)), %ecx - movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax + movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $(MTRRphysMask_MSR(1)), %ecx - movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax + movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr

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Patch set updated for coreboot: ea43d74 baytrail: set max frequency early in romstage
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4869 -gerrit commit ea43d74fc24edc00a0151ea7201a00fc59fce879 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 7 17:12:20 2013 -0500 baytrail: set max frequency early in romstage Set the BSP to operate at max frequency early in romstage. The call to punit_init() is when the frequency actually ramps as that makes the punit actually start working. BUG=chrome-os-partner:22857 BRANCH=None TEST=Built and booted. Noted operating frequency status is max. Change-Id: Icfd9e5c7682aa21fc740bd687607ca6a66597d5e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172131 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/baytrail/romstage.h | 1 + src/soc/intel/baytrail/romstage/romstage.c | 2 ++ src/soc/intel/baytrail/tsc_freq.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index d1fe0f1..ff0397c 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -25,6 +25,7 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); +void set_max_freq(void); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h index 4918a02..43c60ec 100644 --- a/src/soc/intel/baytrail/baytrail/romstage.h +++ b/src/soc/intel/baytrail/baytrail/romstage.h @@ -49,6 +49,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); void punit_init(void); +void set_max_freq(void); #if CONFIG_ENABLE_BUILTIN_COM1 void byt_config_com1_and_enable(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 6e965bc..0035019 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -126,6 +126,8 @@ void romstage_common(struct romstage_params *params) console_init(); + set_max_freq(); + punit_init(); gfx_init(); diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index e0b2b7e..0cf7273 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -21,6 +21,12 @@ #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <baytrail/msr.h> +#if !defined(__PRE_RAM__) +#include <baytrail/ramstage.h> +#else +#include <baytrail/romstage.h> +#endif + #define BCLK 100 /* 100 MHz */ unsigned long tsc_freq_mhz(void) @@ -30,3 +36,26 @@ unsigned long tsc_freq_mhz(void) platform_info = rdmsr(MSR_PLATFORM_INFO); return BCLK * ((platform_info.lo >> 8) & 0xff); } + +void set_max_freq(void) +{ + msr_t perf_ctl; + msr_t msr; + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of + * the PERF_CTL. */ + msr = rdmsr(MSR_IACORE_RATIOS); + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; + /* Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of + * the PERF_CTL. */ + msr = rdmsr(MSR_IACORE_VIDS); + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; + perf_ctl.hi = 0; + + wrmsr(MSR_IA32_PERF_CTL, perf_ctl); +}

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Patch set updated for coreboot: 53f9748 baytrail: Add functions to peek at GPIO input values
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4870 -gerrit commit 53f9748322e978c78b467a9be224af98e427d8e8 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Oct 8 11:31:21 2013 -0700 baytrail: Add functions to peek at GPIO input values - Add functions to peek at GPIO input pad values (need to be used from romstage for board ram_id GPIOs) - Modify UART GPIOs to use existing fn-assignment function TEST=Manual. Add debug print and verify that GPIO functions return input values. Also, verify UART still functions in romstage. BUG=chrome-os-partner:22865 Change-Id: Ib2e57631c127a592cfa20ab6e2184822424e9d77 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172189 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 21 +++++++++++++++++++++ src/soc/intel/baytrail/gpio.c | 2 +- src/soc/intel/baytrail/romstage/uart.c | 7 +++---- 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index aae41a4..bdd36c1 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -134,6 +134,10 @@ #define PAD_VAL_OUTPUT_DISABLE (1 << 1) #define PAD_VAL_OUTPUT_ENABLE (0 << 1) +/* pad_val[0] - Value */ +#define PAD_VAL_HIGH (1 << 0) +#define PAD_VAL_LOW (0 << 0) + /* pad_val reg power-on default varies by pad, and apparently can cause issues * if not set correctly, even if the pin isn't configured as GPIO. */ #define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) @@ -247,6 +251,8 @@ struct soc_gpio_config* mainboard_get_gpios(void); /* Functions / defines for changing GPIOs in romstage */ /* SCORE Pad definitions. */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 #define PCU_SMB_CLK_PAD 88 #define PCU_SMB_DATA_PAD 90 @@ -282,4 +288,19 @@ static inline void ssus_select_func(int pad, int func) write32(pconf0_addr, reg); } +/* These functions require that the input pad be configured as an input GPIO */ +static inline int score_get_gpio(int pad) +{ + uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG; + + return read32(val_addr) & PAD_VAL_HIGH; +} + +static inline int ssus_get_gpio(int pad) +{ + uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG; + + return read32(val_addr) & PAD_VAL_HIGH; +} + #endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 8118aeb..9ae79c9 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -44,7 +44,7 @@ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, - 26, 51, 56, 54, 49, 55, 48, 47, 50, 58, + 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, 52, 53, 59, 40 }; /* GPIO bank descriptions */ diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c index dee3be9..e46237a 100644 --- a/src/soc/intel/baytrail/romstage/uart.c +++ b/src/soc/intel/baytrail/romstage/uart.c @@ -32,8 +32,7 @@ void byt_config_com1_and_enable(void) reg = 1; pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - /* Set up the pads to select the UART function. RXD and TXD are - * 0x520 and 0x530, respectively. */ - write32(IO_BASE_ADDRESS + 0x520, read32(IO_BASE_ADDRESS + 0x520) | 1); - write32(IO_BASE_ADDRESS + 0x530, read32(IO_BASE_ADDRESS + 0x530) | 1); + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); }

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Patch set updated for coreboot: 824845a baytrail: move early init to before mainboard
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4871 -gerrit commit 824845a71e21871bc158fce423ee1f839ee50e28 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 8 16:54:18 2013 -0500 baytrail: move early init to before mainboard It's helpful to have a lot of the early init happen before the handoff to mainboard. One example of this need is having the BARs programmed so that the mainboard can read board-specific gpios. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Booted and saw console outout in bayleybay mainboard. Signed-off-by; Aaron Durbin <adurbin(a)chromium.org> Change-Id: I030d7b4f9061ad7501049e8e204ea12255061fbe Reviewed-on: https://chromium-review.googlesource.com/172290 Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/romstage/romstage.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 0035019..4228615 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -107,17 +107,6 @@ void * asmlinkage romstage_main(unsigned long bist, /* Save romstage begin */ mark_ts(&rp, timestamp_get()); - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); - - return setup_stack_and_mttrs(); -} - -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) -{ - struct romstage_handoff *handoff; - program_base_addresses(); tco_disable(); @@ -132,6 +121,17 @@ void romstage_common(struct romstage_params *params) gfx_init(); + /* Call into mainboard. */ + mainboard_romstage_entry(&rp); + + return setup_stack_and_mttrs(); +} + +/* Entry from the mainboard. */ +void romstage_common(struct romstage_params *params) +{ + struct romstage_handoff *handoff; + mark_ts(params, timestamp_get()); /* Initialize RAM */

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Patch set updated for coreboot: cf994f5 baytrail: allow downstream use of SSE instructions
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4881 -gerrit commit cf994f5ed8ac1daa7641f90fce9734a13342cb03 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 12:47:47 2013 -0500 baytrail: allow downstream use of SSE instructions If a payload is compiled to use SSE instructions it will fault with an undefined opcode because SSE instructions weren't enabled. Therefore enable SSE instructions at runtime. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted with SSE enabled payload. No exceptions seen. Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172642 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/soc/intel/baytrail/ramstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 10c030f..229e367 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -20,6 +20,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/microcode.h> +#include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci_def.h> @@ -109,6 +110,9 @@ void baytrail_init_pre_device(void) fill_in_pattrs(); + /* Allow for SSE instructions to be executed. */ + write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config);

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Patch set updated for coreboot: 60249f8 baytrail: add vboot ramstage verification
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4880 -gerrit commit 60249f853646a8230765a41a4641a1787012900d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 21:03:50 2013 -0500 baytrail: add vboot ramstage verification Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/romstage/romstage.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 293ed21..33c0d56 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,6 +9,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4228615..3ae52cf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -25,12 +25,16 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <ramstage_cache.h> +#include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h> static inline uint64_t timestamp_get(void) @@ -169,6 +173,9 @@ void asmlinkage romstage_after_car(void) timestamp_add_now(TS_END_ROMSTAGE); + /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + /* Load the ramstage. */ copy_and_run(); while (1); @@ -270,3 +277,25 @@ static void *setup_stack_and_mttrs(void) return slot; } + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = (1 << 20); + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; +} + +void ramstage_cache_invalid(struct ramstage_cache *cache) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} +

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Patch set updated for coreboot: 6126771 baytrail: fix tsc rate
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4883 -gerrit commit 612677146fae6eb6d7fe1a86513f02ea1324b212 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 00:44:06 2013 -0500 baytrail: fix tsc rate Despite some references to a fixed bclk in some of the docs the bclk is variable per sku. Therefore, perform the calculation according to the BSEL_CR_OVERCLOCK_CONTROL msr which provides the bclk for the cpu cores in Bay Trail. BUG=chrome-os-partner:23166 BRANCH=None TEST=Built and booted B3. correctly says: clocks_per_usec: 2133 Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172771 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/msr.h | 1 + src/soc/intel/baytrail/tsc_freq.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index 7f3b3b2..5094f96 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -21,6 +21,7 @@ #define _BAYTRAIL_MSR_H_ #define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 0cf7273..3b662fe 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -27,14 +27,21 @@ #include <baytrail/romstage.h> #endif - -#define BCLK 100 /* 100 MHz */ unsigned long tsc_freq_mhz(void) { msr_t platform_info; + msr_t clk_info; + unsigned long bclk_khz; platform_info = rdmsr(MSR_PLATFORM_INFO); - return BCLK * ((platform_info.lo >> 8) & 0xff); + clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); + switch (clk_info.lo & 0x3) { + case 0: bclk_khz = 83333; break; + case 1: bclk_khz = 100000; break; + case 2: bclk_khz = 133333; break; + case 3: bclk_khz = 116666; break; + } + return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } void set_max_freq(void)

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Patch set updated for coreboot: 332d65e baytrail: print dram configuration
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4882 -gerrit commit 332d65e3090caa5081da3180441a0fe37a453e8a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 00:26:04 2013 -0500 baytrail: print dram configuration After running the MRC blob print out some information on the training: MRC version, number channels, DDR3 type, and DRAM frequency. Example output: MRC v0.90 2 channels of DDR3 @ 1066MHz Apparently there are two dunit IOSF ports -- 1 for each channel. However, certain registers really on live in channel 0. Thus, there was some changes to dunit support in the iosf area. BUG=chrome-os-partner:22875 BRANCH=None TEST=Built and booted bayleybay in different configs. Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172770 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 15 ++++++++--- src/soc/intel/baytrail/iosf.c | 15 +++++++++++ src/soc/intel/baytrail/romstage/raminit.c | 45 +++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index cf7e559..497124e 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -58,16 +58,21 @@ uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); uint32_t iosf_dunit_read(int reg); void iosf_dunit_write(int reg, uint32_t val); +/* Some registers are per channel while the gloals live in dunit 0 */ +uint32_t iosf_dunit_ch0_read(int reg); +uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ +#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memroy Arbiter/Bunit */ #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ #define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ +#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ @@ -120,10 +125,12 @@ void iosf_punit_write(int reg, uint32_t val); */ #define DRP 0x00 -# define DRP_CH0_RANK0_EN (0x01 << 0) -# define DRP_CH0_RANK1_EN (0x01 << 1) -# define DRP_CH1_RANK0_EN (0x01 << 2) -# define DRP_CH1_RANK1_EN (0x01 << 3) +# define DRP_DIMM0_RANK0_EN (0x01 << 0) +# define DRP_DIMM0_RANK1_EN (0x01 << 1) +# define DRP_DIMM1_RANK0_EN (0x01 << 2) +# define DRP_DIMM1_RANK1_EN (0x01 << 3) +# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ + DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) #define DTR0 0x01 # define DTR0_SPEED_MASK 0x03 # define DTR0_SPEED_800 0x00 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 00a3269..e35e34f 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -70,6 +70,21 @@ uint32_t iosf_dunit_read(int reg) return read_iosf_reg(MDR_REG); } +uint32_t iosf_dunit_ch0_read(int reg) +{ + return iosf_dunit_read(reg); +} + +uint32_t iosf_dunit_ch1_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + void iosf_dunit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index cf9ccfd..7bcd54f 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -26,6 +26,7 @@ #include <baytrail/gpio.h> #include <baytrail/mrc_cache.h> #include <baytrail/iomap.h> +#include <baytrail/iosf.h> #include <baytrail/pci_devs.h> #include <baytrail/romstage.h> @@ -57,6 +58,48 @@ static void ABI_X86 send_to_console(unsigned char b) console_tx_byte(b); } +static void print_dram_info(void) +{ + const int mrc_ver_reg = 0xf0; + const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); + uint32_t reg; + int num_channels; + int speed; + uint32_t ch0; + uint32_t ch1; + + reg = pci_read_config32(soc_dev, mrc_ver_reg); + + printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); + + /* Number of channels enabled and DDR3 type. Determine number of + * channels by keying of the rank enable bits [3:0]. * */ + ch0 = iosf_dunit_ch0_read(DRP); + ch1 = iosf_dunit_ch1_read(DRP); + num_channels = 0; + if (ch0 & DRP_RANK_MASK) + num_channels++; + if (ch1 & DRP_RANK_MASK) + num_channels++; + + printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, + (reg & (1 << 22)) ? "LP" : ""); + + /* DRAM frequency -- all channels run at same frequency. */ + reg = iosf_dunit_read(DTR0); + switch (reg & 0x3) { + case 0: + speed = 800; break; + case 1: + speed = 1066; break; + case 2: + speed = 1333; break; + case 3: + speed = 1600; break; + } + printk(BIOS_INFO, "%dMHz\n", speed); +} + void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; @@ -87,6 +130,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) ret = mrc_entry(mp); + print_dram_info(); + cbmem_initialize_empty(); printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);

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coreboot-gerrit February 2014