coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch merged into coreboot/master: e9846f0 boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs
by gerrit＠coreboot.org 07 Feb '14

07 Feb '14

the following patch was just integrated into master: commit e9846f012e4339a756b118f40a1ab8cabbb4b691 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 12:21:40 2014 +0100 boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs Change-Id: I3a38ca834606bb53e6f82cbe79c3a99288429aee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5124 for details. -gerrit

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New patch to review for coreboot: db947a0 QEMU pl011 console: Move under drivers/emulation/qemu
by Kyösti Mälkki 07 Feb '14

07 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5162 -gerrit commit db947a0e891bc177a0f4436ae4c430966172b4ca Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 7 10:44:41 2014 +0200 QEMU pl011 console: Move under drivers/emulation/qemu Also make this console under Kconfig control. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 12 +++++-- src/drivers/emulation/qemu/Makefile.inc | 13 ++++++-- src/drivers/emulation/qemu/qemu_pl011_uart.c | 37 +++++++++++++++++++++ src/mainboard/emulation/qemu-armv7/Makefile.inc | 2 ++ src/mainboard/emulation/qemu-armv7/uart.c | 43 +++++++------------------ 5 files changed, 70 insertions(+), 37 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 40903c1..e22af05 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -314,19 +314,25 @@ config CONSOLE_CAR_BUFFER_SIZE config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" - depends on BOARD_EMULATION_QEMU_X86 + depends on BOARD_EMULATION_QEMU_X86 || BOARD_EMULATION_QEMU_ARMV7 default y help - Send coreboot debug output to QEMU's isa-debugcon device: + Send coreboot debug output to QEMU debug console. + For qemu-x86: qemu-system-x86_64 \ -chardev file,id=debugcon,path=/dir/file.log \ -device isa-debugcon,iobase=0x402,chardev=debugcon + For qemu-armv7: + qemu-system-arm -M vexpress-a9 \ + -m 1024M -serial stdio -kernel build/coreboot.rom + config CONSOLE_QEMU_DEBUGCON_PORT hex "QEMU debug console port" depends on CONSOLE_QEMU_DEBUGCON - default 0x402 + default 0x402 if BOARD_EMULATION_QEMU_X86 + default 0x10009000 if BOARD_EMULATION_QEMU_ARMV7 choice prompt "Default console log level" diff --git a/src/drivers/emulation/qemu/Makefile.inc b/src/drivers/emulation/qemu/Makefile.inc index 3351627..16364f6 100644 --- a/src/drivers/emulation/qemu/Makefile.inc +++ b/src/drivers/emulation/qemu/Makefile.inc @@ -1,5 +1,14 @@ -romstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c -ramstage-$(CONFIG_CONSOLE_QEMU_DEBUGCON) += qemu_debugcon.c +ifeq ($(CONFIG_CONSOLE_QEMU_DEBUGCON),y) +ifeq ($(CONFIG_BOARD_EMULATION_QEMU_X86),y) +romstage-$(CONFIG_EARLY_CONSOLE) += qemu_debugcon.c +ramstage-y += qemu_debugcon.c +endif +ifeq ($(CONFIG_BOARD_EMULATION_QEMU_ARMV7),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += qemu_pl011_uart.c +romstage-$(CONFIG_EARLY_CONSOLE) += qemu_pl011_uart.c +ramstage-y += qemu_pl011_uart.c +endif +endif ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += bochs.c ramstage-$(CONFIG_DRIVERS_EMULATION_QEMU_BOCHS) += cirrus.c diff --git a/src/drivers/emulation/qemu/qemu_pl011_uart.c b/src/drivers/emulation/qemu/qemu_pl011_uart.c new file mode 100644 index 0000000..88f1ffe --- /dev/null +++ b/src/drivers/emulation/qemu/qemu_pl011_uart.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/qemu_debugcon.h> +#include <uart.h> + +void qemu_debugcon_init(void) +{ +} + +void qemu_debugcon_tx_byte(unsigned char data) +{ + volatile unsigned int *uart0_address = + (unsigned int *)CONFIG_CONSOLE_QEMU_DEBUGCON_PORT; + + *uart0_address = (unsigned int)data; +} + +#if !defined(__PRE_RAM__) +uint32_t uartmem_getbaseaddr(void) +{ + return CONFIG_CONSOLE_QEMU_DEBUGCON_PORT; +} +#endif diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index 431d9ab..a3bac27 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -22,6 +22,8 @@ bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c +ifeq ($(CONFIG_CONSOLE_QEMU_DEBUGCON),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c ramstage-y += uart.c +endif diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c index dfe5d0a..5710150 100644 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ b/src/mainboard/emulation/qemu-armv7/uart.c @@ -14,47 +14,26 @@ */ #include <console/console.h> +#include <console/qemu_debugcon.h> #include <uart.h> -#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) - -static void pl011_init_dev(void) { -} - -static void pl011_uart_tx_byte(unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *)VEXPRESS_UART0_IO_ADDRESS; - - *uart0_address = (unsigned int)data; -} - -static void pl011_uart_tx_flush(void) { -} - -#if !defined(__PRE_RAM__) - -static const struct console_driver pl011_uart_console __console = { - .init = pl011_init_dev, - .tx_byte = pl011_uart_tx_byte, - .tx_flush = pl011_uart_tx_flush, -}; - -uint32_t uartmem_getbaseaddr(void) -{ - return VEXPRESS_UART0_IO_ADDRESS; -} -#else void uart_init(void) { - pl011_init_dev(); } void uart_tx_byte(unsigned char data) { - pl011_uart_tx_byte(data); + qemu_debugcon_tx_byte(data); } -void uart_tx_flush(void) { - pl011_uart_tx_flush(); +void uart_tx_flush(void) +{ } + +#if !defined(__PRE_RAM__) +static const struct console_driver pl011_uart_console __console = { + .init = uart_init, + .tx_byte = uart_tx_byte, + .tx_flush = uart_tx_flush, +}; #endif

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Patch merged into coreboot/master: 987dfe6 device_util: Add dev_find_slot_pnp.
by gerrit＠coreboot.org 07 Feb '14

07 Feb '14

the following patch was just integrated into master: commit 987dfe607be6b450777859e96b0ed3efc096adee Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Feb 4 14:34:11 2014 +0100 device_util: Add dev_find_slot_pnp. Change-Id: I5223c54c8ddbc60a176e4d718730e99decc772a3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5112 for details. -gerrit

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Patch set updated for coreboot: d660985 Kconfig: Move vendorcode menu up from the bottom to above Chipset menu
by Peter Stuge 07 Feb '14

07 Feb '14

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5160 -gerrit commit d660985218c90592df1c0e0dfa6af89898e273cc Author: Peter Stuge <peter(a)stuge.se> Date: Fri Feb 7 03:58:24 2014 +0100 Kconfig: Move vendorcode menu up from the bottom to above Chipset menu Change-Id: Ic97a497a634533f44d94df297ca6e35d94c34565 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 31a41ab..94fea2d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -249,6 +249,8 @@ config HAVE_ARCH_MEMMOVE bool default n +source src/vendorcode/Kconfig + menu "Chipset" comment "CPU" @@ -1108,5 +1110,3 @@ config POWER_BUTTON_IS_OPTIONAL default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) help Internal option that controls ENABLE_POWER_BUTTON visibility. - -source src/vendorcode/Kconfig

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New patch to review for coreboot: ce58a63 Kconfig: Unify IDS options for all six AGESA trees into a vendorcode menu
by Peter Stuge 07 Feb '14

07 Feb '14

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5161 -gerrit commit ce58a6344243b096a8ce87c8483131b7ed0a2b9e Author: Peter Stuge <peter(a)stuge.se> Date: Fri Feb 7 03:57:36 2014 +0100 Kconfig: Unify IDS options for all six AGESA trees into a vendorcode menu Change-Id: I5bea6d777581c0cae537cb8cfd196c3ac9fc1a37 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/cpu/amd/agesa/family10/Kconfig | 8 - src/cpu/amd/agesa/family15/Kconfig | 8 - src/mainboard/amd/dinar/OptionsIds.h | 64 ------- src/mainboard/amd/inagua/OptionsIds.h | 64 ------- src/mainboard/amd/olivehill/OptionsIds.h | 67 ------- src/mainboard/amd/parmer/OptionsIds.h | 67 ------- src/mainboard/amd/persimmon/OptionsIds.h | 64 ------- src/mainboard/amd/south_station/OptionsIds.h | 64 ------- src/mainboard/amd/thatcher/OptionsIds.h | 67 ------- src/mainboard/amd/torpedo/OptionsIds.h | 64 ------- src/mainboard/amd/union_station/OptionsIds.h | 64 ------- src/mainboard/asrock/e350m1/OptionsIds.h | 66 ------- src/mainboard/asrock/imb-a180/OptionsIds.h | 67 ------- src/mainboard/asus/f2a85-m/OptionsIds.h | 67 ------- src/mainboard/gizmosphere/gizmo/OptionsIds.h | 65 ------- src/mainboard/lippert/frontrunner-af/OptionsIds.h | 64 ------- src/mainboard/lippert/toucan-af/OptionsIds.h | 64 ------- src/mainboard/supermicro/h8qgi/OptionsIds.h | 66 ------- src/mainboard/supermicro/h8scm/OptionsIds.h | 67 ------- src/mainboard/tyan/s8226/OptionsIds.h | 67 ------- src/vendorcode/Kconfig | 1 + src/vendorcode/amd/Kconfig | 1 + src/vendorcode/amd/agesa/Kconfig | 203 ++++++++++++++++++++++ src/vendorcode/amd/agesa/Makefile.inc | 2 + src/vendorcode/amd/agesa/OptionsIds.h | 71 ++++++++ src/vendorcode/amd/agesa/f10/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f12/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f15/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 2 +- 31 files changed, 284 insertions(+), 1200 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 621ee58..ae5a09e 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -49,12 +49,4 @@ config HAVE_INIT_TIMER bool default y -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - endif #CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 02991a0..963ef42 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -70,12 +70,4 @@ config HAVE_INIT_TIMER bool default y -config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - bool "Redirect AGESA IDS_HDT_CONSOLE to serial console" - default n - help - This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. - - Warning: Only enable this option when debuging or tracing AMD AGESA code. - endif #CPU_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/amd/dinar/OptionsIds.h b/src/mainboard/amd/dinar/OptionsIds.h deleted file mode 100644 index a756942..0000000 --- a/src/mainboard/amd/dinar/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/inagua/OptionsIds.h b/src/mainboard/amd/inagua/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/inagua/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/olivehill/OptionsIds.h b/src/mainboard/amd/olivehill/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/olivehill/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/parmer/OptionsIds.h b/src/mainboard/amd/parmer/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/parmer/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/persimmon/OptionsIds.h b/src/mainboard/amd/persimmon/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/persimmon/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/south_station/OptionsIds.h b/src/mainboard/amd/south_station/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/south_station/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/thatcher/OptionsIds.h b/src/mainboard/amd/thatcher/OptionsIds.h deleted file mode 100644 index e006441..0000000 --- a/src/mainboard/amd/thatcher/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/torpedo/OptionsIds.h b/src/mainboard/amd/torpedo/OptionsIds.h deleted file mode 100644 index 4e86877..0000000 --- a/src/mainboard/amd/torpedo/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/amd/union_station/OptionsIds.h b/src/mainboard/amd/union_station/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/amd/union_station/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asrock/e350m1/OptionsIds.h b/src/mainboard/asrock/e350m1/OptionsIds.h deleted file mode 100644 index 600753c..0000000 --- a/src/mainboard/asrock/e350m1/OptionsIds.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asrock/imb-a180/OptionsIds.h b/src/mainboard/asrock/imb-a180/OptionsIds.h deleted file mode 100644 index 0a1d328..0000000 --- a/src/mainboard/asrock/imb-a180/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h deleted file mode 100644 index bf7eedc..0000000 --- a/src/mainboard/asus/f2a85-m/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -//#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/gizmosphere/gizmo/OptionsIds.h b/src/mainboard/gizmosphere/gizmo/OptionsIds.h deleted file mode 100755 index 3655b5e..0000000 --- a/src/mainboard/gizmosphere/gizmo/OptionsIds.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/lippert/frontrunner-af/OptionsIds.h b/src/mainboard/lippert/frontrunner-af/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/lippert/frontrunner-af/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/lippert/toucan-af/OptionsIds.h b/src/mainboard/lippert/toucan-af/OptionsIds.h deleted file mode 100644 index cf0a4be..0000000 --- a/src/mainboard/lippert/toucan-af/OptionsIds.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -#define IDSOPT_ASSERT_ENABLED TRUE - -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/supermicro/h8qgi/OptionsIds.h b/src/mainboard/supermicro/h8qgi/OptionsIds.h deleted file mode 100644 index cdf1701..0000000 --- a/src/mainboard/supermicro/h8qgi/OptionsIds.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/supermicro/h8scm/OptionsIds.h b/src/mainboard/supermicro/h8scm/OptionsIds.h deleted file mode 100644 index bf719bf..0000000 --- a/src/mainboard/supermicro/h8scm/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/mainboard/tyan/s8226/OptionsIds.h b/src/mainboard/tyan/s8226/OptionsIds.h deleted file mode 100644 index ceb336f..0000000 --- a/src/mainboard/tyan/s8226/OptionsIds.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/** - * @file - * - * IDS Option File - * - * This file is used to switch on/off IDS features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: AGESA - * @e sub-project: Core - * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ - */ -#ifndef _OPTION_IDS_H_ -#define _OPTION_IDS_H_ - -/** - * - * This file generates the defaults tables for the Integrated Debug Support - * Module. The documented build options are imported from a user controlled - * file for processing. The build options for the Integrated Debug Support - * Module are listed below: - * - * IDSOPT_IDS_ENABLED - * IDSOPT_ERROR_TRAP_ENABLED - * IDSOPT_CONTROL_ENABLED - * IDSOPT_TRACING_ENABLED - * IDSOPT_PERF_ANALYSIS - * IDSOPT_ASSERT_ENABLED - * IDS_DEBUG_PORT - * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED - * - **/ - -#define IDSOPT_IDS_ENABLED TRUE -//#define IDSOPT_CONTROL_ENABLED TRUE -//#define IDSOPT_TRACING_ENABLED TRUE -//#define IDSOPT_PERF_ANALYSIS TRUE -#define IDSOPT_ASSERT_ENABLED TRUE -//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE -//#undef IDSOPT_DEBUG_ENABLED -//#define IDSOPT_DEBUG_ENABLED FALSE -//#undef IDSOPT_HOST_SIMNOW -//#define IDSOPT_HOST_SIMNOW FALSE -//#undef IDSOPT_HOST_HDT -//#define IDSOPT_HOST_HDT FALSE -//#define IDS_DEBUG_PORT 0x80 - -#endif diff --git a/src/vendorcode/Kconfig b/src/vendorcode/Kconfig index a8cbe02..9b6e5d4 100644 --- a/src/vendorcode/Kconfig +++ b/src/vendorcode/Kconfig @@ -1,2 +1,3 @@ +source src/vendorcode/amd/Kconfig source src/vendorcode/google/Kconfig source src/vendorcode/intel/Kconfig diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig new file mode 100644 index 0000000..e59f40e --- /dev/null +++ b/src/vendorcode/amd/Kconfig @@ -0,0 +1 @@ +source src/vendorcode/amd/agesa/Kconfig diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..ddcc4e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,203 @@ +if CPU_AMD_AGESA +menu "AGESA" + +config VENDORCODE_AMD_AGESA_F10 + def_bool y if CPU_AMD_AGESA_FAMILY10 + +config VENDORCODE_AMD_AGESA_F12 + def_bool y if CPU_AMD_AGESA_FAMILY12 + +config VENDORCODE_AMD_AGESA_F14 + def_bool y if CPU_AMD_AGESA_FAMILY14 + +config VENDORCODE_AMD_AGESA_F15 + def_bool y if CPU_AMD_AGESA_FAMILY15 + +config VENDORCODE_AMD_AGESA_F15TN + def_bool y if CPU_AMD_AGESA_FAMILY15_TN + +config VENDORCODE_AMD_AGESA_F16KB + def_bool y if CPU_AMD_AGESA_FAMILY16_KB + +config VENDORCODE_AMD_AGESA_R12067 + def_bool y if VENDORCODE_AMD_AGESA_F10 + +config VENDORCODE_AMD_AGESA_R38300 + def_bool y if CPU_AMD_AGESA_FAMILY14 + select VENDORCODE_AMD_AGESA_R12067 + +config VENDORCODE_AMD_AGESA_R44324 + def_bool y if VENDORCODE_AMD_AGESA_F12 || VENDORCODE_AMD_AGESA_F15 + select VENDORCODE_AMD_AGESA_R38300 + +config VENDORCODE_AMD_AGESA_R63425 + def_bool y if VENDORCODE_AMD_AGESA_F15TN + select VENDORCODE_AMD_AGESA_R44324 + +config VENDORCODE_AMD_AGESA_R84150 + def_bool y if VENDORCODE_AMD_AGESA_F16KB + select VENDORCODE_AMD_AGESA_R63425 + + +config IDSOPT_IDS_ENABLED + bool "Integrated Debug Support" + default n + help + Integrated Debug Support Module is used to debug AGESA events. + +config IDSOPT_CONTROL_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + + Support *skip* hooks for IDS options. + +config IDSOPT_CONTROL_NV_TO_CMOS + def_bool n + depends on IDSOPT_IDS_ENABLED && VENDORCODE_AMD_AGESA_R44324 + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDS_OPT_CMOS_INDEX_PORT + hex "IDS NVRAM index I/O port" + default 0x70 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_DATA_PORT + hex "IDS NVRAM data I/O port" + default 0x71 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_REGION_START + hex "IDS NVRAM region start" + default 0x20 + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDS_OPT_CMOS_REGION_END + hex "IDS NVRAM region end" + default 0x7f + depends on IDSOPT_CONTROL_NV_TO_CMOS + +config IDSOPT_TRACING_ENABLED + bool "Enable trace messages" + default y + depends on IDSOPT_IDS_ENABLED + help + This option enables trace message output by AGESA at runtime. + +config IDSOPT_CUSTOMIZE_TRACING_SERVICE + def_bool n + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_R63425 + help + This IDS option is dead code in the current coreboot AGESA sources. + + The option allows to create custom trace handlers which would + replace the AGESA-internal tracing support. + +choice + prompt "Output trace messages to" + default IDSOPT_TRACING_CONSOLE_SERIALPORT + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_R63425 + +config REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL + bool "coreboot console" + depends on VENDORCODE_AMD_AGESA_F10 || VENDORCODE_AMD_AGESA_F15 + help + Output trace messages to the coreboot console. + +config IDSOPT_TRACING_CONSOLE_HDTOUT + bool "hardware debug tool" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a Hardware Debug Tool. + +config IDSOPT_TRACING_CONSOLE_SERIALPORT + bool "serial port" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a 16550-compatible UART. + +config IDSOPT_TRACING_CONSOLE_REDIRECT_IO + bool "I/O port" + depends on VENDORCODE_AMD_AGESA_R63425 + help + Output trace messages to a custom I/O port. + +endchoice + +config IDSOPT_SERIAL_PORT + hex "Serial port I/O port" + default 0x3f8 + depends on IDSOPT_TRACING_ENABLED && IDSOPT_TRACING_CONSOLE_SERIALPORT + +config IDSOPT_DEBUG_PRINT_IO_PORT + hex "I/O port" + default 0x80 + depends on IDSOPT_TRACING_ENABLED && IDSOPT_TRACING_CONSOLE_REDIRECT_IO + +config IDSOPT_C_OPTIMIZATION_DISABLED + def_bool n if IDSOPT_TRACING_ENABLED + def_bool y if !IDSOPT_TRACING_ENABLED + depends on IDSOPT_TRACING_ENABLED && VENDORCODE_AMD_AGESA_F14 + help + Disable printk(BIOS_DEBUG) for IDS_HDT_CONSOLE messages. + +config IDSOPT_PERF_ANALYSIS + def_bool n + depends on IDSOPT_IDS_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + + The option enables collection and analysis of performance timestamps. + +config IDSOPT_ERROR_TRAP_ENABLED + bool "Trap Error events with stop code display" + default n + depends on IDSOPT_IDS_ENABLED + help + This option makes IDS trap and stop execution on an AGESA Error event. + +config IDSOPT_ASSERT_ENABLED + bool "Trap ASSERT failures with stop code display" + default y + depends on IDSOPT_IDS_ENABLED + help + This option makes IDS trap and stop execution if an ASSERT() is false. + + ASSERT is used in AGESA code for testing for fatal errors that must + be resolved before production. This is used to do parameter checks, + bounds checking, range checks and 'sanity' checks. + +config IDS_DEBUG_PORT + hex "AGESA_TESTPOINT I/O port" + default 0x80 + depends on IDSOPT_IDS_ENABLED + help + This configures the AGESA_TESTPOINT I/O port, usually the POST port. + +config IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED + select IDSOPT_ERROR_TRAP_ENABLED + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDSOPT_DEBUG_CODE_ENABLED + def_bool n + depends on IDSOPT_IDS_ENABLED && VENDORCODE_AMD_AGESA_R38300 + help + This IDS option is dead code in the current coreboot AGESA sources. + +config IDSOPT_IDT_EXCEPTION_TRAP + bool "Trap exceptions with a 'jmp $' infinite loop" + default n + depends on IDSOPT_IDS_ENABLED && EXPERT && VENDORCODE_AMD_AGESA_F15TN + help + This option adds a 'jmp $' into every exception handler. + + Technically this option is available already with F12 but in the + coreboot AGESA sources the option only does something for F15TN. + +endmenu +endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 99356a6..cff0453 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -1,3 +1,5 @@ +AGESA_INC = -Isrc/vendorcode/amd/agesa + subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY10) += f10 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += f12 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += f14 diff --git a/src/vendorcode/amd/agesa/OptionsIds.h b/src/vendorcode/amd/agesa/OptionsIds.h new file mode 100644 index 0000000..d823b45 --- /dev/null +++ b/src/vendorcode/amd/agesa/OptionsIds.h @@ -0,0 +1,71 @@ +/** + * Copyright (c) 2014 Peter Stuge <peter(a)stuge.se> + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +#if CONFIG_IDSOPT_IDS_ENABLED +#define IDSOPT_IDS_ENABLED (CONFIG_IDSOPT_IDS_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_ERROR_TRAP_ENABLED +#define IDSOPT_ERROR_TRAP_ENABLED (CONFIG_IDSOPT_ERROR_TRAP_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_CONTROL_ENABLED +#define IDSOPT_CONTROL_ENABLED (CONFIG_IDSOPT_CONTROL_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_TRACING_ENABLED +#define IDSOPT_TRACING_ENABLED (CONFIG_IDSOPT_TRACING_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_TRACING_CONSOLE_HDTOUT +#define IDSOPT_TRACING_CONSOLE_HDTOUT (CONFIG_IDSOPT_TRACING_CONSOLE_HDTOUT ? TRUE : FALSE) +#endif + +#ifdef CONFIG_IDSOPT_TRACING_CONSOLE_SERIAL +#define IDSOPT_TRACING_CONSOLE_SERIALPORT (CONFIG_IDSOPT_TRACING_CONSOLE_SERIALPORT ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_SERIAL_PORT +#define IDSOPT_SERIAL_PORT CONFIG_IDSOPT_SERIAL_PORT +#endif + +#ifdef CONFIG_IDSOPT_TRACING_CONSOLE_REDIRECT_TO +#define IDSOPT_TRACING_CONSOLE_REDIRECT_TO (CONFIG_IDSOPT_TRACING_CONSOLE_REDIRECT_TO ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_DEBUG_PRINT_IO_PORT +#define IDSOPT_DEBUG_PRINT_IO_PORT CONFIG_IDSOPT_DEBUG_PRINT_IO_PORT +#endif + +#if CONFIG_IDSOPT_PERF_ANALYSIS +#define IDSOPT_PERF_ANALYSIS (CONFIG_IDSOPT_PERF_ANALYSIS ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_ASSERT_ENABLED +#define IDSOPT_ASSERT_ENABLED (CONFIG_IDSOPT_ASSERT_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDS_DEBUG_PORT +#define IDS_DEBUG_PORT CONFIG_IDS_DEBUG_PORT +#endif + +#if CONFIG_IDSOPT_CAR_CORRUPTION_CHECK_ENABLED +#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED (CONFIG_IDSOPT_CAR_CORRUPTION_CHECK_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_DEBUG_CODE_ENABLED +#define IDSOPT_DEBUG_CODE_ENABLED (CONFIG_IDSOPT_DEBUG_CODE_ENABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_C_OPTIMIZATION_DISABLED +#define IDSOPT_C_OPTIMIZATION_DISABLED (CONFIG_IDSOPT_C_OPTIMIZATION_DISABLED ? TRUE : FALSE) +#endif + +#if CONFIG_IDSOPT_IDT_EXCEPTION_TRAP +#define IDSOPT_IDT_EXCEPTION_TRAP (CONFIG_IDSOPT_IDT_EXCEPTION_TRAP ? TRUE : FALSE) +#endif + +#endif diff --git a/src/vendorcode/amd/agesa/f10/Makefile.inc b/src/vendorcode/amd/agesa/f10/Makefile.inc index 203efab..544a8c8 100644 --- a/src/vendorcode/amd/agesa/f10/Makefile.inc +++ b/src/vendorcode/amd/agesa/f10/Makefile.inc @@ -20,7 +20,7 @@ ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT = src/vendorcode/amd/agesa/f10 -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index e1bafbe..b00423d 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f12 -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 6a266ec..9a61432 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f14 -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f15/Makefile.inc b/src/vendorcode/amd/agesa/f15/Makefile.inc index 2a7acce..51087fb 100644 --- a/src/vendorcode/amd/agesa/f15/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15/Makefile.inc @@ -20,7 +20,7 @@ ## ABSOLUTE AGESA V5 ROOT PATH ## AGESA_ROOT ?= $(PWD) -AGESA_INC ?= -I$(src)/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index f90e7b1..c2e1d2a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f15tn -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 0e68895..cca25f3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -30,7 +30,7 @@ # AGESA V5 Files AGESA_ROOT = src/vendorcode/amd/agesa/f16kb -AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include AGESA_INC += -I$(AGESA_ROOT)/Lib

1 0

New patch to review for coreboot: cbe91ff Kconfig: Move vendorcode menu up from the bottom to above Chipset menu
by Peter Stuge 07 Feb '14

07 Feb '14

Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5160 -gerrit commit cbe91ff4e72f4601b311b501f33bce593fc80465 Author: Peter Stuge <peter(a)stuge.se> Date: Fri Feb 7 03:58:24 2014 +0100 Kconfig: Move vendorcode menu up from the bottom to above Chipset menu Change-Id: Ic97a497a634533f44d94df297ca6e35d94c34565 Signed-off-by: Peter Stuge <peter(a)stuge.se> --- src/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 88df9ae..50d414b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -249,6 +249,8 @@ config HAVE_ARCH_MEMMOVE bool default n +source src/vendorcode/Kconfig + menu "Chipset" comment "CPU" @@ -1086,5 +1088,3 @@ config POWER_BUTTON_IS_OPTIONAL default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE) help Internal option that controls ENABLE_POWER_BUTTON visibility. - -source src/vendorcode/Kconfig

1 0

Patch set updated for coreboot: 79ee493 rambi: add per-sku SPD support
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4872 -gerrit commit 79ee493ce5ffb9befedc270928fe7b09ef47db56 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 8 15:33:39 2013 -0500 rambi: add per-sku SPD support There are currently 4 SKUs: 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz Add each of the 4 spds to the build, and use the proper parameters to MRC to use the in-memory SPD information. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Noted 1024 bytes of SPD content. Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172280 --- src/mainboard/google/rambi/Kconfig | 4 ++ src/mainboard/google/rambi/Makefile.inc | 2 + src/mainboard/google/rambi/romstage.c | 45 ++++++++++++++++++++- src/mainboard/google/rambi/spd/Makefile.inc | 46 ++++++++++++++++++++++ .../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 +++++++++++++++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++++++++++++++ .../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 +++++++++++++++ .../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 +++++++++++++++ 8 files changed, 223 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 292d321..db6f4e2 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -32,4 +32,8 @@ config HAVE_ME_BIN bool default n +config SPD_CBFS_ADDRESS + hex "Location of SPD in CBFS" + default 0xfffec000 + endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/Makefile.inc b/src/mainboard/google/rambi/Makefile.inc index d3c6f0d..98e566b 100644 --- a/src/mainboard/google/rambi/Makefile.inc +++ b/src/mainboard/google/rambi/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +subdirs-y += spd + romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += gpio.c diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index f845173..d15a21d 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -19,19 +19,60 @@ #include <stdint.h> #include <string.h> +#include <cbfs.h> #include <console/console.h> +#include <baytrail/gpio.h> #include <baytrail/mrc_wrapper.h> #include <baytrail/romstage.h> +/* + * RAM_ID[2:0] are on GPIO_SSUS[39:37] + * 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz + * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz + * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + */ +#define SPD_SIZE 256 +#define GPIO_SSUS_37_PAD 57 +#define GPIO_SSUS_38_PAD 50 +#define GPIO_SSUS_39_PAD 58 + +static void *get_spd_pointer(char *spd_file_content, int total_spds) +{ + int ram_id = 0; + + ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); + ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); + ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); + + if (ram_id >= total_spds) + return NULL; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + void mainboard_romstage_entry(struct romstage_params *rp) { + struct cbfs_file *spd_file; + void *spd_content; + struct mrc_params mp = { .mainboard = { .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_SMBUS, - .spd_addrs = { 0xa0, 0xa2 }, + .dram_info_location = DRAM_INFO_SPD_MEM, }, }; + + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* Both channels are always present. */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE); + mp.mainboard.dram_data[0] = spd_content; + mp.mainboard.dram_data[1] = spd_content; + rp->mrc_params = &mp; romstage_common(rp); } diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc new file mode 100644 index 0000000..84695ab --- /dev/null +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +SPD_BIN = $(obj)/spd.bin + +# Order matters for SPD sources. The following indicies +# define the SPD data to use. +# 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz +# 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz +# 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA +SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 +SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab +spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS) diff --git a/src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex new file mode 100644 index 0000000..4bd8e0e --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 03 11 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +00 05 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 22 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 41 5f +48 4d 54 33 31 32 53 36 +44 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100644 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex new file mode 100644 index 0000000..f99c92a --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 03 11 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +50 00 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 6a 15 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex new file mode 100644 index 0000000..f3bcb56 --- /dev/null +++ b/src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 04 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 19 d2 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff

1 0

Patch set updated for coreboot: ac70f50 rambi: Add ncore GPIO config tables
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4874 -gerrit commit ac70f5099b621b472bcfbc30e97c33a15c0154ef Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Oct 9 15:29:46 2013 -0700 rambi: Add ncore GPIO config tables gpncore config tables were previously missing -- add them. Also, make the baytrail GPIO/PAD LUTs easier to read. TEST=Manual. Build + boot on bayleybay. BUG=chrome-os-partner:22865 Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172510 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 34 +++++++++++++++- src/soc/intel/baytrail/baytrail/gpio.h | 38 ++++++++++++++---- src/soc/intel/baytrail/gpio.c | 72 ++++++++++++++++++---------------- 3 files changed, 102 insertions(+), 42 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 8393e33..3f91366 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -20,6 +20,38 @@ #include <stdlib.h> #include <baytrail/gpio.h> +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_DEFAULT, /* GPIO 0 */ + GPIO_DEFAULT, /* GPIO 1 */ + GPIO_DEFAULT, /* GPIO 2 */ + GPIO_DEFAULT, /* GPIO 3 */ + GPIO_DEFAULT, /* GPIO 4 */ + GPIO_DEFAULT, /* GPIO 5 */ + GPIO_DEFAULT, /* GPIO 6 */ + GPIO_DEFAULT, /* GPIO 7 */ + GPIO_DEFAULT, /* GPIO 8 */ + GPIO_DEFAULT, /* GPIO 9 */ + GPIO_DEFAULT, /* GPIO 10 */ + GPIO_DEFAULT, /* GPIO 11 */ + GPIO_DEFAULT, /* GPIO 12 */ + GPIO_DEFAULT, /* GPIO 13 */ + GPIO_DEFAULT, /* GPIO 14 */ + GPIO_DEFAULT, /* GPIO 15 */ + GPIO_DEFAULT, /* GPIO 16 */ + GPIO_DEFAULT, /* GPIO 17 */ + GPIO_DEFAULT, /* GPIO 18 */ + GPIO_DEFAULT, /* GPIO 19 */ + GPIO_DEFAULT, /* GPIO 20 */ + GPIO_DEFAULT, /* GPIO 21 */ + GPIO_DEFAULT, /* GPIO 22 */ + GPIO_DEFAULT, /* GPIO 23 */ + GPIO_DEFAULT, /* GPIO 24 */ + GPIO_DEFAULT, /* GPIO 25 */ + GPIO_DEFAULT, /* GPIO 26 */ + GPIO_END +}; + /* SCORE GPIOs */ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_DEFAULT, /* GPIO 0 */ @@ -177,7 +209,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { }; static struct soc_gpio_config gpio_config = { - .ncore = NULL, + .ncore = gpncore_gpio_map, .score = gpscore_gpio_map, .ssus = gpssus_gpio_map }; diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index bdd36c1..f62f5c8 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -142,25 +142,47 @@ * if not set correctly, even if the pin isn't configured as GPIO. */ #define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +/* Configure GPIOs as legacy by default. GPNCORE doesn't support + * legacy config -- so also configure the pad regs as GPIO. We rely upon + * the fact that all GPNCORE pads are function 0 GPIO. */ #define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT } + +#define GPIO_INPUT_PD_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_DOWN | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT } + +#define GPIO_INPUT_NOPU \ + { .pad_conf0 = PAD_PU_10K | PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT_ENABLE, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } #define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT_ENABLE, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_LOW, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_LOW } #define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT, \ + { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT_ENABLE, \ + .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_HIGH, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } @@ -214,8 +236,10 @@ { .pad_conf0 = GPIO_LIST_END } /* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_PU_10K -#define GPIO_UNUSED GPIO_INPUT_PU_10K +#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT_PU GPIO_INPUT_PU_10K +#define GPIO_INPUT_PD GPIO_INPUT_PD_10K +#define GPIO_NC GPIO_INPUT_PU_10K #define GPIO_DEFAULT GPIO_FUNC0 struct soc_gpio_map { diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 9ae79c9..2916c99 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -23,53 +23,57 @@ /* GPIO-to-Pad LUTs */ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 25, 24, 23, 32, 33, 34, 36, 37, 35, 22, - 20, 21, 18, 38, 39, 1, 4, 8, 17, 0, - 3, 6, 16, 19, 2, 5, 9 }; + { 25, 24, 23, 32, 33, 34, 36, 37, /* [ 0: 7] */ + 35, 22, 20, 21, 18, 38, 39, 1, /* [ 8:15] */ + 4, 8, 17, 0, 3, 6, 16, 19, /* [16:23] */ + 2, 5, 9 }; /* [24:26] */ static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = - { 85, 89, 93, 96, 99, 102, 98, 101, 34, 37, - 36, 38, 39, 35, 40, 84, 62, 61, 64, 59, - 54, 56, 60, 55, 63, 57, 51, 50, 53, 47, - 52, 49, 48, 43, 46, 41, 45, 42, 58, 44, - 95, 105, 70, 68, 67, 66, 69, 71, 65, 72, - 86, 90, 88, 92, 103, 77, 79, 83, 78, 81, - 80, 82, 13, 12, 15, 14, 17, 18, 19, 16, - 2, 1, 0, 4, 6, 7, 9, 8, 33, 32, - 31, 30, 29, 27, 25, 28, 26, 23, 21, 20, - 24, 22, 5, 3, 10, 11, 106, 87, 91, 104, - 97, 100 }; + { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ + 106, 87, 91, 104, 97, 100 }; /* [96:101] */ static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = - { 29, 33, 30, 31, 32, 34, 36, 35, 38, 37, - 18, 7, 11, 20, 17, 1, 8, 10, 19, 12, - 0, 2, 23, 39, 28, 27, 22, 21, 24, 25, - 26, 51, 56, 54, 49, 55, 48, 57, 50, 58, - 52, 53, 59, 40 }; + { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ + 52, 53, 59, 40 }; /* [40:43] */ /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { - .gpio_count = GPNCORE_COUNT, - .gpio_to_pad = gpncore_gpio_to_pad, - .legacy_base = GP_LEGACY_BASE_NONE, - .pad_base = GPNCORE_PAD_BASE, - .has_wake_en = 0, + .gpio_count = GPNCORE_COUNT, + .gpio_to_pad = gpncore_gpio_to_pad, + .legacy_base = GP_LEGACY_BASE_NONE, + .pad_base = GPNCORE_PAD_BASE, + .has_wake_en = 0, }; static const struct gpio_bank gpscore_bank = { - .gpio_count = GPSCORE_COUNT, - .gpio_to_pad = gpscore_gpio_to_pad, - .legacy_base = GPSCORE_LEGACY_BASE, - .pad_base = GPSCORE_PAD_BASE, - .has_wake_en = 0, + .gpio_count = GPSCORE_COUNT, + .gpio_to_pad = gpscore_gpio_to_pad, + .legacy_base = GPSCORE_LEGACY_BASE, + .pad_base = GPSCORE_PAD_BASE, + .has_wake_en = 0, }; static const struct gpio_bank gpssus_bank = { - .gpio_count = GPSSUS_COUNT, - .gpio_to_pad = gpssus_gpio_to_pad, - .legacy_base = GPSSUS_LEGACY_BASE, - .pad_base = GPSSUS_PAD_BASE, - .has_wake_en = 1, + .gpio_count = GPSSUS_COUNT, + .gpio_to_pad = gpssus_gpio_to_pad, + .legacy_base = GPSSUS_LEGACY_BASE, + .pad_base = GPSSUS_PAD_BASE, + .has_wake_en = 1, }; static void setup_gpios(const struct soc_gpio_map *gpios,

1 0

Patch set updated for coreboot: cf672d2 rambi: Add platform GPIO configuration tables
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4875 -gerrit commit cf672d2db07d1fd972d462cd38e5625a69634ffb Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Oct 10 13:41:19 2013 -0700 rambi: Add platform GPIO configuration tables Configure GPIOs according to function on board. TEST=compile only. BUG=chrome-os-partner:22863 Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172657 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 347 +++++++++++++++++++------------------- 1 file changed, 174 insertions(+), 173 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 3f91366..d7082be 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -20,191 +20,192 @@ #include <stdlib.h> #include <baytrail/gpio.h> +/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */ /* NCORE GPIOs */ static const struct soc_gpio_map gpncore_gpio_map[] = { - GPIO_DEFAULT, /* GPIO 0 */ - GPIO_DEFAULT, /* GPIO 1 */ - GPIO_DEFAULT, /* GPIO 2 */ - GPIO_DEFAULT, /* GPIO 3 */ - GPIO_DEFAULT, /* GPIO 4 */ - GPIO_DEFAULT, /* GPIO 5 */ - GPIO_DEFAULT, /* GPIO 6 */ - GPIO_DEFAULT, /* GPIO 7 */ - GPIO_DEFAULT, /* GPIO 8 */ - GPIO_DEFAULT, /* GPIO 9 */ - GPIO_DEFAULT, /* GPIO 10 */ - GPIO_DEFAULT, /* GPIO 11 */ - GPIO_DEFAULT, /* GPIO 12 */ - GPIO_DEFAULT, /* GPIO 13 */ - GPIO_DEFAULT, /* GPIO 14 */ - GPIO_DEFAULT, /* GPIO 15 */ - GPIO_DEFAULT, /* GPIO 16 */ - GPIO_DEFAULT, /* GPIO 17 */ - GPIO_DEFAULT, /* GPIO 18 */ - GPIO_DEFAULT, /* GPIO 19 */ - GPIO_DEFAULT, /* GPIO 20 */ - GPIO_DEFAULT, /* GPIO 21 */ - GPIO_DEFAULT, /* GPIO 22 */ - GPIO_DEFAULT, /* GPIO 23 */ - GPIO_DEFAULT, /* GPIO 24 */ - GPIO_DEFAULT, /* GPIO 25 */ - GPIO_DEFAULT, /* GPIO 26 */ + GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */ + GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */ + GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */ + GPIO_NC, /* S0_NC03 - NC */ + GPIO_NC, /* S0_NC04 - NC */ + GPIO_NC, /* S0_NC05 - NC */ + GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */ + GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */ + GPIO_NC, /* S0_NC08 - NC */ + GPIO_FUNC2, /* S0_NC09 - SOC_DISP_ON_C */ + GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */ + GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */ + GPIO_NC, /* S0_NC12 - NC */ + GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ + GPIO_NC, /* S0_NC14 - NC */ + GPIO_NC, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_NC, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_NC, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_NC, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_NC, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_NC, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_NC, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_NC, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_NC, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_NC, /* S0_NC24 - NC */ + GPIO_NC, /* S0_NC25 - NC */ + GPIO_NC, /* S0_NC26 - NC */ GPIO_END }; /* SCORE GPIOs */ static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_DEFAULT, /* GPIO 0 */ - GPIO_DEFAULT, /* GPIO 1 */ - GPIO_DEFAULT, /* GPIO 2 */ - GPIO_DEFAULT, /* GPIO 3 */ - GPIO_DEFAULT, /* GPIO 4 */ - GPIO_DEFAULT, /* GPIO 5 */ - GPIO_DEFAULT, /* GPIO 6 */ - GPIO_DEFAULT, /* GPIO 7 */ - GPIO_DEFAULT, /* GPIO 8 */ - GPIO_DEFAULT, /* GPIO 9 */ - GPIO_DEFAULT, /* GPIO 10 */ - GPIO_DEFAULT, /* GPIO 11 */ - GPIO_DEFAULT, /* GPIO 12 */ - GPIO_DEFAULT, /* GPIO 13 */ - GPIO_DEFAULT, /* GPIO 14 */ - GPIO_DEFAULT, /* GPIO 15 */ - GPIO_DEFAULT, /* GPIO 16 */ - GPIO_DEFAULT, /* GPIO 17 */ - GPIO_DEFAULT, /* GPIO 18 */ - GPIO_DEFAULT, /* GPIO 19 */ - GPIO_DEFAULT, /* GPIO 20 */ - GPIO_DEFAULT, /* GPIO 21 */ - GPIO_DEFAULT, /* GPIO 22 */ - GPIO_DEFAULT, /* GPIO 23 */ - GPIO_DEFAULT, /* GPIO 24 */ - GPIO_DEFAULT, /* GPIO 25 */ - GPIO_DEFAULT, /* GPIO 26 */ - GPIO_DEFAULT, /* GPIO 27 */ - GPIO_DEFAULT, /* GPIO 28 */ - GPIO_DEFAULT, /* GPIO 29 */ - GPIO_DEFAULT, /* GPIO 30 */ - GPIO_DEFAULT, /* GPIO 31 */ - GPIO_DEFAULT, /* GPIO 32 */ - GPIO_DEFAULT, /* GPIO 33 */ - GPIO_DEFAULT, /* GPIO 34 */ - GPIO_DEFAULT, /* GPIO 35 */ - GPIO_DEFAULT, /* GPIO 36 */ - GPIO_DEFAULT, /* GPIO 37 */ - GPIO_DEFAULT, /* GPIO 38 */ - GPIO_DEFAULT, /* GPIO 39 */ - GPIO_DEFAULT, /* GPIO 40 */ - GPIO_DEFAULT, /* GPIO 41 */ - GPIO_DEFAULT, /* GPIO 42 */ - GPIO_DEFAULT, /* GPIO 43 */ - GPIO_DEFAULT, /* GPIO 44 */ - GPIO_DEFAULT, /* GPIO 45 */ - GPIO_DEFAULT, /* GPIO 46 */ - GPIO_DEFAULT, /* GPIO 47 */ - GPIO_DEFAULT, /* GPIO 48 */ - GPIO_DEFAULT, /* GPIO 49 */ - GPIO_DEFAULT, /* GPIO 50 */ - GPIO_FUNC1, /* GPIO 51 - SMBus DATA */ - GPIO_FUNC1, /* GPIO 52 - SMBus CLK */ - GPIO_DEFAULT, /* GPIO 53 */ - GPIO_DEFAULT, /* GPIO 54 */ - GPIO_DEFAULT, /* GPIO 55 */ - GPIO_DEFAULT, /* GPIO 56 */ - GPIO_FUNC1, /* GPIO 57 - COM1 TXD */ - GPIO_DEFAULT, /* GPIO 58 */ - GPIO_DEFAULT, /* GPIO 59 */ - GPIO_DEFAULT, /* GPIO 60 */ - GPIO_FUNC1, /* GPIO 61 - COM1 RXD */ - GPIO_DEFAULT, /* GPIO 62 */ - GPIO_DEFAULT, /* GPIO 63 */ - GPIO_DEFAULT, /* GPIO 64 */ - GPIO_DEFAULT, /* GPIO 65 */ - GPIO_DEFAULT, /* GPIO 66 */ - GPIO_DEFAULT, /* GPIO 67 */ - GPIO_DEFAULT, /* GPIO 68 */ - GPIO_DEFAULT, /* GPIO 69 */ - GPIO_DEFAULT, /* GPIO 70 */ - GPIO_DEFAULT, /* GPIO 71 */ - GPIO_DEFAULT, /* GPIO 72 */ - GPIO_DEFAULT, /* GPIO 73 */ - GPIO_DEFAULT, /* GPIO 74 */ - GPIO_DEFAULT, /* GPIO 75 */ - GPIO_DEFAULT, /* GPIO 76 */ - GPIO_DEFAULT, /* GPIO 77 */ - GPIO_DEFAULT, /* GPIO 78 */ - GPIO_DEFAULT, /* GPIO 79 */ - GPIO_DEFAULT, /* GPIO 80 */ - GPIO_DEFAULT, /* GPIO 81 */ - GPIO_DEFAULT, /* GPIO 82 */ - GPIO_DEFAULT, /* GPIO 83 */ - GPIO_DEFAULT, /* GPIO 84 */ - GPIO_DEFAULT, /* GPIO 85 */ - GPIO_DEFAULT, /* GPIO 86 */ - GPIO_DEFAULT, /* GPIO 87 */ - GPIO_DEFAULT, /* GPIO 88 */ - GPIO_DEFAULT, /* GPIO 89 */ - GPIO_DEFAULT, /* GPIO 90 */ - GPIO_DEFAULT, /* GPIO 91 */ - GPIO_DEFAULT, /* GPIO 92 */ - GPIO_DEFAULT, /* GPIO 93 */ - GPIO_DEFAULT, /* GPIO 94 */ - GPIO_DEFAULT, /* GPIO 95 */ - GPIO_DEFAULT, /* GPIO 96 */ - GPIO_DEFAULT, /* GPIO 97 */ - GPIO_DEFAULT, /* GPIO 98 */ - GPIO_DEFAULT, /* GPIO 99 */ - GPIO_DEFAULT, /* GPIO 100 */ - GPIO_DEFAULT, /* GPIO 101 */ + GPIO_INPUT, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ + GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ + GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ + GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */ + GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */ + GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */ + GPIO_NC, /* S0-SC007 - SD3_WP (NC) */ + GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */ + GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */ + GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */ + GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */ + GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */ + GPIO_NC, /* S0-SC013 - NC */ + GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ + GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ + GPIO_FUNC3, /* S0-SC016 - MMC1_CLK */ + GPIO_FUNC3, /* S0-SC017 - MMC1_D[0] */ + GPIO_FUNC3, /* S0-SC018 - MMC1_D[1] */ + GPIO_FUNC3, /* S0-SC019 - MMC1_D[2] */ + GPIO_FUNC3, /* S0-SC020 - MMC1_D[3] */ + GPIO_FUNC3, /* S0-SC021 - MMC1_D[4] */ + GPIO_FUNC3, /* S0-SC022 - MMC1_D[5] */ + GPIO_FUNC3, /* S0-SC023 - MMC1_D[6] */ + GPIO_FUNC3, /* S0-SC024 - MMC1_D[7] */ + GPIO_FUNC3, /* S0-SC025 - MMC1_CMD */ + GPIO_FUNC3, /* S0-SC026 - MMC1_RST */ + GPIO_NC, /* S0-SC027 - NC */ + GPIO_NC, /* S0-SC028 - NC */ + GPIO_NC, /* S0-SC029 - NC */ + GPIO_NC, /* S0-SC030 - NC */ + GPIO_NC, /* S0-SC031 - NC */ + GPIO_NC, /* S0-SC032 - NC */ + GPIO_NC, /* S0-SC033 - SD3_CLK (NC) */ + GPIO_NC, /* S0-SC034 - SD3_D0 (NC) */ + GPIO_NC, /* S0-SC035 - SD3_D1 (NC) */ + GPIO_NC, /* S0-SC036 - SD3_D2 (NC) */ + GPIO_NC, /* S0-SC037 - SD3_D3 (NC) */ + GPIO_NC, /* S0-SC038 - SD3_CD# (NC) */ + GPIO_NC, /* S0-SC039 - SD3_CMD (NC) */ + GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN (NC) */ + GPIO_NC, /* S0-SC041 - SDIO3_PWR_EN# (NC)*/ + GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */ + GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */ + GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */ + GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */ + GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */ + GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ + GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ + GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ + GPIO_FUNC1, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ + GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ + GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ + GPIO_DEFAULT, /* S0-SC054 - NC */ + GPIO_INPUT, /* S0-SC055 - TRACKPAD_INT_DX - INT */ + GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ + GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ + GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ + GPIO_INPUT, /* S0-SC059 - EC_IN_RW_C */ + GPIO_NC, /* S0-SC060 - NC */ + GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */ + GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */ + GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */ + GPIO_FUNC1, /* S0-SC064 - I2S_DIN */ + GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */ + GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */ + GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ + GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ + GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ + GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_NC, /* S0-SC071 - NC */ + GPIO_INPUT, /* S0-SC072 - TOUCH_INT_L_DX - INT */ + GPIO_NC, /* S0-SC073 - NC */ + GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ + GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ + GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */ + GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */ + GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */ + GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */ + GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */ + GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */ + GPIO_NC, /* S0-SC082 - NC */ + GPIO_NC, /* S0-SC083 - NC */ + GPIO_NC, /* S0-SC084 - NC */ + GPIO_NC, /* S0-SC085 - NC */ + GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */ + GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */ + GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */ + GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */ + GPIO_NC, /* S0-SC090 - NC */ + GPIO_NC, /* S0-SC091 - NC */ + GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */ + GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */ + GPIO_NC, /* S0-SC094 - NC */ + GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */ + GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */ + GPIO_NC, /* S0-SC097 - NC */ + GPIO_NC, /* S0-SC098 - NC */ + GPIO_NC, /* S0-SC099 - NC */ + GPIO_NC, /* S0-SC100 - NC */ + GPIO_NC, /* S0-SC101 - NC*/ GPIO_END }; /* SSUS GPIOs */ static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_DEFAULT, /* GPIO 0 */ - GPIO_DEFAULT, /* GPIO 1 */ - GPIO_DEFAULT, /* GPIO 2 */ - GPIO_DEFAULT, /* GPIO 3 */ - GPIO_DEFAULT, /* GPIO 4 */ - GPIO_DEFAULT, /* GPIO 5 */ - GPIO_DEFAULT, /* GPIO 6 */ - GPIO_DEFAULT, /* GPIO 7 */ - GPIO_DEFAULT, /* GPIO 8 */ - GPIO_DEFAULT, /* GPIO 9 */ - GPIO_DEFAULT, /* GPIO 10 */ - GPIO_DEFAULT, /* GPIO 11 */ - GPIO_DEFAULT, /* GPIO 12 */ - GPIO_DEFAULT, /* GPIO 13 */ - GPIO_DEFAULT, /* GPIO 14 */ - GPIO_DEFAULT, /* GPIO 15 */ - GPIO_DEFAULT, /* GPIO 16 */ - GPIO_DEFAULT, /* GPIO 17 */ - GPIO_DEFAULT, /* GPIO 18 */ - GPIO_DEFAULT, /* GPIO 19 */ - GPIO_DEFAULT, /* GPIO 20 */ - GPIO_DEFAULT, /* GPIO 21 */ - GPIO_DEFAULT, /* GPIO 22 */ - GPIO_DEFAULT, /* GPIO 23 */ - GPIO_DEFAULT, /* GPIO 24 */ - GPIO_DEFAULT, /* GPIO 25 */ - GPIO_DEFAULT, /* GPIO 26 */ - GPIO_DEFAULT, /* GPIO 27 */ - GPIO_DEFAULT, /* GPIO 28 */ - GPIO_DEFAULT, /* GPIO 29 */ - GPIO_DEFAULT, /* GPIO 30 */ - GPIO_DEFAULT, /* GPIO 31 */ - GPIO_DEFAULT, /* GPIO 32 */ - GPIO_DEFAULT, /* GPIO 33 */ - GPIO_DEFAULT, /* GPIO 34 */ - GPIO_DEFAULT, /* GPIO 35 */ - GPIO_DEFAULT, /* GPIO 36 */ - GPIO_DEFAULT, /* GPIO 37 */ - GPIO_DEFAULT, /* GPIO 38 */ - GPIO_DEFAULT, /* GPIO 39 */ - GPIO_DEFAULT, /* GPIO 40 */ - GPIO_DEFAULT, /* GPIO 41 */ - GPIO_DEFAULT, /* GPIO 42 */ - GPIO_DEFAULT, /* GPIO 43 */ + GPIO_NC, /* S500 - PCH_WAKE# (NC) */ + GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ + GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ + GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ + GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ + GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ + GPIO_INPUT, /* S507 - SOC_KBC_SMI - INT */ + GPIO_NC, /* S508 - NC */ + GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ + GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ + GPIO_FUNC0, /* S511 - SUSPWRDNACK */ + GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ + GPIO_FUNC0, /* S513 - SLP_SX */ + GPIO_NC, /* S514 - NC */ + GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */ + GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */ + GPIO_NC, /* S517 - NC */ + GPIO_FUNC0, /* S518 - SUS_STAT# */ + GPIO_FUNC0, /* S519 - USB_OC0# */ + GPIO_FUNC0, /* S520 - USB_OC1# */ + GPIO_NC, /* S521 - NC */ + GPIO_NC, /* S522 - XDP_GPIO_DFX0 */ + GPIO_NC, /* S523 - XDP_GPIO_DFX1 */ + GPIO_NC, /* S524 - XDP_GPIO_DFX2 */ + GPIO_NC, /* S525 - XDP_GPIO_DFX3 */ + GPIO_NC, /* S526 - XDP_GPIO_DFX4 */ + GPIO_NC, /* S527 - XDP_GPIO_DFX5 */ + GPIO_NC, /* S528 - XDP_GPIO_DFX6 */ + GPIO_NC, /* S529 - XDP_GPIO_DFX7 */ + GPIO_NC, /* S530 - XDP_GPIO_DFX8 */ + GPIO_NC, /* S531 - NC */ + GPIO_NC, /* S532 - NC */ + GPIO_NC, /* S533 - NC */ + GPIO_NC, /* S534 - NC */ + GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ + GPIO_NC, /* S536 - NC */ + GPIO_INPUT, /* S537 - RAM_ID0 */ + GPIO_INPUT, /* S538 - RAM_ID1 */ + GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_NC, /* S540 - NC */ + GPIO_NC, /* S541 - NC */ + GPIO_NC, /* S542 - NC */ + GPIO_NC, /* S543 - NC */ GPIO_END };

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Patch set updated for coreboot: 80d99ae baytrail: add reset support
by Aaron Durbin 06 Feb '14

06 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4878 -gerrit commit 80d99aef700d334f2b59f1f786c1910628ded86d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 20:54:57 2013 -0500 baytrail: add reset support Bay Trail has the following types of resets it supports: - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but with ETR[20] set. While these are documented this support currently provides support for 2nd soft reset as well as cold and warm reset. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted. Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172710 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/Makefile.inc | 2 ++ src/soc/intel/baytrail/baytrail/pmc.h | 12 +++++++++ src/soc/intel/baytrail/baytrail/reset.h | 36 +++++++++++++++++++++++++ src/soc/intel/baytrail/reset.c | 47 +++++++++++++++++++++++++++++++++ 5 files changed, 98 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 4cd2133..293ed21 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_IN_CBFS select DYNAMIC_CBMEM select HAVE_SMI_HANDLER + select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index b4474c0..9695a70 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -20,6 +20,8 @@ romstage-y += iosf.c ramstage-y += northcluster.c ramstage-y += ramstage.c ramstage-y += gpio.c +romstage-y += reset.c +ramstage-y += reset.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index 2cf1f00..b85800a 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -26,6 +26,12 @@ /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define GEN_PMCONF1 0x20 # define UART_EN (1 << 24) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define TCO_RLD 0x60 @@ -37,4 +43,10 @@ # define TCO_TMR_HALT (1 << 11) #define TCO_TMR 0x70 +/* I/O ports */ +#define RST_CNT 0xcf9 +# define FULL_RST (1 << 3) +# define RST_CPU (1 << 2) +# define SYS_RST (1 << 1) + #endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/reset.h b/src/soc/intel/baytrail/baytrail/reset.h new file mode 100644 index 0000000..dbf0fd2 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/reset.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RESET_H_ +#define _BAYTRAIL_RESET_H_ +#include <reset.h> + +/* Bay Trail has the following types of resets: + * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 + * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 + * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 + * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 + * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but + * with ETR[20] set. + */ + +void cold_reset(void); +void warm_reset(void); + +#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/baytrail/reset.c b/src/soc/intel/baytrail/reset.c new file mode 100644 index 0000000..a421ec9 --- /dev/null +++ b/src/soc/intel/baytrail/reset.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/pmc.h> +#include <baytrail/reset.h> + +void cold_reset(void) +{ + /* S0->S5->S0 trip. */ + outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); +} + +void warm_reset(void) +{ + /* PMC_PLTRST# asserted. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void soft_reset(void) +{ + /* Sends INIT# to CPU */ + outb(RST_CPU, RST_CNT); +} + +void hard_reset(void) +{ + /* Don't power cycle on hard_reset(). It's not really clear what the + * semantics should be for the meaning of hard_reset(). */ + warm_reset(); +}

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coreboot-gerrit February 2014