coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: d0b600c Remove CACHE_ROM.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit d0b600cd0bb792504cbe051a849a1dbe7fa816e7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cache coherency in worst cases. Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 20 +------ src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 2 insertions(+), 158 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f8d295e..6e6428b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -782,9 +782,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..4425ed3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index dfb9c94..fc18603 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -184,16 +184,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources(addr_space, mask, match, MTRR_TYPE_WRCOMB); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -365,61 +355,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -467,17 +402,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..b8a372b 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,24 +67,12 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that +/* ROM caching can be used after variable MTRRs are set up. + * Be sure to check the console log when adding WRCOMB resources. Beware that * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the * rom caching will be disabled if all threads run the MTRR code. Therefore, * one needs to call x86_mtrr_enable_rom_caching() after all threads of the * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 613593e..d3311ef 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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New patch to review for coreboot: 23a8def usbdebug: Remove EHCI_DEBUG_OFFSET
by Kyösti Mälkki 09 Feb '14

09 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5176 -gerrit commit 23a8def8993c7f62ec6b5f9797b1b56e85b65e10 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 9 19:21:30 2014 +0200 usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 9 +++++--- src/drivers/usb/ehci_debug.h | 2 +- src/drivers/usb/pci_ehci.c | 34 +++++++++++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/Kconfig | 4 ---- src/southbridge/amd/cimx/sb700/Kconfig | 4 ---- src/southbridge/amd/cimx/sb800/Kconfig | 4 ---- src/southbridge/amd/sb600/Kconfig | 4 ---- src/southbridge/amd/sb700/Kconfig | 4 ---- src/southbridge/amd/sb800/Kconfig | 4 ---- src/southbridge/intel/bd82x6x/Kconfig | 4 ---- src/southbridge/intel/fsp_bd82x6x/Kconfig | 4 ---- src/southbridge/intel/i82801dx/Kconfig | 4 ---- src/southbridge/intel/i82801ex/Kconfig | 4 ---- src/southbridge/intel/i82801gx/Kconfig | 4 ---- src/southbridge/intel/i82801ix/Kconfig | 4 ---- src/southbridge/intel/ibexpeak/Kconfig | 4 ---- src/southbridge/intel/lynxpoint/Kconfig | 4 ---- src/southbridge/intel/sch/Kconfig | 4 ---- src/southbridge/nvidia/ck804/Kconfig | 4 ---- src/southbridge/nvidia/mcp55/Kconfig | 4 ---- src/southbridge/sis/sis966/Kconfig | 3 --- 21 files changed, 39 insertions(+), 77 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 26d61fb..beb553e 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -588,6 +588,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ int port_map_tried; int playtimes = 3; + dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset); + ehci_caps = (struct ehci_caps *)ehci_bar; ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); @@ -608,7 +610,6 @@ try_next_port: debug_port = HCS_DEBUG_PORT(hcs_params); n_ports = HCS_N_PORTS(hcs_params); - dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar); dprintk(BIOS_INFO, "debug_port: %d\n", debug_port); dprintk(BIOS_INFO, "n_ports: %d\n", n_ports); @@ -985,11 +986,13 @@ struct dbgp_pipe *dbgp_console_input(void) int usbdebug_init(void) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); + unsigned int ehci_base, dbg_offset; #if !defined(__PRE_RAM__) && !defined(__SMM__) if (!get_usbdebug_from_cbmem(dbg_info)) return 0; #endif - ehci_debug_hw_enable(); - return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); + if (ehci_debug_hw_enable(&ehci_base, &dbg_offset)) + return -1; + return usbdebug_init_(ehci_base, dbg_offset, dbg_info); } diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index 462eb23..2e549d2 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -24,7 +24,7 @@ void usbdebug_re_enable(unsigned ehci_base); void usbdebug_disable(void); -void ehci_debug_hw_enable(void); +int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset); void ehci_debug_select_port(unsigned int port); #endif /* _EHCI_DEBUG_H_ */ diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 7c715f6..f374810 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -34,12 +34,42 @@ static struct device_operations *ehci_drv_ops; static struct device_operations ehci_dbg_ops; #endif -void ehci_debug_hw_enable(void) +int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { -#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); + +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = dbg_dev; +#else + device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev)); #endif + + u16 status = pci_read_config16(dev, PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 1; + + /* Scan capabilities list. */ + u8 pos = pci_read_config8(dev, PCI_CAPABILITY_LIST); + int i; + for (i=0; pos >= 0x40 && i < 48; i++) { + u32 cap = pci_read_config32(dev, pos); + printk(BIOS_SPEW, "cap %08x\n", cap); + if ((u8) cap != PCI_CAP_ID_EHCI_DEBUG) { + pos = (cap >> 8) & 0xfc; + continue; + } + + /* FIXME: We should remove static EHCI_BAR_INDEX. */ + u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1); + if (dbg_bar != EHCI_BAR_INDEX) + break; + *base = CONFIG_EHCI_BAR; + *dbg_offset = (cap>>16) & 0x1ffc; + printk(BIOS_SPEW, "base %08x offset %08x\n", *base, *dbg_offset); + return 0; + } + return 1; } void ehci_debug_select_port(unsigned int port) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 1550cb4..dd5120d 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -43,10 +43,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" default y diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 4304357..d8bad86 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -54,10 +54,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb700/bootblock.c" diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 37aff9e..832655d 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -209,10 +209,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - choice prompt "Fan Control" default SB800_NO_FAN_CONTROL diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index fe9468d..4d5fff4 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -32,10 +32,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - choice prompt "SATA Mode" default SATA_MODE_IDE diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index b0c92dc..e391fc8 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -45,8 +45,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - endif # SOUTHBRIDGE_AMD_SB700 diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 9547d3e..24dc007 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -37,8 +37,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - endif # SOUTHBRIDGE_AMD_SB800 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index d060dae..9cfa5d5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,10 +41,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 1a8e80a..b2b4929 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -37,10 +37,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/fsp_bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index f7f93a7..8ef778f 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -33,8 +33,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x80 - endif diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig index e4e9160..caa5c79 100644 --- a/src/southbridge/intel/i82801ex/Kconfig +++ b/src/southbridge/intel/i82801ex/Kconfig @@ -11,8 +11,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - endif diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 62c6b43..777b69b 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -32,10 +32,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801gx/bootblock.c" diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8a4a53e..493be60 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -33,10 +33,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801ix/bootblock.c" diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 97d5883..c05fe43 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -39,10 +39,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..bfb7b73 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -44,10 +44,6 @@ config EHCI_BAR hex default 0xe8000000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/lynxpoint/bootblock.c" diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index 432fb8d..d320a53 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -30,10 +30,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config HAVE_CMC bool "Add a CMC state machine binary" help diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index b6f718e..e21f79e 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -14,10 +14,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x98 - config CK804_USE_NIC bool default n diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..89aa452 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -14,10 +14,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x98 - config MCP55_USE_NIC bool default n diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..1fbd57d 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -12,6 +12,3 @@ config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 -config EHCI_DEBUG_OFFSET - hex - default 0x98 if SOUTHBRIDGE_SIS_SIS966

1 0

New patch to review for coreboot: a0cabe9 usbdebug: Split PCI EHCI part
by Kyösti Mälkki 09 Feb '14

09 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5175 -gerrit commit a0cabe945ecc455dc1cc5be77adb20b8e623723b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 7 19:24:23 2014 +0200 usbdebug: Split PCI EHCI part There are EHCI compatible host controllers on ARM without PCI bus architecture. Currently we have not come across one with the debug capability though. Change-Id: I8775c9814f6fdf8754f97265118a7186369d721d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/Makefile.inc | 4 +- src/drivers/usb/ehci_debug.c | 84 ++++--------------------------------- src/drivers/usb/ehci_debug.h | 30 ++++++++++++++ src/drivers/usb/pci_ehci.c | 98 ++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci_def.h | 1 + 5 files changed, 140 insertions(+), 77 deletions(-) diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc index 43931a9..043ebe1 100644 --- a/src/drivers/usb/Makefile.inc +++ b/src/drivers/usb/Makefile.inc @@ -1,3 +1,3 @@ -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c pci_ehci.c -ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c +ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 7413a8a..26d61fb 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -21,15 +21,13 @@ #include <stddef.h> #include <console/console.h> #include <console/usb.h> -#include <device/pci_ehci.h> #include <arch/io.h> -#include <device/pci.h> -#include <device/pci_def.h> #include <arch/byteorder.h> #include <arch/early_variables.h> #include <string.h> #include <cbmem.h> +#include "ehci_debug.h" #include "usb_ch9.h" #include "ehci.h" @@ -107,8 +105,6 @@ static int dbgp_enabled(void); #define USB_PID_DATA_TOGGLE 0x88 #define DBGP_CLAIM (DBGP_OWNER | DBGP_ENABLED | DBGP_INUSE) -#define PCI_CAP_ID_EHCI_DEBUG 0xa - #define HUB_ROOT_RESET_TIME 50 /* times are in msec */ #define HUB_SHORT_RESET_TIME 10 #define HUB_LONG_RESET_TIME 200 @@ -119,10 +115,6 @@ static int dbgp_enabled(void); #define DBGP_MAX_PACKET 8 static struct ehci_debug_info glob_dbg_info CAR_GLOBAL; -#if !defined(__PRE_RAM__) && !defined(__SMM__) -static struct device_operations *ehci_drv_ops; -static struct device_operations ehci_dbg_ops; -#endif static inline struct ehci_debug_info *dbgp_ehci_info(void) { @@ -580,19 +572,6 @@ err: } #endif /* CONFIG_USBDEBUG_OPTIONAL_HUB_PORT */ -static void enable_usbdebug(void) -{ -#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); - pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); -#endif -} - -static void set_debug_port(unsigned int port) -{ - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); - pci_ehci_dbg_set_port(dbg_dev, port); -} static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info) { @@ -617,9 +596,9 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ memset(&info->ep_pipe, 0, sizeof (info->ep_pipe)); if (CONFIG_USBDEBUG_DEFAULT_PORT > 0) - set_debug_port(CONFIG_USBDEBUG_DEFAULT_PORT); + ehci_debug_select_port(CONFIG_USBDEBUG_DEFAULT_PORT); else - set_debug_port(1); + ehci_debug_select_port(1); try_next_time: port_map_tried = 0; @@ -640,7 +619,7 @@ try_next_port: if(port_map_tried && (new_debug_port != debug_port)) { if(--playtimes) { - set_debug_port(debug_port); + ehci_debug_select_port(debug_port); goto try_next_time; } return -1; @@ -847,11 +826,11 @@ next_debug_port: port_map_tried |= (1 << (debug_port - 1)); new_debug_port = ((debug_port-1 + 1) % n_ports) + 1; if (port_map_tried != ((1 << n_ports) - 1)) { - set_debug_port(new_debug_port); + ehci_debug_select_port(new_debug_port); goto try_next_port; } if (--playtimes) { - set_debug_port(new_debug_port); + ehci_debug_select_port(new_debug_port); goto try_next_time; } #else @@ -930,7 +909,7 @@ unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe) } #if !defined(__PRE_RAM__) && !defined(__SMM__) -static void usbdebug_re_enable(unsigned ehci_base) +void usbdebug_re_enable(unsigned ehci_base) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); unsigned diff; @@ -948,7 +927,7 @@ static void usbdebug_re_enable(unsigned ehci_base) dbg_info->ep_pipe[i].status |= DBGP_EP_ENABLED; } -static void usbdebug_disable(void) +void usbdebug_disable(void) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); int i; @@ -956,40 +935,6 @@ static void usbdebug_disable(void) dbg_info->ep_pipe[i].status &= ~DBGP_EP_ENABLED; } -static void pci_ehci_set_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev)); - usbdebug_disable(); - - if (ehci_drv_ops->set_resources) - ehci_drv_ops->set_resources(dev); - res = find_resource(dev, EHCI_BAR_INDEX); - if (!res) - return; - - usbdebug_re_enable((u32)res->base); - report_resource_stored(dev, res, ""); - printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev)); -} - -void pci_ehci_read_resources(struct device *dev) -{ - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); - - if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { - memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); - ehci_drv_ops = dev->ops; - ehci_dbg_ops.set_resources = pci_ehci_set_resources; - dev->ops = &ehci_dbg_ops; - printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev)); - } else { - printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev)); - } - - pci_dev_read_resources(dev); -} #endif #if !defined(__PRE_RAM__) && !defined(__SMM__) @@ -1022,17 +967,6 @@ static void migrate_ehci_debug(void) CAR_MIGRATE(migrate_ehci_debug); #endif -unsigned long pci_ehci_base_regs(pci_devfn_t sdev) -{ -#ifdef __SIMPLE_DEVICE__ - unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; -#else - device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev)); - unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f; -#endif - return base + HC_LENGTH(read32(base)); -} - int dbgp_ep_is_active(struct dbgp_pipe *pipe) { return (pipe->status & DBGP_EP_STATMASK) == (DBGP_EP_VALID | DBGP_EP_ENABLED); @@ -1056,6 +990,6 @@ int usbdebug_init(void) if (!get_usbdebug_from_cbmem(dbg_info)) return 0; #endif - enable_usbdebug(); + ehci_debug_hw_enable(); return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h new file mode 100644 index 0000000..462eb23 --- /dev/null +++ b/src/drivers/usb/ehci_debug.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 AMD + * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef _EHCI_DEBUG_H_ +#define _EHCI_DEBUG_H_ + +void usbdebug_re_enable(unsigned ehci_base); +void usbdebug_disable(void); + +void ehci_debug_hw_enable(void); +void ehci_debug_select_port(unsigned int port); + +#endif /* _EHCI_DEBUG_H_ */ diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c new file mode 100644 index 0000000..7c715f6 --- /dev/null +++ b/src/drivers/usb/pci_ehci.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com) + * Copyright (C) 2007 AMD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stddef.h> +#include <console/console.h> +#include <device/pci_ehci.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <string.h> + +#include "ehci_debug.h" +#include "ehci.h" + +#if !defined(__PRE_RAM__) && !defined(__SMM__) +static struct device_operations *ehci_drv_ops; +static struct device_operations ehci_dbg_ops; +#endif + +void ehci_debug_hw_enable(void) +{ +#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); +#endif +} + +void ehci_debug_select_port(unsigned int port) +{ + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_ehci_dbg_set_port(dbg_dev, port); +} + +#if !defined(__PRE_RAM__) && !defined(__SMM__) +static void pci_ehci_set_resources(struct device *dev) +{ + struct resource *res; + + printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev)); + usbdebug_disable(); + + if (ehci_drv_ops->set_resources) + ehci_drv_ops->set_resources(dev); + res = find_resource(dev, EHCI_BAR_INDEX); + if (!res) + return; + + usbdebug_re_enable((u32)res->base); + report_resource_stored(dev, res, ""); + printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev)); +} + +void pci_ehci_read_resources(struct device *dev) +{ + pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + + if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) { + memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops)); + ehci_drv_ops = dev->ops; + ehci_dbg_ops.set_resources = pci_ehci_set_resources; + dev->ops = &ehci_dbg_ops; + printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev)); + } else { + printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev)); + } + + pci_dev_read_resources(dev); +} +#endif + +unsigned long pci_ehci_base_regs(pci_devfn_t sdev) +{ +#ifdef __SIMPLE_DEVICE__ + unsigned long base = pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f; +#else + device_t dev = dev_find_slot(PCI_DEV2SEGBUS(sdev), PCI_DEV2DEVFN(sdev)); + unsigned long base = pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f; +#endif + return base + HC_LENGTH(read32(base)); +} + diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index dae4e68..d8b655a 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -181,6 +181,7 @@ #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ #define PCI_CAP_ID_PCIX 0x07 /* PCIX */ #define PCI_CAP_ID_HT 0x08 /* Hypertransport */ +#define PCI_CAP_ID_EHCI_DEBUG 0x0A /* EHCI debug port */ #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ #define PCI_CAP_ID_PCIE 0x10 /* PCI Express */ #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */

1 0

Patch set updated for coreboot: ef8fd89 util/board_status/board_status.sh: Only create a shallow clone
by Paul Menzel 09 Feb '14

09 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5173 -gerrit commit ef8fd890d2f613aeccffbd3e3bf95c5be9b1bb02 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 9 10:26:39 2014 +0100 util/board_status/board_status.sh: Only create a shallow clone Pass `--depth 1` to the command `git clone` when cloning the board-status repository as the history is not needed. This saves a little time and space. Change-Id: Ib998e4bf0abd2f348f54dbe0377a0c386248ba5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/board_status/board_status.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 3cff231..aa72b97 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -187,7 +187,7 @@ if [ $UPLOAD_RESULTS -eq 1 ]; then # FIXME: the board-status directory might get big over time. # Is there a way we can push the results without fetching the # whole repo? - git clone "ssh://${username}@review.coreboot.org:29418/board-status" + git clone --depth 1 "ssh://${username}@review.coreboot.org:29418/board-status" if [ $? -ne 0 ]; then "Error cloning board-status repo, aborting." exit $EXIT_FAILURE

1 0

New patch to review for coreboot: 1deeeaf NOTFORMERGE: lenovo/t60: Enable Infrared port.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5174 -gerrit commit 1deeeaf11228a9a9c9a1d88aff6cd2f08e3aff5d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 9 12:34:02 2014 +0100 NOTFORMERGE: lenovo/t60: Enable Infrared port. Change-Id: I4d49ee83c8135de503dcfb84b950f98c2a2306c9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/acpi/superio.asl | 16 ++++++++++++++++ src/mainboard/lenovo/t60/devicetree.cb | 3 +++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl index e69de29..a0d8e0a 100644 --- a/src/mainboard/lenovo/t60/acpi/superio.asl +++ b/src/mainboard/lenovo/t60/acpi/superio.asl @@ -0,0 +1,16 @@ + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..63e10dd 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -148,6 +148,9 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + irq 0xf0 = 0x82 end device pnp 164e.3 off # Serial Port

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New patch to review for coreboot: e365564 util/board_status/board_status.sh: Only create a shallow clone
by Paul Menzel 09 Feb '14

09 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5173 -gerrit commit e36556413a96e5f703e0f39005ea9e0c2337da35 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 9 10:26:39 2014 +0100 util/board_status/board_status.sh: Only create a shallow clone Pass `--depth 1` to the command `git clone` when cloning the board_status repository as the history is not needed. This saves a little time and space. Change-Id: Ib998e4bf0abd2f348f54dbe0377a0c386248ba5a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/board_status/board_status.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 3cff231..aa72b97 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -187,7 +187,7 @@ if [ $UPLOAD_RESULTS -eq 1 ]; then # FIXME: the board-status directory might get big over time. # Is there a way we can push the results without fetching the # whole repo? - git clone "ssh://${username}@review.coreboot.org:29418/board-status" + git clone --depth 1 "ssh://${username}@review.coreboot.org:29418/board-status" if [ $? -ne 0 ]; then "Error cloning board-status repo, aborting." exit $EXIT_FAILURE

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New patch to review for coreboot: d3f9801 util/board_status/board_status.sh: Only pass switch `-a` once to `git commit`
by Paul Menzel 09 Feb '14

09 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5172 -gerrit commit d3f98017d6833462dba1831dbc22e672cf8099fe Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 9 10:24:22 2014 +0100 util/board_status/board_status.sh: Only pass switch `-a` once to `git commit` Change-Id: Iabcb26229401b03ad4ba2df0f78eee08f379aa03 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/board_status/board_status.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 735932b..3cff231 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -202,7 +202,7 @@ if [ $UPLOAD_RESULTS -eq 1 ]; then echo "Uploading results" git add "${vendor}" - git commit -a -am "${mainboard_dir}/${tagged_version}/${timestamp}" + git commit -a -m "${mainboard_dir}/${tagged_version}/${timestamp}" git push origin # Results have been uploaded so it's pointless to keep the

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New patch to review for coreboot: 9ddfe00 util/board_status/board_status.sh: Make script executable
by Paul Menzel 09 Feb '14

09 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5171 -gerrit commit 9ddfe001bda7d68198696bb22602bb866a80ec05 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 9 10:20:02 2014 +0100 util/board_status/board_status.sh: Make script executable Simply calling the script does not work if it is not executable. $ LANG=C util/board_status/board_status.sh bash: util/board_status/board_status.sh: Permission denied Change-Id: I58f6d356bf1625ee205a536ee95c08294891b123 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/board_status/board_status.sh | 0 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh old mode 100644 new mode 100755

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Patch set updated for coreboot: 34d4f25 NOTFORMERGE: lenovo/x60: Enable Infrared port.
by Vladimir Serbinenko 09 Feb '14

09 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5170 -gerrit commit 34d4f25eb9219ff49abc7dab2ccac82671e151b0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 9 02:17:26 2014 +0100 NOTFORMERGE: lenovo/x60: Enable Infrared port. Change-Id: I251031086dd5ac012e3dc2e8fed816a8ca629f15 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x60/acpi/superio.asl | 17 +++++++++++++++++ src/mainboard/lenovo/x60/devicetree.cb | 3 +++ 2 files changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl index 31ffb7b..073d23b 100644 --- a/src/mainboard/lenovo/x60/acpi/superio.asl +++ b/src/mainboard/lenovo/x60/acpi/superio.asl @@ -1,3 +1,20 @@ + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + #if IS_ENABLED(CONFIG_BOARD_LENOVO_X60T) Device (DTR) // Digitizer { diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 5b4e37f..2388917 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -125,6 +125,9 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + irq 0xf0 = 0x82 end device pnp 164e.3 on # Digitizer

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Patch set updated for coreboot: f3c6aeb jetway/nf81-t56n-lf: Serialize ACPI methods to avoid races.
by Edward O'Callaghan 09 Feb '14

09 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5079 -gerrit commit f3c6aebecd1317a410d90af7de2ce5fe79ab4e54 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jan 29 15:29:44 2014 +1100 jetway/nf81-t56n-lf: Serialize ACPI methods to avoid races. Fix the remark introduced in ACPICA version 20130517 that gives the following explanation: If a thread blocks within the method for any reason, and another thread enters the method, the method will fail because an attempt will be made to create the same (named) object twice. In this case, issue a remark that the method should be marked serialized. ACPICA BZ 909. Change-Id: I2b3605a31a8647c07be0830e54cd117d53985c81 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl index b3aed9c..4071f85 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi/ide.asl @@ -77,7 +77,7 @@ Method(GTTM, 1) /* get total time*/ Device(PRID) { Name (_ADR, Zero) - Method(_GTM, 0) + Method(_GTM, 0, Serialized) { NAME(OTBF, Buffer(20) { /* out buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -122,7 +122,7 @@ Device(PRID) Return(OTBF) /* out buffer */ } /* End Method(_GTM) */ - Method(_STM, 3, NotSerialized) + Method(_STM, 3, Serialized) { NAME(INBF, Buffer(20) { /* in buffer */ 0xFF, 0xFF, 0xFF, 0xFF, @@ -173,7 +173,7 @@ Device(PRID) Device(MST) { Name(_ADR, 0) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, @@ -209,7 +209,7 @@ Device(PRID) Device(SLAV) { Name(_ADR, 1) - Method(_GTF) { + Method(_GTF, 0, Serialized) { Name(CMBF, Buffer(21) { 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF,

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coreboot-gerrit February 2014