coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 46c33f5 cpu: Only ask for length and address of ucode when included in CBFS
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4481 -gerrit commit 46c33f58d9f52ea6c40635dcff51a3473c15577f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Dec 4 22:05:15 2013 -0600 cpu: Only ask for length and address of ucode when included in CBFS The original intention was to only run prompt for CPU_MICROCODE_CBFS_LOC and CPU_MICROCODE_CBFS_LEN when a microcode file was included in CBFS. This happens when either CPU_MICROCODE_CBFS_GENERATE or CPU_MICROCODE_CBFS_EXTERNAL is selected, however, Kconfig checked that against CPU_MICROCODE_IN_CBFS. The end result was that length and location were always prompted, even when the user elected not to include any microcode. Instead, check if microcode is added to CBFS during the build. Change-Id: I9b61d022bcc879549e844bdfd5d5109554cc1a16 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index f3883d3..a300549 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -173,12 +173,12 @@ config CPU_MICROCODE_FILE config CPU_MICROCODE_CBFS_LOC hex "Microcode address in CBFS" - depends on CPU_MICROCODE_IN_CBFS + depends on CPU_MICROCODE_ADDED_DURING_BUILD default 0 config CPU_MICROCODE_CBFS_LEN hex "Microcode length in CBFS" - depends on CPU_MICROCODE_IN_CBFS + depends on CPU_MICROCODE_ADDED_DURING_BUILD default 0xC000 help The microcode needs a specific length to get correctly

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Patch set updated for coreboot: 195c9d5 RFC: console: Make 8250 memmaped console independent of Oxford PCIe952
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4587 -gerrit commit 195c9d57dc1b1f0049357b1087e1a7735a3800ff Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 19:33:06 2013 -0500 RFC: console: Make 8250 memmaped console independent of Oxford PCIe952 RFC: Request for comments. DO NOT MERGE (YET) Running the console on an 8250-compatible memory-mapped UART was only possible via an Oxford PCIe952 adapter, as the console code explicitly depended on variables and functions defined by the Oxford driver. Change-Id: Icde4cdb2d671865502293183aed5664e8690a9ac Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 5 +-- src/console/console.c | 6 +-- src/drivers/oxford/oxpcie/Makefile.inc | 1 + src/drivers/oxford/oxpcie/oxpcie_early.c | 13 ++++-- src/drivers/oxford/oxpcie/oxpcie_memconsole.c | 62 +++++++++++++++++++++++++++ src/include/uart8250.h | 9 ++-- src/lib/uart8250mem.c | 53 +---------------------- 7 files changed, 81 insertions(+), 68 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0eb3dc2..e9867a7 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -41,10 +41,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart8250_mem_tx_byte(uart8250_mem_get_baseaddr(), byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); diff --git a/src/console/console.c b/src/console/console.c index a31e293..93c5f88 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -106,11 +106,11 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_CONSOLE_SERIAL +#if CONFIG_CONSOLE_SERIAL && !CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif -#if CONFIG_DRIVERS_OXFORD_OXPCIE && CONFIG_CONSOLE_SERIAL8250MEM - oxford_init(); +#if CONFIG_CONSOLE_SERIAL8250MEM + uart_mem_init(); #endif #if CONFIG_CONSOLE_NE2K ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 6cc29c4..b967e02 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -2,4 +2,5 @@ ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_memconsole.c endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4..ed6a7ff 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -38,7 +38,12 @@ #if defined(__PRE_RAM__) int oxford_oxpcie_present CAR_GLOBAL; -void oxford_init(void) +u32 uart8250_mem_get_baseaddr(void) +{ + return CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +} + +u32 uart_mem_init(void) { u16 reg16; oxford_oxpcie_present = 1; @@ -92,7 +97,7 @@ void oxford_init(void) */ id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; + return -1; device = OXPCIE_DEVICE_3; break; case 0xc1581415: /* e.g. Startech MPEX2S952 */ @@ -101,7 +106,7 @@ void oxford_init(void) default: /* No UART here. */ oxford_oxpcie_present = 0; - return; + return -1; } /* Setup base address on device */ @@ -117,6 +122,8 @@ void oxford_init(void) u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + + return uart0_base; } #endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_memconsole.c b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c new file mode 100644 index 0000000..d1d0ce4 --- /dev/null +++ b/src/drivers/oxford/oxpcie/oxpcie_memconsole.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Subject to the GNU GPL version 2. + */ + +#include <uart8250.h> +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#include "option_table.h" +#endif + +u32 uart_mem_init(void) +{ + unsigned uart_baud = CONFIG_TTYS0_BAUD; + u32 uart_bar = 0; + unsigned div; + + /* find out the correct baud rate */ +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) && CONFIG_USE_OPTION_TABLE + b_index = read_option(baud_rate, 0); + b_index &= 7; + uart_baud = baud[b_index]; +#else + if (get_option(&b_index, "baud_rate") == CB_SUCCESS) + uart_baud = baud[b_index]; +#endif +#endif + + /* Now find the UART base address and calculate the divisor */ + +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) + device_t dev = dev_find_device(0x1415, 0xc158, NULL); + if (!dev) + dev = dev_find_device(0x1415, 0xc11b, NULL); + + if (dev) { + struct resource *res = find_resource(dev, 0x10); + + if (res) { + uart_bar = res->base + 0x1000; // for 1st UART + // uart_bar = res->base + 0x2000; // for 2nd UART + } + } + + if (!uart_bar) +#endif + uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART + // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART + + div = 4000000 / uart_baud; + + if (uart_bar) + uart8250_mem_init(uart_bar, div); + + return uart_bar; +} diff --git a/src/include/uart8250.h b/src/include/uart8250.h index a3868c5..493e32a 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,6 +20,8 @@ #ifndef UART8250_H #define UART8250_H +#include <types.h> + /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -130,13 +132,8 @@ void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); void uart8250_mem_tx_flush(unsigned base_port); void uart8250_mem_init(unsigned base_port, unsigned divisor); u32 uart_mem_init(void); +u32 uart8250_mem_get_baseaddr(void); -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; - -void oxford_init(void); -#endif #endif #endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..39dec37 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,8 +20,8 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> #if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> #include "option_table.h" #endif #include <device/device.h> @@ -102,54 +102,3 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) /* Set to 3 for 8N1 */ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } - -u32 uart_mem_init(void) -{ - unsigned uart_baud = CONFIG_TTYS0_BAUD; - u32 uart_bar = 0; - unsigned div; - - /* find out the correct baud rate */ -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - uart_baud = baud[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - uart_baud = baud[b_index]; -#endif -#endif - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE - -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - - if (dev) { - struct resource *res = find_resource(dev, 0x10); - - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } - - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART - - div = 4000000 / uart_baud; -#endif - - if (uart_bar) - uart8250_mem_init(uart_bar, div); - - return uart_bar; -}

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Patch set updated for coreboot: c2a3fe0 uart8250_mem_console.c: Remove inclusion of mc146818rtc.h
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4586 -gerrit commit c2a3fe053a411cbc5851488bff474ef1cffeb8c7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:27:56 2013 -0500 uart8250_mem_console.c: Remove inclusion of mc146818rtc.h The RTC functionality ptovided by the include is specific to x86, but is not used for this type of console. Change-Id: I82d0dfdb6e8b67bc81291a7a5d63ced91e095772 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/console/uart8250mem_console.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0;

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Patch set updated for coreboot: 0b46e8d uart8250.h: Do not guard entire include file by config options
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4585 -gerrit commit 0b46e8d9e6e3816081057bba17ebb5cbe46ad223 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Dec 29 18:13:58 2013 -0500 uart8250.h: Do not guard entire include file by config options Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/include/uart8250.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/include/uart8250.h b/src/include/uart8250.h index bec3637..a3868c5 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,8 +20,6 @@ #ifndef UART8250_H #define UART8250_H -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -141,6 +139,4 @@ void oxford_init(void); #endif #endif -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - #endif /* UART8250_H */

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Patch merged into coreboot/master: de15d39 hp/dl145_g1: Adding ACPI support
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit de15d39d6936669b2f0b1c77fde29c8475845571 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Sat Feb 8 00:17:21 2014 +0100 hp/dl145_g1: Adding ACPI support Basic ACPI support for this old platform. Created by copying and tweaking similar motherboard ACPI implementations in coreboot. Works reasonably well under Linux, providing HPET-timers and more under linux (tested under OpenSUSE 12.2 kernel 3.4.63-2.44). Not tested under Windows. Change-Id: I69431be962a0d272db398ecf4ac9f0249de8ebab Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> See http://review.coreboot.org/5185 for details. -gerrit

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Patch set updated for coreboot: 9ba6867 board_status.sh: allow user to supply console log
by David Hendricks 10 Feb '14

10 Feb '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5191 -gerrit commit 9ba6867e97b6ec7a0ad8dd0c019c928bd2950a6b Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 10 14:40:34 2014 -0800 board_status.sh: allow user to supply console log This adds an option to allow the user to supply a console log, for example if serial console logs provide additional pre-RAM messages that are useful. Change-Id: I3c8e496c90e56868196e95f5326c76cd524ad775 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/board_status/board_status.sh | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 735932b..8e9ec16 100644 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -10,6 +10,7 @@ EXIT_FAILURE=1 # Stuff from command-line switches REMOTE_HOST="" +CONSOLE_LOG="" CLOBBER_OUTPUT=0 UPLOAD_RESULTS=0 @@ -103,6 +104,9 @@ show_help() { Options -h Show this message. + -c <filename> + Use <filename> as console log instead of content from cbmem. Useful if + target does not support CBMEM or if serial log captures more messages. -C Clobber temporary output when finished. Useful for debugging. -r <host> @@ -118,6 +122,9 @@ while getopts "Chr:u" opt; do show_help exit $EXIT_SUCCESS ;; + c) + CONSOLE_LOG="$OPTARG" + ;; C) CLOBBER_OUTPUT=1 ;; @@ -169,7 +176,12 @@ printf "Upstream URL: %s\n" $($getrevision -U)>> ${tmpdir}/${results}/revision.t printf "Timestamp: %s\n" "$timestamp" >> ${tmpdir}/${results}/revision.txt test_cmd $REMOTE "cbmem" -cmd $REMOTE "cbmem -c" "${tmpdir}/${results}/coreboot_console.txt" +if [ -f "$CONSOLE_LOG" ]; then + cp "$CONSOLE_LOG" "${tmpdir}/${results}/coreboot_console.txt" + chmod 644 "${tmpdir}/${results}/coreboot_console.txt" +else + cmd $REMOTE "cbmem -c" "${tmpdir}/${results}/coreboot_console.txt" +fi cmd_nonfatal $REMOTE "cbmem -t" "${tmpdir}/${results}/coreboot_timestamps.txt" cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt"

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New patch to review for coreboot: e64fa8a board_status.sh: allow user to supply console log
by David Hendricks 10 Feb '14

10 Feb '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5191 -gerrit commit e64fa8ae461283a9ab0b182b3ff9a876bfb0ac6f Author: David Hendricks <dhendrix(a)chromium.org> Date: Mon Feb 10 14:40:34 2014 -0800 board_status.sh: allow user to supply console log This adds an option to allow the user to supply a console log, for example if serial console logs provide additional pre-RAM messages that are useful. Change-Id: I3c8e496c90e56868196e95f5326c76cd524ad775 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/board_status/board_status.sh | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 735932b..d649e11 100644 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -10,6 +10,7 @@ EXIT_FAILURE=1 # Stuff from command-line switches REMOTE_HOST="" +CONSOLE_LOG="" CLOBBER_OUTPUT=0 UPLOAD_RESULTS=0 @@ -103,6 +104,9 @@ show_help() { Options -h Show this message. + -c <filename> + Use <filename> as console log instead of content from cbmem. Useful if + target does not support CBMEM. -C Clobber temporary output when finished. Useful for debugging. -r <host> @@ -118,6 +122,9 @@ while getopts "Chr:u" opt; do show_help exit $EXIT_SUCCESS ;; + c) + CONSOLE_LOG="$OPTARG" + ;; C) CLOBBER_OUTPUT=1 ;; @@ -169,7 +176,11 @@ printf "Upstream URL: %s\n" $($getrevision -U)>> ${tmpdir}/${results}/revision.t printf "Timestamp: %s\n" "$timestamp" >> ${tmpdir}/${results}/revision.txt test_cmd $REMOTE "cbmem" -cmd $REMOTE "cbmem -c" "${tmpdir}/${results}/coreboot_console.txt" +if [ -f "$CONSOLE_LOG" ]; then + cp "$CONSOLE_LOG" "${tmpdir}/${results}/coreboot_console.txt" +else + cmd $REMOTE "cbmem -c" "${tmpdir}/${results}/coreboot_console.txt" +fi cmd_nonfatal $REMOTE "cbmem -t" "${tmpdir}/${results}/coreboot_timestamps.txt" cmd $REMOTE dmesg "${tmpdir}/${results}/kernel_log.txt"

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Patch set updated for coreboot: f58aafd drivers/i2c/at24rf08c: Indent files
by Ronald G. Minnich 10 Feb '14

10 Feb '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5094 -gerrit commit f58aafdbda5f6d91123a1a8456fe0fedfc6175b0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 2 12:27:12 2014 +0100 drivers/i2c/at24rf08c: Indent files Change-Id: I0969396aa9230acf6319f62190d8bf303eb97567 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/i2c/at24rf08c/at24rf08c.c | 11 +++++------ src/drivers/i2c/at24rf08c/lenovo_serials.c | 25 ++++++++++++------------- 2 files changed, 17 insertions(+), 19 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/at24rf08c.c b/src/drivers/i2c/at24rf08c/at24rf08c.c index a9cf2c5..4c97e60 100644 --- a/src/drivers/i2c/at24rf08c/at24rf08c.c +++ b/src/drivers/i2c/at24rf08c/at24rf08c.c @@ -32,15 +32,14 @@ static void at24rf08c_init(device_t dev) if (!dev->enabled) return; - /* Ensure that EEPROM/RFID chip is not accessible through RFID. + /* Ensure that EEPROM/RFID chip is not accessible through RFID. Need to do it only on 5c. */ if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c) return; - printk (BIOS_DEBUG, "Locking EEPROM RFID\n"); + printk(BIOS_DEBUG, "Locking EEPROM RFID\n"); - for (i = 0; i < 8; i++) - { + for (i = 0; i < 8; i++) { /* After a register write AT24RF08C sometimes stops responding. Retry several times in case of failure. */ @@ -49,7 +48,7 @@ static void at24rf08c_init(device_t dev) break; } - printk (BIOS_DEBUG, "init EEPROM done\n"); + printk(BIOS_DEBUG, "init EEPROM done\n"); } static void at24rf08c_noop(device_t dummy) @@ -70,5 +69,5 @@ static void enable_dev(device_t dev) struct chip_operations drivers_i2c_at24rf08c_ops = { CHIP_NAME("AT24RF08C") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 8c63d7d..a097b2a 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -33,7 +33,7 @@ static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) dev = dev_find_slot_on_smbus(1, 0x54 | bank); if (dev == 0) { printk(BIOS_WARNING, "EEPROM not found\n"); - memcpy(result, "*INVALID*", sizeof ("*INVALID*")); + memcpy(result, "*INVALID*", sizeof("*INVALID*")); return; } @@ -42,14 +42,14 @@ static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) int j; /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding. Retry several times in case of failure. - */ + */ for (j = 0; j < 100; j++) { t = smbus_read_byte(dev, start + i); if (t >= 0) break; } if (t < 0x20 || t > 0x7f) { - memcpy(result, "*INVALID*", sizeof ("*INVALID*")); + memcpy(result, "*INVALID*", sizeof("*INVALID*")); return; } result[i] = t; @@ -64,7 +64,7 @@ const char *smbios_mainboard_serial_number(void) if (already_read) return result; - memset(result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x2e, 7, result); already_read = 1; @@ -79,14 +79,14 @@ const char *smbios_mainboard_product_name(void) if (already_read) return result; - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); at24rf08c_read_string(0, 0x27, 7, result); already_read = 1; return result; } -void smbios_mainboard_set_uuid(u8 *uuid) +void smbios_mainboard_set_uuid(u8 * uuid) { static char result[16]; unsigned i; @@ -97,19 +97,18 @@ void smbios_mainboard_set_uuid(u8 *uuid) 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 }; - if (already_read) { - memcpy (uuid, result, 16); + memcpy(uuid, result, 16); return; } - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); dev = dev_find_slot_on_smbus(1, 0x56); if (dev == 0) { printk(BIOS_WARNING, "eeprom not found\n"); already_read = 1; - memset (uuid, 0, 16); + memset(uuid, 0, 16); return; } @@ -118,14 +117,14 @@ void smbios_mainboard_set_uuid(u8 *uuid) int j; /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding. Retry several times in case of failure. - */ + */ for (j = 0; j < 100; j++) { t = smbus_read_byte(dev, 0x12 + i); if (t >= 0) break; } if (t < 0) { - memset (result, 0, sizeof (result)); + memset(result, 0, sizeof(result)); break; } result[remap[i]] = t; @@ -133,5 +132,5 @@ void smbios_mainboard_set_uuid(u8 *uuid) already_read = 1; - memcpy (uuid, result, 16); + memcpy(uuid, result, 16); }

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Patch set updated for coreboot: 482d2bb arch/x86/boot/tables.c: Remove unused variable assignment to `rom_table_end`
by Ronald G. Minnich 10 Feb '14

10 Feb '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5106 -gerrit commit 482d2bbb38dc7529ac6c7f255c5ca83a95d552cd Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 3 08:36:51 2014 +0100 arch/x86/boot/tables.c: Remove unused variable assignment to `rom_table_end` Change-Id: I098d1238cda16060c3566f242443007cdaf9bd82 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/boot/tables.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index e980ed8..23b17f9 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -237,8 +237,7 @@ struct lb_memory *write_tables(void) new_high_table_pointer - high_table_pointer); } else { /* The coreboot table must be in 0-4K or 960K-1M */ - rom_table_end = write_coreboot_table( - low_table_start, low_table_end, + write_coreboot_table(low_table_start, low_table_end, rom_table_start, rom_table_end); }

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Patch set updated for coreboot: a9b488d util/board_status: Only pass switch `-a` once to `git commit`
by Paul Menzel 10 Feb '14

10 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5172 -gerrit commit a9b488d49b4c1ca8fdb25aed287bded8f9160037 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 9 10:24:22 2014 +0100 util/board_status: Only pass switch `-a` once to `git commit` Change-Id: Iabcb26229401b03ad4ba2df0f78eee08f379aa03 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/board_status/board_status.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 735932b..3cff231 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -202,7 +202,7 @@ if [ $UPLOAD_RESULTS -eq 1 ]; then echo "Uploading results" git add "${vendor}" - git commit -a -am "${mainboard_dir}/${tagged_version}/${timestamp}" + git commit -a -m "${mainboard_dir}/${tagged_version}/${timestamp}" git push origin # Results have been uploaded so it's pointless to keep the

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coreboot-gerrit February 2014