coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a56ac31 baytrail: bring up APs
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4889 -gerrit commit a56ac3116777957e9f4f0d8d3f19f62e50b376d4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 21 12:36:17 2013 -0500 baytrail: bring up APs Bring up the APs using x86 MP infrastructure. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi. Noted all cores are brought up. Change-Id: I9231eff5494444e8eb17ecdc5a0af72a2e5208b5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173704 --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.c | 7 +-- src/soc/intel/baytrail/cpu.c | 82 ++++++++++++++++++++++++++++++ 5 files changed, 86 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 33c0d56..fbfe153 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES + select PARALLEL_MP select SMM_MODULES select SMM_TSEG select SMP diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 9695a70..686b4ac 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -22,6 +22,7 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += reset.c ramstage-y += reset.c +ramstage-y += cpu.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index ff0397c..790b8c6 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -25,6 +25,7 @@ /* The baytrail_init_pre_device() function is called prior to device * initialization, but it's after console and cbmem has been reinitialized. */ void baytrail_init_pre_device(void); +void baytrail_init_cpus(device_t dev); void set_max_freq(void); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 5a898f6..0f686fa 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -40,18 +40,13 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; -static void cpu_bus_init(device_t dev) -{ - printk(BIOS_DEBUG, "cpu_bus_init()\n"); -} - static void cpu_bus_noop(device_t dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, - .init = cpu_bus_init, + .init = baytrail_init_cpus, .scan_bus = NULL, }; diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c new file mode 100644 index 0000000..4217947 --- /dev/null +++ b/src/soc/intel/baytrail/cpu.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/mp.h> + +#include <baytrail/pattrs.h> +#include <baytrail/ramstage.h> + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), +}; + +/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +static int adjust_apic_id(int index, int apic_id) +{ + return 2 * index; +} + +void baytrail_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + const struct pattrs *pattrs = pattrs_get(); + struct mp_params mp_params; + + /* Set up MTRRs based on physical address size. */ + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_mtrr_check(); + + mp_params.num_cpus = pattrs->num_cpus, + mp_params.parallel_microcode_load = 1, + mp_params.adjust_apic_id = adjust_apic_id; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = intel_microcode_find(); + mp_params.microcode_pointer = NULL; + + if (mp_init(cpu_bus, &mp_params)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } +} + +static void baytrail_core_init(device_t cpu) +{ + printk(BIOS_DEBUG, "Init BayTrail core.\n"); +} + +static struct device_operations cpu_dev_ops = { + .init = baytrail_core_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x30673 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; +

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Patch set updated for coreboot: 17acddd baytrail: allow downstream use of SSE instructions
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4881 -gerrit commit 17acddd9904af8a203d9b87a14199fe4e4f9620b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 12:47:47 2013 -0500 baytrail: allow downstream use of SSE instructions If a payload is compiled to use SSE instructions it will fault with an undefined opcode because SSE instructions weren't enabled. Therefore enable SSE instructions at runtime. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted with SSE enabled payload. No exceptions seen. Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172642 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> --- src/soc/intel/baytrail/ramstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 10c030f..229e367 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -20,6 +20,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/microcode.h> +#include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci_def.h> @@ -109,6 +110,9 @@ void baytrail_init_pre_device(void) fill_in_pattrs(); + /* Allow for SSE instructions to be executed. */ + write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config);

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Patch set updated for coreboot: dd80fb4 baytrail: add vboot ramstage verification
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4880 -gerrit commit dd80fb484b596c673cdac69d59ac87a50f3e2792 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 21:03:50 2013 -0500 baytrail: add vboot ramstage verification Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/romstage/romstage.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 293ed21..33c0d56 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,6 +9,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4228615..3ae52cf 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -25,12 +25,16 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <ramstage_cache.h> +#include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h> static inline uint64_t timestamp_get(void) @@ -169,6 +173,9 @@ void asmlinkage romstage_after_car(void) timestamp_add_now(TS_END_ROMSTAGE); + /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + /* Load the ramstage. */ copy_and_run(); while (1); @@ -270,3 +277,25 @@ static void *setup_stack_and_mttrs(void) return slot; } + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = (1 << 20); + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; +} + +void ramstage_cache_invalid(struct ramstage_cache *cache) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} +

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Patch set updated for coreboot: 33d0e01 baytrail: fix tsc rate
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4883 -gerrit commit 33d0e01986f21bc65f6089ae2d0ae4898b8fc450 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 00:44:06 2013 -0500 baytrail: fix tsc rate Despite some references to a fixed bclk in some of the docs the bclk is variable per sku. Therefore, perform the calculation according to the BSEL_CR_OVERCLOCK_CONTROL msr which provides the bclk for the cpu cores in Bay Trail. BUG=chrome-os-partner:23166 BRANCH=None TEST=Built and booted B3. correctly says: clocks_per_usec: 2133 Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172771 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/msr.h | 1 + src/soc/intel/baytrail/tsc_freq.c | 13 ++++++++++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index 7f3b3b2..5094f96 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -21,6 +21,7 @@ #define _BAYTRAIL_MSR_H_ #define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 0cf7273..3b662fe 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -27,14 +27,21 @@ #include <baytrail/romstage.h> #endif - -#define BCLK 100 /* 100 MHz */ unsigned long tsc_freq_mhz(void) { msr_t platform_info; + msr_t clk_info; + unsigned long bclk_khz; platform_info = rdmsr(MSR_PLATFORM_INFO); - return BCLK * ((platform_info.lo >> 8) & 0xff); + clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); + switch (clk_info.lo & 0x3) { + case 0: bclk_khz = 83333; break; + case 1: bclk_khz = 100000; break; + case 2: bclk_khz = 133333; break; + case 3: bclk_khz = 116666; break; + } + return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } void set_max_freq(void)

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Patch set updated for coreboot: 5a67eaa baytrail: print dram configuration
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4882 -gerrit commit 5a67eaa927db1c6038e7108ee27b96ca9781a86d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 00:26:04 2013 -0500 baytrail: print dram configuration After running the MRC blob print out some information on the training: MRC version, number channels, DDR3 type, and DRAM frequency. Example output: MRC v0.90 2 channels of DDR3 @ 1066MHz Apparently there are two dunit IOSF ports -- 1 for each channel. However, certain registers really on live in channel 0. Thus, there was some changes to dunit support in the iosf area. BUG=chrome-os-partner:22875 BRANCH=None TEST=Built and booted bayleybay in different configs. Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172770 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 15 ++++++++--- src/soc/intel/baytrail/iosf.c | 15 +++++++++++ src/soc/intel/baytrail/romstage/raminit.c | 45 +++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index cf7e559..497124e 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -58,16 +58,21 @@ uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); uint32_t iosf_dunit_read(int reg); void iosf_dunit_write(int reg, uint32_t val); +/* Some registers are per channel while the gloals live in dunit 0 */ +uint32_t iosf_dunit_ch0_read(int reg); +uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ #define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ +#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memroy Arbiter/Bunit */ #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ #define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ +#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ @@ -120,10 +125,12 @@ void iosf_punit_write(int reg, uint32_t val); */ #define DRP 0x00 -# define DRP_CH0_RANK0_EN (0x01 << 0) -# define DRP_CH0_RANK1_EN (0x01 << 1) -# define DRP_CH1_RANK0_EN (0x01 << 2) -# define DRP_CH1_RANK1_EN (0x01 << 3) +# define DRP_DIMM0_RANK0_EN (0x01 << 0) +# define DRP_DIMM0_RANK1_EN (0x01 << 1) +# define DRP_DIMM1_RANK0_EN (0x01 << 2) +# define DRP_DIMM1_RANK1_EN (0x01 << 3) +# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ + DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) #define DTR0 0x01 # define DTR0_SPEED_MASK 0x03 # define DTR0_SPEED_800 0x00 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 00a3269..e35e34f 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -70,6 +70,21 @@ uint32_t iosf_dunit_read(int reg) return read_iosf_reg(MDR_REG); } +uint32_t iosf_dunit_ch0_read(int reg) +{ + return iosf_dunit_read(reg); +} + +uint32_t iosf_dunit_ch1_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + void iosf_dunit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index cf9ccfd..7bcd54f 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -26,6 +26,7 @@ #include <baytrail/gpio.h> #include <baytrail/mrc_cache.h> #include <baytrail/iomap.h> +#include <baytrail/iosf.h> #include <baytrail/pci_devs.h> #include <baytrail/romstage.h> @@ -57,6 +58,48 @@ static void ABI_X86 send_to_console(unsigned char b) console_tx_byte(b); } +static void print_dram_info(void) +{ + const int mrc_ver_reg = 0xf0; + const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); + uint32_t reg; + int num_channels; + int speed; + uint32_t ch0; + uint32_t ch1; + + reg = pci_read_config32(soc_dev, mrc_ver_reg); + + printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); + + /* Number of channels enabled and DDR3 type. Determine number of + * channels by keying of the rank enable bits [3:0]. * */ + ch0 = iosf_dunit_ch0_read(DRP); + ch1 = iosf_dunit_ch1_read(DRP); + num_channels = 0; + if (ch0 & DRP_RANK_MASK) + num_channels++; + if (ch1 & DRP_RANK_MASK) + num_channels++; + + printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, + (reg & (1 << 22)) ? "LP" : ""); + + /* DRAM frequency -- all channels run at same frequency. */ + reg = iosf_dunit_read(DTR0); + switch (reg & 0x3) { + case 0: + speed = 800; break; + case 1: + speed = 1066; break; + case 2: + speed = 1333; break; + case 3: + speed = 1600; break; + } + printk(BIOS_INFO, "%dMHz\n", speed); +} + void raminit(struct mrc_params *mp, int prev_sleep_state) { int ret; @@ -87,6 +130,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) ret = mrc_entry(mp); + print_dram_info(); + cbmem_initialize_empty(); printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);

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Patch set updated for coreboot: ae5eb13 rambi: disable internal pullups on ram_id[2:0]
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4885 -gerrit commit ae5eb131cd439505fe3a7c3299192dd005784caf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 16 09:21:55 2013 -0700 rambi: disable internal pullups on ram_id[2:0] The ram_id[2:0] signals have stuffing options for pull up/down with values of 10K. However, the default pulldown values for these pads are 20K. Therefore, one can't read a high value because of the high voltage threshold is 0.65 * Vref. Therefore the high signals are marginal at best. Fix this issue by disabling the internal pull for the pads connected to ram_id[2:0]. BUG=chrome-os-partner:23350 BRANCH=None TEST=Built and checked that ram_id[2:0] is properly read now. Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173211 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> --- src/mainboard/google/rambi/romstage.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index d15a21d..369ebad 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -37,14 +37,29 @@ #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 +static inline void disable_internal_pull(int pad) +{ + const int pull_mask = ~(0xf << 7); + write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); +} + static void *get_spd_pointer(char *spd_file_content, int total_spds) { int ram_id = 0; + /* The ram_id[2:0] pullups on rambi are too large for the default 20K + * pulldown on the pad. Therefore, disable the internal pull resistor to + * read high values correctly. */ + disable_internal_pull(GPIO_SSUS_37_PAD); + disable_internal_pull(GPIO_SSUS_38_PAD); + disable_internal_pull(GPIO_SSUS_39_PAD); + ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0); ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1); ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2); + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + if (ram_id >= total_spds) return NULL;

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Patch set updated for coreboot: 907d9c8 baytrail: correct MMC pci location
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4884 -gerrit commit 907d9c8980559a3ec2f691e4dfdf863f3391eb97 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 08:39:54 2013 -0500 baytrail: correct MMC pci location The original documentation was incorrect. Fix the pci device for the MMC port to reflect reality. MMC is at 00:17.0 with a device id of 0x0f50. BUG=None BRANCH=None TEST=Built. Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172772 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 46c6ea6..8b0335e 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -32,11 +32,6 @@ #define GFX_FUNC 0 # define GFX_DEVID 0x0f31 -/* MMC Port */ -#define MMC_DEV 16 -#define MMC_FUNC 0 -# define MMC_DEVID 0x0f14 - /* SDIO Port */ #define SDIO_DEV 17 #define SDIO_FUNC 0 @@ -63,6 +58,11 @@ #define LPE_FUNC 0 # define LPE_DEVID 0x0f28 +/* MMC Port */ +#define MMC_DEV 23 +#define MMC_FUNC 0 +# define MMC_DEVID 0x0f50 + /* Serial IO 1 */ #define SIO1_DEV 24 # define SIO_DMA1_DEV SIO1_DEV

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Patch set updated for coreboot: 9b167e1 rambi: add BSP lapic device
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4887 -gerrit commit 9b167e15c4da77e1824b17db4152be7a2ee3583d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 21 12:11:17 2013 -0500 rambi: add BSP lapic device There's some baked in assumptions internal to coreboot that the BSP's cpu device exists in the device tree. Therefore provide one in the device tree. BUG=chrome-os-partner:22862 BRANCH=None TEST=Compiled and booted with other changes. Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173702 --- src/mainboard/google/rambi/devicetree.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 376aab6..c6ea97c 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -1,5 +1,7 @@ chip soc/intel/baytrail - device cpu_cluster 0 on end + device cpu_cluster 0 on + device lapic 0 on end + end device domain 0 on device pci 00.0 on end # SoC router device pci 02.0 on end # GFX

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Patch set updated for coreboot: 637cff4 baytrail: Modify GPIO pull-up specification method
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4886 -gerrit commit 637cff4d1a80fc0a6f27607fd92fc518dfd61d4d Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Oct 18 17:13:18 2013 -0700 baytrail: Modify GPIO pull-up specification method Minor style changes to the way GPIO pull-ups are specified in board-specific GPIO maps. Intent is to allow calls to GPIO_FUNC macro from such maps. BUG=chrome-os-partner:22863 TEST=Manual. Build + boot on bayleybay. Change-Id: I80134b65d22d3ad8a049837dccc0985e321645da Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173748 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: David James <davidjames(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 49 +++++++++++++--------------------- 1 file changed, 18 insertions(+), 31 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index a180ba7..8d7925b 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -105,9 +105,9 @@ #define PAD_PU_40K (3 << 9) /* config0[8:7] - Pull assign */ -#define PAD_PU_DISABLE (0 << 7) -#define PAD_PU_UP (1 << 7) -#define PAD_PU_DOWN (2 << 7) +#define PAD_PULL_DISABLE (0 << 7) +#define PAD_PULL_UP (1 << 7) +#define PAD_PULL_DOWN (2 << 7) /* config0[2:0] - Func. pin mux */ #define PAD_FUNC0 0x0 @@ -146,7 +146,7 @@ * legacy config -- so also configure the pad regs as GPIO. We rely upon * the fact that all GPNCORE pads are function 0 GPIO. */ #define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_UP | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT_ENABLE, \ @@ -154,7 +154,7 @@ .io_sel = GPIO_DIR_INPUT } #define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_DOWN | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT_ENABLE, \ @@ -162,7 +162,7 @@ .io_sel = GPIO_DIR_INPUT } #define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_10K | PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT_ENABLE, \ @@ -170,7 +170,7 @@ .io_sel = GPIO_DIR_INPUT } #define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_LOW, \ @@ -179,7 +179,7 @@ .gp_lvl = GPIO_LEVEL_LOW } #define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PU_DISABLE | PAD_CONFIG0_DEFAULT \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_HIGH, \ @@ -188,34 +188,21 @@ .gp_lvl = GPIO_LEVEL_HIGH } /* Define no-pull / PU / PD configs for each functional config option */ -#define _GPIO_FUNC(_func, _pu, _str) \ +#define GPIO_FUNC(_func, _pudir, _str) \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC##_func | PAD_PU_##_pu | PAD_PU_##_str | \ + .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_DEFAULT } -#define GPIO_FUNC0 _GPIO_FUNC(0, DISABLE, 10K) -#define GPIO_FUNC0_PU_10K _GPIO_FUNC(0, UP, 10K) -#define GPIO_FUNC0_PD_10K _GPIO_FUNC(0, DOWN, 10K) -#define GPIO_FUNC1 _GPIO_FUNC(1, DISABLE, 10K) -#define GPIO_FUNC1_PU_10K _GPIO_FUNC(1, UP, 10K) -#define GPIO_FUNC1_PD_10K _GPIO_FUNC(1, DOWN, 10K) -#define GPIO_FUNC2 _GPIO_FUNC(2, DISABLE, 10K) -#define GPIO_FUNC2_PU_10K _GPIO_FUNC(2, UP, 10K) -#define GPIO_FUNC2_PD_10K _GPIO_FUNC(2, DOWN, 10K) -#define GPIO_FUNC3 _GPIO_FUNC(3, DISABLE, 10K) -#define GPIO_FUNC3_PU_10K _GPIO_FUNC(3, UP, 10K) -#define GPIO_FUNC3_PD_10K _GPIO_FUNC(3, DOWN, 10K) -#define GPIO_FUNC4 _GPIO_FUNC(4, DISABLE, 10K) -#define GPIO_FUNC4_PU_10K _GPIO_FUNC(4, UP, 10K) -#define GPIO_FUNC4_PD_10K _GPIO_FUNC(4, DOWN, 10K) -#define GPIO_FUNC5 _GPIO_FUNC(5, DISABLE, 10K) -#define GPIO_FUNC5_PU_10K _GPIO_FUNC(5, UP, 10K) -#define GPIO_FUNC5_PD_10K _GPIO_FUNC(5, DOWN, 10K) -#define GPIO_FUNC6 _GPIO_FUNC(6, DISABLE, 10K) -#define GPIO_FUNC6_PU_10K _GPIO_FUNC(6, UP, 10K) -#define GPIO_FUNC6_PD_10K _GPIO_FUNC(6, DOWN, 10K) +/* Default functional configs -- no PU */ +#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 10K) +#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 10K) +#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 10K) +#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 10K) +#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 10K) +#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 10K) +#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 10K) /* End marker */ #define GPIO_LIST_END 0xffffffff

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Patch set updated for coreboot: 2ee650f crossgcc: Update IASL to latest version (20140114)
by Alexandru Gagniuc 11 Feb '14

11 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5116 -gerrit commit 2ee650fb647c0cfad6db19cafdb62705d3035eb7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Feb 4 10:46:51 2014 -0600 crossgcc: Update IASL to latest version (20140114) Change-Id: I2450cad4a43907b8ca6d8f4d35932d7f451f71ea Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/crossgcc/buildgcc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 87054f2..c6d7183 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -20,8 +20,8 @@ # Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA # -CROSSGCC_DATE="September 20th, 2013" -CROSSGCC_VERSION="1.23" +CROSSGCC_DATE="February 10th, 2014" +CROSSGCC_VERSION="1.24" # default settings TARGETDIR=`pwd`/xgcc @@ -37,7 +37,7 @@ GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.23.2 GDB_VERSION=7.6 -IASL_VERSION=20130626 +IASL_VERSION=20140114 PYTHON_VERSION=3.3.2 EXPAT_VERSION=2.1.0

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coreboot-gerrit February 2014