coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch merged into coreboot/master: 058755b hp/dl145_g1: Add HAVE_HARD_RESET
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 058755b695ee2778cb9c7622d9ad1c8465f2e729 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:13:06 2014 +0100 hp/dl145_g1: Add HAVE_HARD_RESET This platform has a hard reset button Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> See http://review.coreboot.org/5097 for details. -gerrit

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Patch merged into coreboot/master: ee94d65 hp/dl145_g1: Adding FID/VID and Powernow ACPI
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit ee94d6533955d629fafac154032f3060386ea933 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:51:03 2014 +0100 hp/dl145_g1: Adding FID/VID and Powernow ACPI Add cool-n-quiet functionality which allows the OS to dynamic alter CPU voltage and frequency change in order to save power e.g. when the CPU load is low. Change-Id: I4c895a56bcf571d4276af192aeef87d120143063 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> See http://review.coreboot.org/5186 for details. -gerrit

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Patch set updated for coreboot: ee94d65 hp/dl145_g1: Adding FID/VID and Powernow ACPI
by Oskar Enoksson 11 Feb '14

11 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5186 -gerrit commit ee94d6533955d629fafac154032f3060386ea933 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:51:03 2014 +0100 hp/dl145_g1: Adding FID/VID and Powernow ACPI Add cool-n-quiet functionality which allows the OS to dynamic alter CPU voltage and frequency change in order to save power e.g. when the CPU load is low. Change-Id: I4c895a56bcf571d4276af192aeef87d120143063 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/mainboard/hp/dl145_g1/Kconfig | 2 ++ src/mainboard/hp/dl145_g1/acpi_tables.c | 5 +++++ src/mainboard/hp/dl145_g1/romstage.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 72f8d09..a169b88 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -13,6 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select SET_FIDVID + select SET_FIDVID_DEBUG select RAMINIT_SYSINFO # select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index dd96318..c94688e 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -21,6 +21,7 @@ #include <cpu/amd/amdk8_sysconf.h> #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" +#include <cpu/amd/model_fxx_powernow.h> #define DUMP_ACPI_TABLES 0 @@ -163,6 +164,10 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); +#if CONFIG_SET_FIDVID + amd_model_fxx_generate_powernow(pm_base + 0x10, 6, 1); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); +#endif return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 3cb6761..a5df58d 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -86,6 +86,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" +#if CONFIG_SET_FIDVID +#include "cpu/amd/model_fxx/fidvid.c" +#endif #define RC0 ((1<<1)<<8) #define RC1 ((1<<2)<<8) @@ -130,6 +133,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif ht_setup_chains_x(sysinfo); +#if CONFIG_SET_FIDVID + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + struct cpuid_result cpuid1 = cpuid(0x80000007); + if ((cpuid1.edx & 0x6) == 0x6) { + { + /* Read FIDVID_STATUS */ + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + // show final fid and vid + { + msr_t msr; + msr=rdmsr(0xc0010042); + print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + } + + } else { + print_debug("Changing FIDVID not supported\n"); + } +#endif needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); @@ -159,6 +189,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); +#if CONFIG_SET_FIDVID + init_timer(); // Need to use TMICT to synchronize FID/VID +#endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices();

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Patch set updated for coreboot: bdeedfe hp/dl145_g1: Fix some commented out code
by Oskar Enoksson 11 Feb '14

11 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5187 -gerrit commit bdeedfee46ba632dec112d8d11b9e87c27de7b23 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:15:18 2014 +0100 hp/dl145_g1: Fix some commented out code Some out-commented code contained variables which changed name. This commit fixes the "problem". Change-Id: I8d9168c9f4b2cb6810b3e4dfeff2155f3c08357d Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/mainboard/hp/dl145_g1/mptable.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 35dedde..725220e 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -53,26 +53,26 @@ static void *smp_write_config_table(void *v) // /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ // Integrated SMBus 2.0 - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15); // Integrated AMD AC97 Audio - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12); // Integrated AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13); // On board ATI Rage XL - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14); // On board Broadcom nics smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00); // On board LSI SCSI - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02); // PCIX-133 Slot smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03); + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04); /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa);

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Patch set updated for coreboot: 3a2e997 Eliminate more ASL warnings
by Oskar Enoksson 11 Feb '14

11 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5190 -gerrit commit 3a2e997fbbe226a211aee26e68388b1e06ee3393 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 23:20:14 2014 +0100 Eliminate more ASL warnings There were ASL compiler warnings about "Size mismatch". This commit eliminates the warnings by changing the ASL declarations of those fields. Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/superio/winbond/w83627hf/acpi/superio.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index a8a184a..41f3588 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -712,7 +712,7 @@ Device(SIO) { IRQNoFlags (IRQX) {} }) CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + CreateWordField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) @@ -1153,7 +1153,7 @@ Device(SIO) { }) CreateWordField (Arg0, IO0._MIN, IOA0) CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQX._INT, IRQL) + CreateWordField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) Divide(IOA1, 256, Local2, Local3) @@ -1235,7 +1235,7 @@ Device(SIO) { Name (TMPL, ResourceTemplate () { IRQNoFlags (IRQX) {} }) - CreateByteField (Arg0, IRQX._INT, IRQL) + CreateWordField (Arg0, IRQX._INT, IRQL) Subtract(FindSetLeftBit (IRQL), 1, Local0)

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Patch set updated for coreboot: 8a41a2e hp/dl145_g1: Add missing copyright notes
by Oskar Enoksson 11 Feb '14

11 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5188 -gerrit commit 8a41a2e28ff0f94fdc0fd20d3f1a483b78bb9138 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:19:35 2014 +0100 hp/dl145_g1: Add missing copyright notes Missing copyright notes added. Change-Id: I55b320a169b1125017c63b7a2384078465e7ce6e Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/mainboard/hp/dl145_g1/get_bus_conf.c | 4 ++++ src/mainboard/hp/dl145_g1/mb_sysconf.h | 4 ++++ src/mainboard/hp/dl145_g1/mptable.c | 4 ++++ src/mainboard/hp/dl145_g1/resourcemap.c | 5 ++++- src/mainboard/hp/dl145_g1/romstage.c | 4 ++++ 5 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c index 9ca5792..acfa023 100644 --- a/src/mainboard/hp/dl145_g1/get_bus_conf.c +++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/mainboard/hp/dl145_g1/mb_sysconf.h b/src/mainboard/hp/dl145_g1/mb_sysconf.h index 2b16791..9d373b3 100644 --- a/src/mainboard/hp/dl145_g1/mb_sysconf.h +++ b/src/mainboard/hp/dl145_g1/mb_sysconf.h @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #ifndef MB_SYSCONF_H #define MB_SYSCONF_H diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c index 725220e..b9af38b 100644 --- a/src/mainboard/hp/dl145_g1/mptable.c +++ b/src/mainboard/hp/dl145_g1/mptable.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <console/console.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c index 9a9fb10..4cc08f5 100644 --- a/src/mainboard/hp/dl145_g1/resourcemap.c +++ b/src/mainboard/hp/dl145_g1/resourcemap.c @@ -1,6 +1,9 @@ /* * DL145G1 needs a different resource map - * This file may need more tweaking, it is copied from the Tyan S2881 mainboard + * This file was originally copied from the tyan/s2881 coreboot mainboard. + * + * Copyright (c) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. */ static void setup_dl145g1_resource_map(void) diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 67ce9c1..3cb6761 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -1,3 +1,7 @@ +/* + * Copyright (c) 2011,2014 Oskar Enoksson <enok(a)lysator.liu.se> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ #include <stdint.h> #include <string.h> #include <device/pci_def.h>

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Patch set updated for coreboot: 714c10d Eliminate some ASL warnings
by Oskar Enoksson 11 Feb '14

11 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5189 -gerrit commit 714c10d58294ff8f628b62c959f2ad8d86f7eee7 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 23:19:02 2014 +0100 Eliminate some ASL warnings The ASL compiler warned about "Control Method should be made Serialized (due to creation of named objects within)". This commit eliminates the warnings by changing those NonSerialized into Serialized. Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/northbridge/amd/amdk8/util.asl | 6 +++--- src/superio/winbond/w83627hf/acpi/superio.asl | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdk8/util.asl b/src/northbridge/amd/amdk8/util.asl index 57a2cf9..921de4e 100644 --- a/src/northbridge/amd/amdk8/util.asl +++ b/src/northbridge/amd/amdk8/util.asl @@ -109,7 +109,7 @@ Scope (\_SB) } /* GetBusResources(Node, Link) */ - Method (GWBN, 2, NotSerialized) + Method (GWBN, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -149,7 +149,7 @@ Scope (\_SB) } /* GetMemoryResources(Node, Link) */ - Method (GMEM, 2, NotSerialized) + Method (GMEM, 2, Serialized) { Name (BUF0, ResourceTemplate () { @@ -214,7 +214,7 @@ Scope (\_SB) } /* GetIOResources(Node, Link) */ - Method (GIOR, 2, NotSerialized) + Method (GIOR, 2, Serialized) { Name (BUF0, ResourceTemplate () { diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 8531339..a8a184a 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -655,7 +655,7 @@ Device(SIO) { EXCM () } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IO (Decode16, 0x0000, 0x0000, 0x01, 0x08, IO0) @@ -1099,7 +1099,7 @@ Device(SIO) { Notify(PS2M, 1) } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IRQNoFlags (IRQX) {} @@ -1203,7 +1203,7 @@ Device(SIO) { EXCM () } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IRQNoFlags (IRQX) {} @@ -1425,7 +1425,7 @@ Device(SIO) { EXCM () } - Method (_CRS) + Method (_CRS, 0, Serialized) { Name (CRS, ResourceTemplate () { IO (Decode16, 0x0000, 0x0000, 0x08, 0x02, IO0)

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Patch set updated for coreboot: 058755b hp/dl145_g1: Add HAVE_HARD_RESET
by Oskar Enoksson 11 Feb '14

11 Feb '14

Oskar Enoksson (enok(a)lysator.liu.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5097 -gerrit commit 058755b695ee2778cb9c7622d9ad1c8465f2e729 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:13:06 2014 +0100 hp/dl145_g1: Add HAVE_HARD_RESET This platform has a hard reset button Change-Id: Ic4d2f9382b6770654eea8842a37ad38cf12de459 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/mainboard/hp/dl145_g1/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 94189ce..72f8d09 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 select SUPERIO_WINBOND_W83627HF + select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE

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Patch set updated for coreboot: bbdf01d x86: provide stage_exit() like arm
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5086 -gerrit commit bbdf01de632e76ef437fbc1dcd53c1048af95007 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 15:48:29 2014 -0600 x86: provide stage_exit() like arm The arm architectures have a stage_exit() function which takes a void * pointer as an entry point. Provide the same API for x86. This can make the booting paths less architecture-specific. Change-Id: I4ecfbf32f38f2e3817381b63e1f97e92654c5f97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/stages.h | 8 ++++++++ src/arch/x86/lib/cbfs_and_run.c | 5 +---- src/vendorcode/google/chromeos/vboot_loader.c | 7 ++----- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 8cbf5da..91d0db6 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -24,4 +24,12 @@ void asmlinkage copy_and_run(void); void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); + +static inline void stage_exit(void *entry) +{ + __asm__ volatile ( + "jmp *%%edi\n" + :: "D"(entry) + ); +} #endif diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 6379842..3d56e19 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -34,10 +34,7 @@ static void cbfs_and_run_core(const char *filename) timestamp_add_now(TS_END_COPYRAM); print_debug("Jumping to image.\n"); - __asm__ volatile ( - "jmp *%%edi\n" - :: "D"(dst) - ); + stage_exit(dst); } void asmlinkage copy_and_run(void) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index badff27..cc7c25d 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/stages.h> #include <stdint.h> #include <stddef.h> #include <cbfs.h> @@ -180,11 +181,7 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, timestamp_add_now(TS_END_COPYRAM); - __asm__ volatile ( - "movl $0, %%ebp\n" - "jmp *%%edi\n" - :: "D"(rmod_load.entry) - ); + stage_exit(rmod_load.entry); } void vboot_verify_firmware(struct romstage_handoff *handoff)

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Patch set updated for coreboot: b4ec448 coreboot: infrastructure for different ramstage loaders
by Aaron Durbin 11 Feb '14

11 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5087 -gerrit commit b4ec44839eb437ba6c6aac77785959e66a9b4ad1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 30 17:19:46 2014 -0600 coreboot: infrastructure for different ramstage loaders There are 2 methods currently available in coreboot to load ramstage from romstage: cbfs and vboot. The vboot path had to be explicitly enabled and code needed to be added to each chipset to support both. Additionally, many of the paths were duplicated between the two. An additional complication is the presence of having a relocatable ramstage which creates another path with duplication. To rectify this situation provide a common API through the use of a callback to load the ramstage. The rest of the existing logic to handle all the various cases is put in a common place. Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/lib/cbfs_and_run.c | 21 +----- src/cpu/intel/haswell/romstage.c | 2 - src/include/cbfs.h | 22 +++++- src/include/cbmem.h | 5 ++ src/include/ramstage_loader.h | 34 +++++++++ src/include/romstage_handoff.h | 10 ++- src/lib/Makefile.inc | 1 + src/lib/cbfs.c | 53 -------------- src/lib/loaders/Makefile.inc | 21 ++++++ src/lib/loaders/cbfs_ramstage_loader.c | 67 +++++++++++++++++ src/lib/loaders/load_and_run_ramstage.c | 100 ++++++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 4 -- src/vendorcode/google/chromeos/vboot_loader.c | 87 ++++++++++------------ 13 files changed, 297 insertions(+), 130 deletions(-) diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c index 3d56e19..ca8d61b 100644 --- a/src/arch/x86/lib/cbfs_and_run.c +++ b/src/arch/x86/lib/cbfs_and_run.c @@ -17,27 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> -#include <cbfs.h> #include <arch/stages.h> -#include <timestamp.h> - -static void cbfs_and_run_core(const char *filename) -{ - u8 *dst; - - timestamp_add_now(TS_START_COPYRAM); - print_debug("Loading image.\n"); - dst = cbfs_load_stage(CBFS_DEFAULT_MEDIA, filename); - if ((void *)dst == (void *) -1) - die("FATAL: Essential component is missing.\n"); - - timestamp_add_now(TS_END_COPYRAM); - print_debug("Jumping to image.\n"); - stage_exit(dst); -} +#include <ramstage_loader.h> void asmlinkage copy_and_run(void) { - cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram"); + run_ramstage(); } diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 60a1c3a..9e27668 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -309,8 +309,6 @@ void romstage_after_car(void) prepare_for_resume(handoff); - vboot_verify_firmware(handoff); - /* Load the ramstage. */ copy_and_run(); } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index c05566d..9ce862b 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -83,6 +83,10 @@ void selfboot(void *entry); /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); +#if defined(__PRE_RAM__) +struct romstage_handoff; +struct cbmem_entry; + #if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) /* The cache_loaded_ramstage() and load_cached_ramstage() functions are defined * to be weak so that board and chipset code may override them. Their job is to @@ -90,9 +94,6 @@ int init_default_cbfs_media(struct cbfs_media *media); * relocated ramstage is saved using the cbmem infrastructure. These * functions are only valid during romstage. */ -struct romstage_handoff; -struct cbmem_entry; - /* The implementer of cache_loaded_ramstage() may use the romstage_handoff * structure to store information, but note that the handoff variable can be * NULL. The ramstage cbmem_entry represents the region occupied by the loaded @@ -105,7 +106,22 @@ cache_loaded_ramstage(struct romstage_handoff *handoff, void * __attribute__((weak)) load_cached_ramstage(struct romstage_handoff *handoff, const struct cbmem_entry *ramstage); +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static inline void cache_loaded_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage, void *entry_point) +{ +} + +static inline void * +load_cached_ramstage(struct romstage_handoff *handoff, + const struct cbmem_entry *ramstage) +{ + return NULL; +} + #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ +#endif /* defined(__PRE_RAM__) */ #endif diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..b47a847 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -66,6 +66,7 @@ #define CBMEM_ID_HOB_POINTER 0x484f4221 #ifndef __ASSEMBLER__ +#include <stddef.h> #include <stdint.h> struct cbmem_entry; @@ -150,6 +151,10 @@ void cbmem_late_set_table(uint64_t base, uint64_t size); void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); +static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) +{ + return NULL; +} #endif /* CONFIG_DYNAMIC_CBMEM */ /* Common API between cbmem and dynamic cbmem. */ diff --git a/src/include/ramstage_loader.h b/src/include/ramstage_loader.h new file mode 100644 index 0000000..ad085c0 --- /dev/null +++ b/src/include/ramstage_loader.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef RAMSTAGE_LOADER_H +#define RAMSTAGE_LOADER_H + +#include <stdint.h> +struct cbmem_entry; + +/* Run ramstage from romstage. */ +void run_ramstage(void); + +struct ramstage_loader_ops { + const char *name; + void *(*load)(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry); +}; + +#endif /* RAMSTAGE_LOADER_H */ diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 699838a..307babd 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -41,6 +41,7 @@ struct romstage_handoff { }; #if defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT /* The romstage_handoff_find_or_add() function provides the necessary logic * for initializing the romstage_handoff structure in cbmem. Different components * of the romstage may be responsible for setting up different fields. Therefore @@ -63,7 +64,14 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) return handoff; } -#endif +#else /* CONFIG_EARLY_CBMEM_INIT */ +static inline struct romstage_handoff *romstage_handoff_find_or_add(void) +{ + return NULL; +} +#endif /* CONFIG_EARLY_CBMEM_INIT */ + +#endif /* defined(__PRE_RAM__) */ #endif /* ROMSTAGE_HANDOFF_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 79ceebf..5c37329 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -16,6 +16,7 @@ # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +subdirs-y += loaders bootblock-y += cbfs.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 9fe1757..f2a2587 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -123,58 +123,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, return dest; } -#if CONFIG_RELOCATABLE_RAMSTAGE && defined(__PRE_RAM__) - -#include <rmodule.h> -#include <romstage_handoff.h> -static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, - struct romstage_handoff *handoff) -{ - struct rmod_stage_load rmod_ram = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = name, - }; - - if (rmodule_stage_load_from_cbfs(&rmod_ram)) { - printk(BIOS_DEBUG, "Could not load ramstage.\n"); - return (void *) -1; - } - - cache_loaded_ramstage(handoff, rmod_ram.cbmem_entry, rmod_ram.entry); - - return rmod_ram.entry; -} - -void * cbfs_load_stage(struct cbfs_media *media, const char *name) -{ - struct romstage_handoff *handoff; - const struct cbmem_entry *ramstage; - void *entry; - - handoff = romstage_handoff_find_or_add(); - - if (handoff == NULL) { - LOG("Couldn't find or allocate romstage handoff.\n"); - return load_stage_from_cbfs(media, name, handoff); - } else if (!handoff->s3_resume) - return load_stage_from_cbfs(media, name, handoff); - - ramstage = cbmem_entry_find(CBMEM_ID_RAMSTAGE); - - if (ramstage == NULL) - return load_stage_from_cbfs(media, name, handoff); - - /* S3 resume path. Load a cached copy of the loaded ramstage. If - * return value is NULL load from cbfs. */ - entry = load_cached_ramstage(handoff, ramstage); - if (entry == NULL) - return load_stage_from_cbfs(media, name, handoff); - - return entry; -} - -#else - void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) @@ -211,7 +159,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ #if !CONFIG_ALT_CBFS_LOAD_PAYLOAD void *cbfs_load_payload(struct cbfs_media *media, const char *name) diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc new file mode 100644 index 0000000..eceaa00 --- /dev/null +++ b/src/lib/loaders/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-y += cbfs_ramstage_loader.c +romstage-y += load_and_run_ramstage.c diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c new file mode 100644 index 0000000..5d5cc0b --- /dev/null +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbfs.h> +#include <arch/stages.h> +#include <ramstage_loader.h> +#include <timestamp.h> + +#if CONFIG_RELOCATABLE_RAMSTAGE +#include <rmodule.h> + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + struct rmod_stage_load rmod_ram = { + .cbmem_id = cbmem_id, + .name = name, + }; + + if (rmodule_stage_load_from_cbfs(&rmod_ram)) { + printk(BIOS_DEBUG, "Could not load ramstage.\n"); + return NULL; + } + + *cbmem_entry = rmod_ram.cbmem_entry; + + return rmod_ram.entry; +} + +#else /* CONFIG_RELOCATABLE_RAMSTAGE */ + +static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name); + + if ((void *)entry == (void *) -1) + entry = NULL; + + return entry; +} + +#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ + +const struct ramstage_loader_ops cbfs_ramstage_loader = { + .name = "CBFS", + .load = cbfs_load_ramstage, +}; diff --git a/src/lib/loaders/load_and_run_ramstage.c b/src/lib/loaders/load_and_run_ramstage.c new file mode 100644 index 0000000..be2be82 --- /dev/null +++ b/src/lib/loaders/load_and_run_ramstage.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <cbmem.h> +#include <ramstage_loader.h> +#include <romstage_handoff.h> +#include <timestamp.h> + +extern const struct ramstage_loader_ops cbfs_ramstage_loader; +extern const struct ramstage_loader_ops vboot_ramstage_loader; + +static const struct ramstage_loader_ops *loaders[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_ramstage_loader, +#endif + &cbfs_ramstage_loader, +}; + +static const char *ramstage_name = CONFIG_CBFS_PREFIX "/coreboot_ram"; +static const uint32_t ramstage_id = CBMEM_ID_RAMSTAGE; + +static void +load_ramstage(const struct ramstage_loader_ops *ops, struct romstage_handoff *handoff) +{ + const struct cbmem_entry *cbmem_entry; + void *entry_point; + + timestamp_add_now(TS_START_COPYRAM); + entry_point = ops->load(ramstage_id, ramstage_name, &cbmem_entry); + + if (entry_point == NULL) + return; + + cache_loaded_ramstage(handoff, cbmem_entry, entry_point); + + timestamp_add_now(TS_END_COPYRAM); + + stage_exit(entry_point); +} + +static void run_ramstage_from_resume(struct romstage_handoff *handoff) +{ + void *entry; + const struct cbmem_entry *cbmem_entry; + + if (handoff != NULL && handoff->s3_resume) { + cbmem_entry = cbmem_entry_find(ramstage_id); + + /* No place to load ramstage. */ + if (cbmem_entry == NULL) + return; + + /* Load the cached ramstage to runtime location. */ + entry = load_cached_ramstage(handoff, cbmem_entry); + + if (entry != NULL) { + print_debug("Jumping to image.\n"); + stage_exit(entry); + } + } +} + +void run_ramstage(void) +{ + struct romstage_handoff *handoff; + const struct ramstage_loader_ops *ops; + int i; + + handoff = romstage_handoff_find_or_add(); + + run_ramstage_from_resume(handoff); + + for (i = 0; i < ARRAY_SIZE(loaders); i++) { + ops = loaders[i]; + printk(BIOS_DEBUG, "Trying %s ramstage loader.\n", ops->name); + load_ramstage(ops, handoff); + } + + die("Ramstage was not loaded!\n"); +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 5493801..0359c91 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -46,14 +46,10 @@ int recovery_mode_enabled(void); /* functions implemented in vboot.c */ void init_chromeos(int bootmode); -struct romstage_handoff; #if CONFIG_VBOOT_VERIFY_FIRMWARE -void vboot_verify_firmware(struct romstage_handoff *handoff); void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); -#else -static inline void vboot_verify_firmware(struct romstage_handoff *h) {} #endif #endif diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index cc7c25d..0c5220a 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -26,6 +26,7 @@ #include <console/vtxprintf.h> #include <pc80/tpm.h> #include <reset.h> +#include <ramstage_loader.h> #include <romstage_handoff.h> #include <rmodule.h> #include <string.h> @@ -141,27 +142,52 @@ static void vboot_invoke_wrapper(struct vboot_handoff *vboot_handoff) vboot_run_stub(&context); } -static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, - struct romstage_handoff *handoff) +static void *vboot_load_ramstage(uint32_t cbmem_id, const char *name, + const struct cbmem_entry **cbmem_entry) { + struct vboot_handoff *vboot_handoff; struct cbfs_stage *stage; const struct firmware_component *fwc; struct rmod_stage_load rmod_load = { - .cbmem_id = CBMEM_ID_RAMSTAGE, - .name = CONFIG_CBFS_PREFIX "/coreboot_ram", + .cbmem_id = cbmem_id, + .name = name, }; + timestamp_add_now(TS_START_VBOOT); + + vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, + sizeof(*vboot_handoff)); + + if (vboot_handoff == NULL) { + printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); + return NULL; + } + + memset(vboot_handoff, 0, sizeof(*vboot_handoff)); + + vboot_invoke_wrapper(vboot_handoff); + + timestamp_add_now(TS_END_VBOOT); + + /* Take RO firmware path since no RW area was selected. */ + if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && + vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { + printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", + vboot_handoff->selected_firmware); + return NULL; + } + if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) { printk(BIOS_ERR, "Invalid ramstage index: %d\n", CONFIG_VBOOT_RAMSTAGE_INDEX); - return; + return NULL; } /* Check for invalid address. */ fwc = &vboot_handoff->components[CONFIG_VBOOT_RAMSTAGE_INDEX]; if (fwc->address == 0) { printk(BIOS_DEBUG, "RW ramstage image address invalid.\n"); - return; + return NULL; } printk(BIOS_DEBUG, "RW ramstage image at 0x%08x, 0x%08x bytes.\n", @@ -169,53 +195,18 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff, stage = (void *)fwc->address; - timestamp_add_now(TS_START_COPYRAM); - if (rmodule_stage_load(&rmod_load, stage)) { vboot_handoff->selected_firmware = VB_SELECT_FIRMWARE_READONLY; printk(BIOS_DEBUG, "Could not load ramstage region.\n"); - return; + return NULL; } - cache_loaded_ramstage(handoff, rmod_load.cbmem_entry, rmod_load.entry); - - timestamp_add_now(TS_END_COPYRAM); + *cbmem_entry = rmod_load.cbmem_entry; - stage_exit(rmod_load.entry); + return rmod_load.entry; } -void vboot_verify_firmware(struct romstage_handoff *handoff) -{ - struct vboot_handoff *vboot_handoff; - - /* Don't go down verified boot path on S3 resume. */ - if (handoff != NULL && handoff->s3_resume) - return; - - timestamp_add_now(TS_START_VBOOT); - - vboot_handoff = cbmem_add(CBMEM_ID_VBOOT_HANDOFF, - sizeof(*vboot_handoff)); - - if (vboot_handoff == NULL) { - printk(BIOS_DEBUG, "Could not add vboot_handoff structure.\n"); - return; - } - - memset(vboot_handoff, 0, sizeof(*vboot_handoff)); - - vboot_invoke_wrapper(vboot_handoff); - - timestamp_add_now(TS_END_VBOOT); - - /* Take RO firmware path since no RW area was selected. */ - if (vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_A && - vboot_handoff->selected_firmware != VB_SELECT_FIRMWARE_B) { - printk(BIOS_DEBUG, "No RW firmware selected: 0x%08x\n", - vboot_handoff->selected_firmware); - return; - } - - /* Load ramstage from the vboot_handoff structure. */ - vboot_load_ramstage(vboot_handoff, handoff); -} +const struct ramstage_loader_ops vboot_ramstage_loader = { + .name = "VBOOT", + .load = vboot_load_ramstage, +};

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coreboot-gerrit February 2014