coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

New patch to review for coreboot: 1bba4c1 baytrail: gpio: add configs for PU/PD functional pins
by Aaron Durbin 12 Feb '14

12 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5209 -gerrit commit 1bba4c1b1495ab44d1331bffedfe1c11357ce67f Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Oct 11 12:39:48 2013 -0700 baytrail: gpio: add configs for PU/PD functional pins Pull-ups and pull-downs can be active on functional pins. Add configs for these options so they can be specified on board GPIO maps. TEST=Manual on bayleybay. Verify that platform boots to payload load. BUG=chrome-os-partner:22863 Change-Id: Ie4f77d8ce812f086cc8fe5a6bfcac59669f56f92 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172766 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 62 ++++++++++++++-------------------- 1 file changed, 25 insertions(+), 37 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index f62f5c8..a180ba7 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -187,47 +187,35 @@ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } -#define GPIO_FUNC0 \ +/* Define no-pull / PU / PD configs for each functional config option */ +#define _GPIO_FUNC(_func, _pu, _str) \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC0 | PAD_CONFIG0_DEFAULT, \ + .pad_conf0 = PAD_FUNC##_func | PAD_PU_##_pu | PAD_PU_##_str | \ + PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_DEFAULT } -#define GPIO_FUNC1 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC1 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC2 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC2 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC3 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC3 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC4 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC4 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC5 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC5 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC6 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC6 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } +#define GPIO_FUNC0 _GPIO_FUNC(0, DISABLE, 10K) +#define GPIO_FUNC0_PU_10K _GPIO_FUNC(0, UP, 10K) +#define GPIO_FUNC0_PD_10K _GPIO_FUNC(0, DOWN, 10K) +#define GPIO_FUNC1 _GPIO_FUNC(1, DISABLE, 10K) +#define GPIO_FUNC1_PU_10K _GPIO_FUNC(1, UP, 10K) +#define GPIO_FUNC1_PD_10K _GPIO_FUNC(1, DOWN, 10K) +#define GPIO_FUNC2 _GPIO_FUNC(2, DISABLE, 10K) +#define GPIO_FUNC2_PU_10K _GPIO_FUNC(2, UP, 10K) +#define GPIO_FUNC2_PD_10K _GPIO_FUNC(2, DOWN, 10K) +#define GPIO_FUNC3 _GPIO_FUNC(3, DISABLE, 10K) +#define GPIO_FUNC3_PU_10K _GPIO_FUNC(3, UP, 10K) +#define GPIO_FUNC3_PD_10K _GPIO_FUNC(3, DOWN, 10K) +#define GPIO_FUNC4 _GPIO_FUNC(4, DISABLE, 10K) +#define GPIO_FUNC4_PU_10K _GPIO_FUNC(4, UP, 10K) +#define GPIO_FUNC4_PD_10K _GPIO_FUNC(4, DOWN, 10K) +#define GPIO_FUNC5 _GPIO_FUNC(5, DISABLE, 10K) +#define GPIO_FUNC5_PU_10K _GPIO_FUNC(5, UP, 10K) +#define GPIO_FUNC5_PD_10K _GPIO_FUNC(5, DOWN, 10K) +#define GPIO_FUNC6 _GPIO_FUNC(6, DISABLE, 10K) +#define GPIO_FUNC6_PU_10K _GPIO_FUNC(6, UP, 10K) +#define GPIO_FUNC6_PD_10K _GPIO_FUNC(6, DOWN, 10K) /* End marker */ #define GPIO_LIST_END 0xffffffff

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Patch set updated for coreboot: 4e92f69 baytrail: add vboot ramstage verification
by Aaron Durbin 12 Feb '14

12 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4880 -gerrit commit 4e92f69015c849b719b76884d64eb12bccc07bcd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 21:03:50 2013 -0500 baytrail: add vboot ramstage verification Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/romstage/romstage.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4228615..4d74b53 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -25,12 +25,15 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h> static inline uint64_t timestamp_get(void) @@ -169,6 +172,9 @@ void asmlinkage romstage_after_car(void) timestamp_add_now(TS_END_ROMSTAGE); + /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + /* Load the ramstage. */ copy_and_run(); while (1); @@ -270,3 +276,25 @@ static void *setup_stack_and_mttrs(void) return slot; } + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = (1 << 20); + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; +} + +void ramstage_cache_invalid(struct ramstage_cache *cache) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} +

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New patch to review for coreboot: 1d57a3f baytrail: gpio: add configs for PU/PD functional pins
by Aaron Durbin 12 Feb '14

12 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5208 -gerrit commit 1d57a3ff020e0645f2d4b9be51641232f741c8b8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 12 15:19:23 2014 -0600 baytrail: gpio: add configs for PU/PD functional pins Pull-ups and pull-downs can be active on functional pins. Add configs for these options so they can be specified on board GPIO maps. Change-Id: Ia0ee18fee324053caa7eecaf974e9a8e3150eb22 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 62 ++++++++++++++-------------------- 1 file changed, 25 insertions(+), 37 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index f62f5c8..a180ba7 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -187,47 +187,35 @@ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } -#define GPIO_FUNC0 \ +/* Define no-pull / PU / PD configs for each functional config option */ +#define _GPIO_FUNC(_func, _pu, _str) \ { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC0 | PAD_CONFIG0_DEFAULT, \ + .pad_conf0 = PAD_FUNC##_func | PAD_PU_##_pu | PAD_PU_##_str | \ + PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_DEFAULT } -#define GPIO_FUNC1 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC1 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC2 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC2 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC3 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC3 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC4 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC4 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC5 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC5 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -#define GPIO_FUNC6 \ - { .use_sel = GPIO_USE_PAD, \ - .pad_conf0 = PAD_FUNC6 | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } +#define GPIO_FUNC0 _GPIO_FUNC(0, DISABLE, 10K) +#define GPIO_FUNC0_PU_10K _GPIO_FUNC(0, UP, 10K) +#define GPIO_FUNC0_PD_10K _GPIO_FUNC(0, DOWN, 10K) +#define GPIO_FUNC1 _GPIO_FUNC(1, DISABLE, 10K) +#define GPIO_FUNC1_PU_10K _GPIO_FUNC(1, UP, 10K) +#define GPIO_FUNC1_PD_10K _GPIO_FUNC(1, DOWN, 10K) +#define GPIO_FUNC2 _GPIO_FUNC(2, DISABLE, 10K) +#define GPIO_FUNC2_PU_10K _GPIO_FUNC(2, UP, 10K) +#define GPIO_FUNC2_PD_10K _GPIO_FUNC(2, DOWN, 10K) +#define GPIO_FUNC3 _GPIO_FUNC(3, DISABLE, 10K) +#define GPIO_FUNC3_PU_10K _GPIO_FUNC(3, UP, 10K) +#define GPIO_FUNC3_PD_10K _GPIO_FUNC(3, DOWN, 10K) +#define GPIO_FUNC4 _GPIO_FUNC(4, DISABLE, 10K) +#define GPIO_FUNC4_PU_10K _GPIO_FUNC(4, UP, 10K) +#define GPIO_FUNC4_PD_10K _GPIO_FUNC(4, DOWN, 10K) +#define GPIO_FUNC5 _GPIO_FUNC(5, DISABLE, 10K) +#define GPIO_FUNC5_PU_10K _GPIO_FUNC(5, UP, 10K) +#define GPIO_FUNC5_PD_10K _GPIO_FUNC(5, DOWN, 10K) +#define GPIO_FUNC6 _GPIO_FUNC(6, DISABLE, 10K) +#define GPIO_FUNC6_PU_10K _GPIO_FUNC(6, UP, 10K) +#define GPIO_FUNC6_PD_10K _GPIO_FUNC(6, DOWN, 10K) /* End marker */ #define GPIO_LIST_END 0xffffffff

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Patch merged into coreboot/master: ad93af5 PCI: Add capability list parser to romstage
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit ad93af5c5e48c4882a63447b9d3b8d1def8f7277 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 11 19:56:57 2014 +0200 PCI: Add capability list parser to romstage These are almost one-to-one copies from pci_device.c. However, devicetree has not been enumerated yet and we have no console. Change-Id: Ic80c781626521d03adde05bdb1916acce31290ea Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5196 for details. -gerrit

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Patch set updated for coreboot: 55c54e6 baytrail: add vboot ramstage verification
by Aaron Durbin 12 Feb '14

12 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4880 -gerrit commit 55c54e62ef4db04933f67038457be97b157c141c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 21:03:50 2013 -0500 baytrail: add vboot ramstage verification Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/romstage/romstage.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4228615..4d74b53 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -25,12 +25,15 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h> static inline uint64_t timestamp_get(void) @@ -169,6 +172,9 @@ void asmlinkage romstage_after_car(void) timestamp_add_now(TS_END_ROMSTAGE); + /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + /* Load the ramstage. */ copy_and_run(); while (1); @@ -270,3 +276,25 @@ static void *setup_stack_and_mttrs(void) return slot; } + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = (1 << 20); + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; +} + +void ramstage_cache_invalid(struct ramstage_cache *cache) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} +

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Patch merged into coreboot/master: c97cc98 PCI: Drop includes under cpu
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit c97cc980d42f48ab861ee0cae4d5773503bd9aa0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 12 14:45:02 2014 +0200 PCI: Drop includes under cpu The files affected do not make any PCI configuration calls. If they did, the more correct includes would be pci_ops.h, pci_defs.h and pci_ids.h. Change-Id: I3e7f009371be6ea50318eaabf0c15500cb3f1210 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5200 for details. -gerrit

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Patch merged into coreboot/master: c80879f PCI: Guard pci.h with CONFIG_PCI
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit c80879f36e0d0b7295510edbaad26d9807ce5007 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 12 14:18:50 2014 +0200 PCI: Guard pci.h with CONFIG_PCI Adding PCI functions for romstage in pci.h breaks ARMv7 build without this. Also fix two related includes to use pci_def.h instead. Change-Id: I5291eaf6ddf5a584f50af29cf791d2ca4d9caa71 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5199 for details. -gerrit

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Patch merged into coreboot/master: 3cdb0a9 usbdebug: Split to USB host/device
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit 3cdb0a915b4db35adb1e65f56f19a2b44dc7e60b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 9 23:35:39 2014 +0200 usbdebug: Split to USB host/device Top-level interface to console over USB mut not require low-level details of ECHI debug port internals. Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5197 for details. -gerrit

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Patch set updated for coreboot: ea7ab4f baytrail: add vboot ramstage verification
by Aaron Durbin 12 Feb '14

12 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4880 -gerrit commit ea7ab4fbc1b291810aebe37a356badf9b6b0df3f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 21:03:50 2013 -0500 baytrail: add vboot ramstage verification Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/romstage/romstage.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 293ed21..33c0d56 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,6 +9,7 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 4228615..4d74b53 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -25,12 +25,15 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> +#include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h> static inline uint64_t timestamp_get(void) @@ -169,6 +172,9 @@ void asmlinkage romstage_after_car(void) timestamp_add_now(TS_END_ROMSTAGE); + /* Run vboot verification if configured. */ + vboot_verify_firmware(romstage_handoff_find_or_add()); + /* Load the ramstage. */ copy_and_run(); while (1); @@ -270,3 +276,25 @@ static void *setup_stack_and_mttrs(void) return slot; } + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = (1 << 20); + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[CONFIG_SMM_TSEG_SIZE - cache_size]; +} + +void ramstage_cache_invalid(struct ramstage_cache *cache) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} +

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New patch to review for coreboot: 47cc528 test: empty commit
by Aaron Durbin 12 Feb '14

12 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5203 -gerrit commit 47cc5288897b5edeaf414b575b4b2bf5d19ec4bd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 12 14:36:15 2014 -0600 test: empty commit Change-Id: Ia57d0dd85ba1a564d2a141b4f4d258ff3f22e38f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>

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coreboot-gerrit February 2014