coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 01ff7f0 google/rambi: Re-add option to hardcode location of spd.bin
by Alexandru Gagniuc 13 Feb '14

13 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5212 -gerrit commit 01ff7f0e3efd452376f5516d178aa5d970d0f979 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Feb 13 00:16:56 2014 +0100 google/rambi: Re-add option to hardcode location of spd.bin This is a partial revert of: * 76e25b6 google boards: Do not hardcode location of spd.bin Hardcoding the location of spd.bin is apparently useful during manufacturing. Exactly how and why is irrelevant for coreboot master, but we try to be a good citizen and accomodate all reasonable use cases. As such, allow the location of spd.bin to be specified when running a CHROMEOS build. This also removes the "select CHROMEOS" from rambi, as the correct variable should be "MAINBOARD_HAS_CHROMEOS", while "CHROMEOS" is reserved for the user. Change-Id: I6ca0238e9a11566ec1129a16b5cd507d9951cbd3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/rambi/Kconfig | 8 +++++++- src/mainboard/google/rambi/spd/Makefile.inc | 4 ++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 292d321..d316feb 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS - select CHROMEOS config MAINBOARD_DIR string @@ -32,4 +31,11 @@ config HAVE_ME_BIN bool default n +# Positioning spd.bin at a fixed address is useful during manufacturing, but +# offers no benefit otherwise, hence only present the option with ChromeOS +config SPD_CBFS_ADDRESS + depends on CHROMEOS + hex "Location of SPD in CBFS" + default 0xfffec000 + endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc index 36f4b66..0ec7b39 100644 --- a/src/mainboard/google/rambi/spd/Makefile.inc +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -43,3 +43,7 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +# See comment in rambi/Kconfig for why this is done like this +ifeq ($(CONFIG_CHROMEOS),y) +spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS) +endif

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Patch set updated for coreboot: 0a38fea intel/bd82x6x: Rename SATA speed "support" register to "limit"
by Alexandru Gagniuc 13 Feb '14

13 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4777 -gerrit commit 0a38feaddc9081953c8b4615fbbed212c036bf2b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 21 18:31:35 2014 -0600 intel/bd82x6x: Rename SATA speed "support" register to "limit" "sata_interface_speed_support" implies that we must tell coreboot, via devicetree.cb at what speed the SATA ports can operate. However, that is not necessary, and the actual use of this register is to limit the speed of all ports connected to the PCH. As such, use "sata_interface_speed_limit" as a better name. Change-Id: Icb07644d7bb044687b6b571bee6e2bde7f4cab85 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/butterfly/devicetree.cb | 2 +- src/mainboard/google/stout/devicetree.cb | 2 +- src/mainboard/kontron/ktqm77/devicetree.cb | 2 +- src/mainboard/lenovo/x230/devicetree.cb | 2 +- src/southbridge/intel/bd82x6x/chip.h | 16 +++++++++++----- src/southbridge/intel/bd82x6x/sata.c | 4 ++-- src/southbridge/intel/ibexpeak/sata.c | 4 ++-- 7 files changed, 19 insertions(+), 13 deletions(-) diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9a7a1d5..36f3ba3 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2" + register "sata_interface_speed_limit" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 653d3fe..e157035 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -59,7 +59,7 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2" + register "sata_interface_speed_limit" = "0x2" # Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index f6390ac..c850609 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/intel/sandybridge # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) - register "sata_interface_speed_support" = "0x3" + register "sata_interface_speed_limit" = "0x3" # TODO: Enable generic LPC decodes... register "gen1_dec" = "0x001c02e1" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a76de5f..cd708a5 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -58,7 +58,7 @@ chip northbridge/intel/sandybridge # Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata) register "sata_port_map" = "0x7" # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" + register "sata_interface_speed_limit" = "0x3" register "gen1_dec" = "0x7c1601" register "gen2_dec" = "0x0c15e1" diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 0f2f0e9..c722da5 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -69,15 +69,21 @@ struct southbridge_intel_bd82x6x_config { uint32_t sata_port1_gen3_tx; /** - * SATA Interface Speed Support Configuration + * SATA Interface Speed Support Configuration (ISS) + * + * This option limits the maximum SATA link speed on all SATA ports. + * For systems with a mix of 6G and 3G ports, each port will operate up + * to its capability, but not any higher than the limit set here. This + * option should only be used if the SATA port cannot operate at its + * full speed due to hardware bugs, such as board mis-routing. * * Only the lower two bits have a meaning: * 00 - No effect (leave as chip default) - * 01 - 1.5 Gb/s maximum speed - * 10 - 3.0 Gb/s maximum speed - * 11 - 6.0 Gb/s maximum speed + * 01 - 1.5 Gb/s maximum speed (Gen 1) + * 10 - 3.0 Gb/s maximum speed (Gen 2) + * 11 - 6.0 Gb/s maximum speed (Gen 3) */ - uint8_t sata_interface_speed_support; + uint8_t sata_interface_speed_limit; uint32_t gen1_dec; uint32_t gen2_dec; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 133ebee..8d12202 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -107,10 +107,10 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ - if (config->sata_interface_speed_support) + if (config->sata_interface_speed_limit) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) + reg32 |= (config->sata_interface_speed_limit & 0x03) << 20; } write32(abar + 0x00, reg32); diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 078dc8e..2a6e454 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -110,9 +110,9 @@ static void sata_init(struct device *dev) reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS /* Set ISS, if available */ - if (config->sata_interface_speed_support) { + if (config->sata_interface_speed_limit) { reg32 &= ~0x00f00000; - reg32 |= (config->sata_interface_speed_support & 0x03) + reg32 |= (config->sata_interface_speed_limit & 0x03) << 20; } write32(abar + 0x00, reg32);

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Patch set updated for coreboot: d8ba4b6 uio_usbdebug: User-space-i/o framework for usbdebug
by Nico Huber 13 Feb '14

13 Feb '14

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4695 -gerrit commit d8ba4b63ff4c59f54300ccce2976225c69b93a7e Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Jan 1 20:47:55 2014 +0100 uio_usbdebug: User-space-i/o framework for usbdebug uio_usbdebug enables you to debug coreboot's usbdebug driver inside a running operating system (only Linux at this time). This comes very handy if you're hacking the usbdebug driver and don't have any other debug output from coreboot itself. Currently, only Intel chipsets are supported. Change-Id: Iaf0bcd4b4c01ae0b099d1206d553344054a62f31 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/uio_usbdebug/Makefile | 44 ++++++++++++++ util/uio_usbdebug/README | 77 ++++++++++++++++++++++++ util/uio_usbdebug/console/printk.c | 34 +++++++++++ util/uio_usbdebug/device/device_util.c | 42 +++++++++++++ util/uio_usbdebug/device/pci_device.c | 30 ++++++++++ util/uio_usbdebug/device/pci_ops.c | 25 ++++++++ util/uio_usbdebug/lib/cbmem.c | 8 +++ util/uio_usbdebug/linux/Makefile | 13 ++++ util/uio_usbdebug/linux/uio_ehci_pci.c | 106 +++++++++++++++++++++++++++++++++ util/uio_usbdebug/uio_usbdebug.c | 60 +++++++++++++++++++ util/uio_usbdebug/uio_usbdebug_intel.c | 41 +++++++++++++ 11 files changed, 480 insertions(+) diff --git a/util/uio_usbdebug/Makefile b/util/uio_usbdebug/Makefile new file mode 100644 index 0000000..0ec9a8e --- /dev/null +++ b/util/uio_usbdebug/Makefile @@ -0,0 +1,44 @@ +include ../../.config + +ARCHDIR-$(CONFIG_ARCH_ARMV7) := armv7 +ARCHDIR-$(CONFIG_ARCH_X86) := x86 + +# Only Intel chipsets supported, currently. +OBJ-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON) += uio_usbdebug_intel.o + +PROGRAM := uio_usbdebug + +CB_SRC := $(shell realpath ../../src) +CB_SOURCES := drivers/usb/pci_ehci.c drivers/usb/ehci_debug.c +CB_INCLUDES := drivers/usb/ehci.h drivers/usb/ehci_debug.h \ + drivers/usb/usb_ch9.h +OBJECTS := uio_usbdebug.o \ + console/printk.o \ + device/device_util.o device/pci_device.o device/pci_ops.o \ + lib/cbmem.o \ + $(OBJ-y) \ + $(patsubst %.c,%.o,$(CB_SOURCES)) + +CONFIG_H := ../../build/config.h + +CFLAGS += -m32 -g \ + -Wall -Wextra -Werror \ + -Wno-unused-parameter -Wno-error=sign-compare +CPPFLAGS += -I../../src/include/ -I../../src/arch/$(ARCHDIR-y)/include/ \ + -include$(CONFIG_H) + +all: $(PROGRAM) + +$(PROGRAM): $(OBJECTS) $(OBJ-y) + $(CC) $(CFLAGS) $(LDFLAGS) -o $@ $(OBJECTS) + +$(CB_SOURCES) $(CB_INCLUDES): + @mkdir -p $(dir $@) + @ln -sf $(CB_SRC)/$@ $@ + +$(OBJECTS): $(CONFIG_H) $(CB_INCLUDES) + +clean: + -@rm -rf $(CB_SOURCES) $(CB_INCLUDES) $(OBJECTS) $(PROGRAM) + +.PHONY: all clean diff --git a/util/uio_usbdebug/README b/util/uio_usbdebug/README new file mode 100644 index 0000000..2d52338 --- /dev/null +++ b/util/uio_usbdebug/README @@ -0,0 +1,77 @@ + +uio_usbdebug - Run coreboot's usbdebug driver in userspace +========================================================== + + +## Purpose + +uio_usbdebug enables you to debug coreboot's usbdebug driver inside a +running operating system (only Linux at this time). This comes very +handy if you're hacking the usbdebug driver and don't have any other +debug output from coreboot itself. + + +## State + +Currently only Intel chipsets are supported. Support for other chipsets +should be straightforward (normally just some port-enable code has to +be implemented). + +The Linux kernel driver (see linux/uio_ehci_pci.c) has only one PCI ID +hardcoded (for ICH7). The whole setup has been developed and tested on +a ThinkPad T60. + +### Files + +uio_usbdebug.c - The userspace part of the uio interface. + +uio_usbdebug_intel.c - Port enable code for Intel chipsets. + +linux/uio_ehci_pci.c - Kernel part of the uio interface. + +console/printk.c - A do_printk() implementation so you can see debug + output with CONFIG_DEBUG_USBDEBUG enabled. + +device/*.c lib/*.c - Some stubs for (hopefully) unneeded functions for + proper linking. + + +## Usage + +### Preparations + +The MMIO space has to be a whole 4K page in size and alignment to be +mapped into userspace. This is very uncommon, so you'll most probably +have to remap the MMIO space. The Linux kernel does that for you with +the `pci=resource_alignment=<pci address>` kernel parameter (e.g. +`pci=resource_alignment=0:1d.7` for ICH7). + +If your PCI device isn't listed in the kernel driver yet, you might want +to add it to the `ehci_pci_ids` table in `linux/uio_ehci_pci.c` (or do +some module alias magic if you know how to). + +### Build / Install + +Somehow like this: + +$ # Configure coreboot for your board and enable CONFIG_USBDEBUG +$ make menuconfig +$ cd util/uio_usbdebug/ +$ make -Clinux/ +$ sudo make -Clinux/ install +$ make + +### Run + +$ # Unload Linux' EHCI driver (high-speed devices will stop working) +$ sudo modprobe -r ehci-pci +$ # Load the uio driver +$ sudo modprobe uio-ehci-pci +$ # Find your uio device +$ ls /sys/module/uio_ehci_pci/drivers/*/*/uio/ +uio0 +$ # Run uio_usbdebug on this device +$ sudo ./uio_usbdebug /dev/uio0 + +Sadly, uio_usbdebug has to be run with root privileges since there are +port-80 writes in the usbdebug driver. diff --git a/util/uio_usbdebug/console/printk.c b/util/uio_usbdebug/console/printk.c new file mode 100644 index 0000000..a73407c --- /dev/null +++ b/util/uio_usbdebug/console/printk.c @@ -0,0 +1,34 @@ +/* + * This file is part of uio_usbdebug + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <stdarg.h> +#include <console/console.h> + +int do_printk(int msg_level, const char *const fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = vfprintf(stderr, fmt, args); + va_end(args); + + return i; +} diff --git a/util/uio_usbdebug/device/device_util.c b/util/uio_usbdebug/device/device_util.c new file mode 100644 index 0000000..213780e --- /dev/null +++ b/util/uio_usbdebug/device/device_util.c @@ -0,0 +1,42 @@ +/* + * This file is part of uio_usbdebug + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +static char g_path[] = { '\0' }; + +const char *dev_path(device_t dev) +{ + return g_path; +} + +struct resource *find_resource(device_t dev, unsigned index) +{ + return NULL; +} + +void report_resource_stored(device_t dev, struct resource *resource, + const char *comment) +{ +} + +struct device *dev_find_slot(unsigned int bus, unsigned int devfn) +{ + return NULL; +} diff --git a/util/uio_usbdebug/device/pci_device.c b/util/uio_usbdebug/device/pci_device.c new file mode 100644 index 0000000..980117f --- /dev/null +++ b/util/uio_usbdebug/device/pci_device.c @@ -0,0 +1,30 @@ +/* + * This file is part of uio_usbdebug + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include <device/device.h> + +unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev) +{ + return 0; +} + +void pci_dev_read_resources(struct device *dev) +{ +} diff --git a/util/uio_usbdebug/device/pci_ops.c b/util/uio_usbdebug/device/pci_ops.c new file mode 100644 index 0000000..2bcfec0 --- /dev/null +++ b/util/uio_usbdebug/device/pci_ops.c @@ -0,0 +1,25 @@ +/* + * This file is part of uio_usbdebug + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> + +u32 pci_read_config32(device_t dev, unsigned int where) +{ + return 0; +} diff --git a/util/uio_usbdebug/lib/cbmem.c b/util/uio_usbdebug/lib/cbmem.c new file mode 100644 index 0000000..6d87880 --- /dev/null +++ b/util/uio_usbdebug/lib/cbmem.c @@ -0,0 +1,8 @@ + +#include <stdint.h> +#include <stddef.h> + +void *cbmem_find(u32 id) +{ + return NULL; +} diff --git a/util/uio_usbdebug/linux/Makefile b/util/uio_usbdebug/linux/Makefile new file mode 100644 index 0000000..fd60b4f --- /dev/null +++ b/util/uio_usbdebug/linux/Makefile @@ -0,0 +1,13 @@ + +obj-m := uio_ehci_pci.o + +all: uio_ehci_pci.c + @$(MAKE) -C/lib/modules/`uname -r`/build M=$(CURDIR) modules + +install: + @$(MAKE) -C/lib/modules/`uname -r`/build M=$(CURDIR) modules_install + +clean: + -@$(MAKE) -C/lib/modules/`uname -r`/build M=$(CURDIR) clean + +.PHONY: all install clean diff --git a/util/uio_usbdebug/linux/uio_ehci_pci.c b/util/uio_usbdebug/linux/uio_ehci_pci.c new file mode 100644 index 0000000..d5c33e3 --- /dev/null +++ b/util/uio_usbdebug/linux/uio_ehci_pci.c @@ -0,0 +1,106 @@ +/* + * uio_ehci_pci - UIO driver for PCI EHCI devices + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This only implements MMIO access (no interrupts). + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/pci.h> +#include <linux/uio_driver.h> + +#define DRIVER_VERSION "0.0.1" +#define DRIVER_AUTHOR "Nico Huber <nico.h(a)gmx.de>" +#define DRIVER_DESC "UIO driver for PCI EHCI devices" +#define DRIVER_TAG "uio_ehci_pci" + +static int probe(struct pci_dev *const pci_dev, + const struct pci_device_id *const did) +{ + struct uio_info *info; + int ret; + + ret = pci_enable_device(pci_dev); + if (ret) + goto return_; + + ret = pci_request_regions(pci_dev, DRIVER_TAG); + if (ret) + goto return_disable; + + info = kzalloc(sizeof(struct uio_info), GFP_KERNEL); + if (!info) { + ret = -ENOMEM; + goto return_release; + } + + info->name = DRIVER_TAG; + info->version = DRIVER_VERSION; + + info->mem[0].name = "EHCI MMIO area"; + info->mem[0].addr = pci_resource_start(pci_dev, 0); + if (!info->mem[0].addr) { + ret = -ENODEV; + goto return_free; + } + info->mem[0].size = pci_resource_len(pci_dev, 0); + info->mem[0].memtype = UIO_MEM_PHYS; + + ret = uio_register_device(&pci_dev->dev, info); + if (ret) + goto return_free; + pci_set_drvdata(pci_dev, info); + + return 0; +return_free: + kfree(info); +return_release: + pci_release_regions(pci_dev); +return_disable: + pci_disable_device(pci_dev); +return_: + return ret; +} + +static void remove(struct pci_dev *const pci_dev) +{ + struct uio_info *const info = pci_get_drvdata(pci_dev); + + uio_unregister_device(info); + kfree(info); + pci_release_regions(pci_dev); + pci_disable_device(pci_dev); +} + +static DEFINE_PCI_DEVICE_TABLE(ehci_pci_ids) = { + { PCI_DEVICE(0x8086, 0x27cc) }, + { 0, } +}; + +static struct pci_driver uio_ehci_pci_driver = { + .name = DRIVER_TAG, + .id_table = ehci_pci_ids, + .probe = probe, + .remove = remove, +}; + +module_pci_driver(uio_ehci_pci_driver); +MODULE_VERSION(DRIVER_VERSION); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); diff --git a/util/uio_usbdebug/uio_usbdebug.c b/util/uio_usbdebug/uio_usbdebug.c new file mode 100644 index 0000000..e4024bf --- /dev/null +++ b/util/uio_usbdebug/uio_usbdebug.c @@ -0,0 +1,60 @@ +/* + * uio_usbdebug - Run coreboot's usbdebug driver in userspace + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdio.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <unistd.h> +#include <sys/mman.h> + +/* coreboot's arch/io.h conflicts with libc's sys/io.h, so declare this here: */ +int ioperm(unsigned long from, unsigned long num, int turn_on); + +#include <arch/io.h> +#include <console/usb.h> + +void *ehci_bar; + +int main(int argc, char *argv[]) +{ + if (argc != 2) { + fprintf(stderr, "Usage: %s <uio-dev>\n", argv[0]); + return 1; + } + const int fd = open(argv[1], O_RDWR); + if (fd < 0) { + perror("Failed to open uio device"); + return 2; + } + ehci_bar = + mmap(NULL, 1 << 8, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0); + if (MAP_FAILED == ehci_bar) { + perror("Failed to map ehci bar"); + close(fd); + return 3; + } + + ioperm(0x80, 1, 1); + + usbdebug_simple_init_at((unsigned)ehci_bar); + + munmap(ehci_bar, 1 << 8); + close(fd); + return 0; +} diff --git a/util/uio_usbdebug/uio_usbdebug_intel.c b/util/uio_usbdebug/uio_usbdebug_intel.c new file mode 100644 index 0000000..95aec01 --- /dev/null +++ b/util/uio_usbdebug/uio_usbdebug_intel.c @@ -0,0 +1,41 @@ +/* + * This file is part of uio_usbdebug + * + * Copyright (C) 2013 Nico Huber <nico.h(a)gmx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <console/usb.h> + +extern void *ehci_bar; + +pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx) +{ + return 0; +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + /* claim usb debug port */ + const unsigned long dbgctl_addr = + ((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET; + write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30)); +} + +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) +{ +}

1 0

Patch set updated for coreboot: a7d7a90 usbdebug: Export ehci_bar through usbdebug_simple_init_at()
by Nico Huber 13 Feb '14

13 Feb '14

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4694 -gerrit commit a7d7a904c13c2302043ac548cdbc14b5206bbebe Author: Nico Huber <nico.h(a)gmx.de> Date: Tue Jan 14 19:26:02 2014 +0100 usbdebug: Export ehci_bar through usbdebug_simple_init_at() Add usbdebug_simple_init_at() to just run the usbdebug init code with a given EHCI BAR. This makes it easier to use our usbdebug code in other contexts, say Linux userspace. Change-Id: I059d8432f654e6b55d5940d45a8fe1df27c2e51e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/drivers/usb/ehci_debug.c | 6 ++++++ src/include/console/usb.h | 1 + 2 files changed, 7 insertions(+) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index b1ae27d..a6b7cd9 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -934,3 +934,9 @@ int usbdebug_init(void) ehci_debug_hw_enable(); return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); } + +int usbdebug_simple_init_at(unsigned ehci_bar) +{ + struct ehci_debug_info *dbg_info = dbgp_ehci_info(); + return usbdebug_init_(ehci_bar, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); +} diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 430557f..d5126be 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -24,6 +24,7 @@ struct dbgp_pipe; int usbdebug_init(void); +int usbdebug_simple_init_at(unsigned ehci_bar); struct dbgp_pipe *dbgp_console_output(void); struct dbgp_pipe *dbgp_console_input(void);

1 0

New patch to review for coreboot: cf1cd10 haswell: backup the default SMM region on resume
by Aaron Durbin 13 Feb '14

13 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5217 -gerrit commit cf1cd103bb36cd6e67b3ce04f30f97fa48deacdf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 13 10:30:42 2014 -0600 haswell: backup the default SMM region on resume Haswell CPUs need to use the default SMM region for relocating to the desired SMM location. Back up that memory on resume instead of reserving the default region. This makes the haswell support more forgiving to software which expects PC-compatible memory layouts. Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/intel/haswell/Kconfig | 1 + src/cpu/intel/haswell/haswell_init.c | 8 ++++++++ src/northbridge/intel/haswell/northbridge.c | 20 ++------------------ 3 files changed, 11 insertions(+), 18 deletions(-) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 25df4d1..b13d686 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -6,6 +6,7 @@ if CPU_INTEL_HASWELL config CPU_SPECIFIC_OPTIONS def_bool y + select BACKUP_DEFAULT_SMM_REGION select SMP select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index f8d295e..d3f1ee5 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -34,6 +34,7 @@ #include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> +#include <cpu/x86/smm.h> #include <delay.h> #include <pc80/mc146818rtc.h> #include <northbridge/intel/haswell/haswell.h> @@ -754,6 +755,7 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) int max_cpus; int num_aps; const void *microcode_patch; + void *smm_save_area; /* Perform any necessary BSP initialization before APs are brought up. * This call also allows the BSP to prepare for any secondary effects @@ -762,6 +764,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) microcode_patch = intel_microcode_find(); + /* Save default SMM area before relocation occurs. */ + smm_save_area = backup_default_smm_area(); + /* This needs to be called after the mtrr setup so the BSP mtrrs * can be mirrored by the APs. */ if (setup_ap_init(cpu_bus, &max_cpus, microcode_patch)) { @@ -783,6 +788,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_patch); + /* Restore the default SMM region. */ + restore_default_smm_area(smm_save_area); + /* Enable ROM caching if option was selected. */ x86_mtrr_enable_rom_caching(); } diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8d57c03..010cc07 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -305,10 +305,7 @@ static void mc_add_dram_resources(device_t dev) /* * These are the host memory ranges that should be added: - * - 0 -> SMM_DEFAULT_BASE : cacheable - * - SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE : - * cacheable and reserved - * - SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 : cacheable + * - 0 -> 0xa0000: cacheable * - 0xc0000 -> TSEG : cacheable * - TESG -> BGSM: cacheable with standard MTRRs and reserved * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved @@ -338,21 +335,8 @@ static void mc_add_dram_resources(device_t dev) */ index = 0; - /* 0 - > SMM_DEFAULT_BASE */ + /* 0 - > 0xa0000 */ base_k = 0; - size_k = SMM_DEFAULT_BASE >> 10; - ram_resource(dev, index++, base_k, size_k); - - /* SMM_DEFAULT_BASE -> SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE */ - resource = new_resource(dev, index++); - resource->base = SMM_DEFAULT_BASE; - resource->size = SMM_DEFAULT_SIZE; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_CACHEABLE | IORESOURCE_STORED | - IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - - /* SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE -> 0xa0000 */ - base_k = (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) >> 10; size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k);

1 0

New patch to review for coreboot: 4048ccc x86: provide infrastructure to backup default SMM region
by Aaron Durbin 13 Feb '14

13 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5216 -gerrit commit 4048cccacf096acdbaed374e8ca7ad8aa45c6502 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 13 10:26:18 2014 -0600 x86: provide infrastructure to backup default SMM region Certain CPUs require the default SMM region to be backed up on resume after a suspend. The reason is that in order to relocate the SMM region the default SMM region has to be used. As coreboot is unaware of how that memory is used it needs to be backed up. Therefore provide a common method for doing this. Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/Kconfig | 6 ++++ src/cpu/x86/smm/Makefile.inc | 2 ++ src/cpu/x86/smm/backup_default_smm.c | 68 ++++++++++++++++++++++++++++++++++++ src/include/cbmem.h | 1 + src/include/cpu/x86/smm.h | 4 +++ src/lib/cbmem_info.c | 1 + 6 files changed, 82 insertions(+) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 21282c3..98238d8 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -122,3 +122,9 @@ config PARALLEL_MP This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs. + +config BACKUP_DEFAULT_SMM_REGION + def_bool n + help + The cpu support will select this option if the default SMM region + needs to be backed up for suspend/resume purposes. diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index b595a36..8dcd130 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +ramstage-$(CONFIG_BACKUP_DEFAULT_SMM_REGION) += backup_default_smm.c + ifeq ($(CONFIG_SMM_MODULES),y) smmstub-y += smm_stub.S smmstub-y += smm_module_header.c diff --git a/src/cpu/x86/smm/backup_default_smm.c b/src/cpu/x86/smm/backup_default_smm.c new file mode 100644 index 0000000..666ff23 --- /dev/null +++ b/src/cpu/x86/smm/backup_default_smm.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/smm.h> + +void *backup_default_smm_area(void) +{ + void *save_area; + const void *default_smm = (void *)SMM_DEFAULT_BASE; + + if (!CONFIG_HAVE_ACPI_RESUME) + return NULL; + + /* + * The buffer needs to be preallocated regardless. In the non-resume + * path it will be allocated for handling resume. Note that cbmem_add() + * does a find before the addition. + */ + save_area = cbmem_add(CBMEM_ID_SMM_SAVE_SPACE, SMM_DEFAULT_SIZE); + + if (save_area == NULL) { + printk(BIOS_DEBUG, "SMM save area not added.\n"); + return NULL; + } + + /* Only back up the area on S3 resume. */ + if (acpi_slp_type == 3) { + memcpy(save_area, default_smm, SMM_DEFAULT_SIZE); + return save_area; + } + + /* + * Not the S3 resume path. No need to restore memory contents after + * SMM relocation. + */ + return NULL; +} + +void restore_default_smm_area(void *smm_save_area) +{ + void *default_smm = (void *)SMM_DEFAULT_BASE; + + if (smm_save_area == NULL) + return; + + memcpy(default_smm, smm_save_area, SMM_DEFAULT_SIZE); +} diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 9e68ba9..9883091 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -61,6 +61,7 @@ #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 #define CBMEM_ID_REFCODE 0x04efc0de #define CBMEM_ID_REFCODE_CACHE 0x4efc0de5 +#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_HOB_POINTER 0x484f4221 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index bda1413..3ab43ff 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -571,4 +571,8 @@ int smm_load_module(void *smram, int size, struct smm_loader_params *params); #endif /* __SMM__ */ #endif /* CONFIG_SMM_MODULES */ +/* Backup and restore default SMM region. */ +void *backup_default_smm_area(void); +void restore_default_smm_area(void *smm_save_area); + #endif diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index de43c66..339e6b9 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -50,6 +50,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, { CBMEM_ID_REFCODE, "REFCODE " }, + { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, };

1 0

Patch merged into coreboot/master: f481171 superio/fintek: Document Fintek F71869AD code.
by gerrit＠coreboot.org 13 Feb '14

13 Feb '14

the following patch was just integrated into master: commit f48117182043fb37e885500d4b8c382ef6010417 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Feb 10 12:08:36 2014 +1100 superio/fintek: Document Fintek F71869AD code. Change-Id: I156077bf5571764d0e4bc044be80c8ab94556de4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5178 for details. -gerrit

1 0

Patch merged into coreboot/master: 1ff338c cpu/allwinner/a10: Add minimal ramstage driver
by gerrit＠coreboot.org 13 Feb '14

13 Feb '14

the following patch was just integrated into master: commit 1ff338c2816a21ff60e43c60526c222982937fe2 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 3 04:24:35 2014 -0500 cpu/allwinner/a10: Add minimal ramstage driver Change-Id: I857755976b17b0e492c086162f395a77933eeed8 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/4698 for details. -gerrit

1 0

Patch merged into coreboot/master: dc7daca baytrail: print dram configuration
by gerrit＠coreboot.org 13 Feb '14

13 Feb '14

the following patch was just integrated into master: commit dc7dacab84b67d5b6f4377d9045d2327d24de942 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 00:26:04 2013 -0500 baytrail: print dram configuration After running the MRC blob print out some information on the training: MRC version, number channels, DDR3 type, and DRAM frequency. Example output: MRC v0.90 2 channels of DDR3 @ 1066MHz Apparently there are two dunit IOSF ports -- 1 for each channel. However, certain registers really on live in channel 0. Thus, there was some changes to dunit support in the iosf area. BUG=chrome-os-partner:22875 BRANCH=None TEST=Built and booted bayleybay in different configs. Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172770 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4882 for details. -gerrit

1 0

Patch merged into coreboot/master: 6beda91 baytrail: allow downstream use of SSE instructions
by gerrit＠coreboot.org 13 Feb '14

13 Feb '14

the following patch was just integrated into master: commit 6beda91d34ce722e55b1d32c0cd6f472e7d4d891 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 12:47:47 2013 -0500 baytrail: allow downstream use of SSE instructions If a payload is compiled to use SSE instructions it will fault with an undefined opcode because SSE instructions weren't enabled. Therefore enable SSE instructions at runtime. BUG=chrome-os-partner:22991 BRANCH=None TEST=Built and booted with SSE enabled payload. No exceptions seen. Change-Id: I919c1ad319c6ce8befec5b4b1fd8c6343d51ccc1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172642 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> See http://review.coreboot.org/4881 for details. -gerrit

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coreboot-gerrit February 2014