coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 4e92f69 baytrail: add vboot ramstage verification
by gerrit＠coreboot.org 13 Feb '14

13 Feb '14

the following patch was just integrated into master: commit 4e92f69015c849b719b76884d64eb12bccc07bcd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 10 21:03:50 2013 -0500 baytrail: add vboot ramstage verification Add suport for verifying the ramstage with vboot during romstage execution. Along with this support select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM to cache the relocated ramstage 1MiB below the top end of the TSEG region. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted with CONFIG_VBOOT_VERIFY_FIRMWARE=y selected. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I355f62469bdcca62b0a4468100effab0342dc8fc Reviewed-on: https://chromium-review.googlesource.com/172712 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4880 for details. -gerrit

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Patch set updated for coreboot: 63f862e libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 13 Feb '14

13 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit 63f862e42711040702c761245901f76d1ab2efc9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 42 ++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..fb79c6b 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,44 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* + * Alignment-agnostic encode/decode bytestream to/from little/big endian. + */ + +static inline uint16_t le16dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static inline uint32_t le32dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static inline void leXXenc(void *pp, uint16_t u, uint8_t b) +{ + unsigned char *p = (unsigned char *)pp; + int i; + + for(i=0; i < b; i++) + p[i] = (u >> i*8) & 0xFF; +} + + +static inline void le16enc(void *pp, uint16_t u) +{ + leXXenc(pp, u, 2); +} + +static inline void le32enc(void *pp, uint32_t u) +{ + leXXenc(pp, u, 4); +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +139,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

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Patch set updated for coreboot: 3d0acae libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 13 Feb '14

13 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit 3d0acaea71ecad3f75b8995312edbaffaccb6342 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 41 ++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..52c2062 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,43 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* + * Alignment-agnostic encode/decode bytestream to/from little/big endian. + */ + +static inline uint16_t le16dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static inline uint32_t le32dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static inline void leXXenc(void *pp, uint16_t u, uint8_t b) +{ + unsigned char *p = (unsigned char *)pp; + + for(int i=0; i < b; i++) + p[i] = (u >> i*8) & 0xFF; +} + + +static inline void le16enc(void *pp, uint16_t u) +{ + leXXenc(pp, u, 2); +} + +static inline void le32enc(void *pp, uint32_t u) +{ + leXXenc(pp, u, 4); +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +138,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

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Patch set updated for coreboot: a08ab5b sandy/ivy: Fix mrc.cache file in CBFS
by Kyösti Mälkki 13 Feb '14

13 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5211 -gerrit commit a08ab5b59d9f5ec56bbe339e5f2e19a41363078a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 00:33:40 2014 +0200 sandy/ivy: Fix mrc.cache file in CBFS The file was not recreated when configuration changed. One would hit this bug when turning CHROMEOS on/off. Also do not create mrc.cache with CHROMEOS at all. Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/sandybridge/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index cef52b2..a201745 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -40,7 +40,8 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := 0xab -$(obj)/mrc.cache: +ifneq ($(CONFIG_CHROMEOS),y) +$(obj)/mrc.cache: $(obj)/config.h dd if=/dev/zero count=1 \ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ tr '\000' '\377' > $@ @@ -49,5 +50,6 @@ cbfs-files-$(CONFIG_HAVE_MRC_CACHE) += mrc.cache mrc.cache-file := $(obj)/mrc.cache mrc.cache-position := 0xfffd0000 mrc.cache-type := 0xac +endif $(obj)/northbridge/intel/sandybridge/acpi.ramstage.o : $(obj)/build.h

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Patch merged into coreboot/master: 714c10d Eliminate some ASL warnings
by gerrit＠coreboot.org 13 Feb '14

13 Feb '14

the following patch was just integrated into master: commit 714c10d58294ff8f628b62c959f2ad8d86f7eee7 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 23:19:02 2014 +0100 Eliminate some ASL warnings The ASL compiler warned about "Control Method should be made Serialized (due to creation of named objects within)". This commit eliminates the warnings by changing those NonSerialized into Serialized. Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> See http://review.coreboot.org/5189 for details. -gerrit

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New patch to review for coreboot: c8ff11d Revert "google boards: Do not hardcode location of spd.bin"
by Stefan Reinauer 12 Feb '14

12 Feb '14

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5212 -gerrit commit c8ff11d7fd2f81687966ae69146e34c45e51cce8 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Feb 13 00:16:56 2014 +0100 Revert "google boards: Do not hardcode location of spd.bin" This reverts commit 76e25b66ae1975212b7863eb91437f92443bfef6. Change-Id: I6ca0238e9a11566ec1129a16b5cd507d9951cbd3 --- src/mainboard/google/bolt/Makefile.inc | 1 + src/mainboard/google/falco/Makefile.inc | 1 + src/mainboard/google/link/Makefile.inc | 1 + src/mainboard/google/peppy/Makefile.inc | 1 + src/mainboard/google/rambi/Kconfig | 4 ++++ src/mainboard/google/rambi/spd/Makefile.inc | 1 + src/mainboard/google/slippy/Makefile.inc | 1 + src/mainboard/samsung/lumpy/Makefile.inc | 1 + 8 files changed, 11 insertions(+) diff --git a/src/mainboard/google/bolt/Makefile.inc b/src/mainboard/google/bolt/Makefile.inc index 4e71be7..57f6f45 100644 --- a/src/mainboard/google/bolt/Makefile.inc +++ b/src/mainboard/google/bolt/Makefile.inc @@ -43,3 +43,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index 3269d2d..50a47a5 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -48,3 +48,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index ba9a5aa..8fb69c6 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -42,3 +42,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc index 7f8cae3..62fc6b0 100644 --- a/src/mainboard/google/peppy/Makefile.inc +++ b/src/mainboard/google/peppy/Makefile.inc @@ -49,3 +49,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 292d321..db6f4e2 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -32,4 +32,8 @@ config HAVE_ME_BIN bool default n +config SPD_CBFS_ADDRESS + hex "Location of SPD in CBFS" + default 0xfffec000 + endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc index 36f4b66..84695ab 100644 --- a/src/mainboard/google/rambi/spd/Makefile.inc +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -43,3 +43,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS) diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index 7a62022..eb2e731 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -45,3 +45,4 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := 0xfffec000 diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc index bb412ce..bd47942 100644 --- a/src/mainboard/samsung/lumpy/Makefile.inc +++ b/src/mainboard/samsung/lumpy/Makefile.inc @@ -28,3 +28,4 @@ $(SPD_BIN): cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +spd.bin-position := 0xfffdc000

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Patch merged into coreboot/master: ac5ffb7 google boards: Do not hardcode location of spd.bin
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit ac5ffb75785135386c1b4dc52d4f6d0bdf151f49 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Feb 12 15:54:47 2014 -0600 google boards: Do not hardcode location of spd.bin spd.bin can reside anywhere in CBFS, and we only use CBFS APIs to access and read it. As such, there is no need to hardcode it, and it can collide with mrc.bin or mrc.cache on some boards. Do not use a specific position for spd.bin, but instead let cbfstool find the optimal placement. Change-Id: I496094d3c0de708813494095b7ac4be8addb4112 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5210 for details. -gerrit

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Patch merged into coreboot/master: 1bba4c1 baytrail: gpio: add configs for PU/PD functional pins
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit 1bba4c1b1495ab44d1331bffedfe1c11357ce67f Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Oct 11 12:39:48 2013 -0700 baytrail: gpio: add configs for PU/PD functional pins Pull-ups and pull-downs can be active on functional pins. Add configs for these options so they can be specified on board GPIO maps. TEST=Manual on bayleybay. Verify that platform boots to payload load. BUG=chrome-os-partner:22863 Change-Id: Ie4f77d8ce812f086cc8fe5a6bfcac59669f56f92 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172766 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5209 for details. -gerrit

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New patch to review for coreboot: fb2312b sandy/ivy: Fix mrc.cache file in CBFS
by Kyösti Mälkki 12 Feb '14

12 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5211 -gerrit commit fb2312b56bfb00d57899af1f19e3c32c0268b50e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 00:33:40 2014 +0200 sandy/ivy: Fix mrc.cache file in CBFS The file was not recreated when configuration changed. One would hit this bug when turning CHROMEOS on/off. Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/sandybridge/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index cef52b2..fdfcdb8 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -40,7 +40,7 @@ mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) mrc.bin-position := 0xfffa0000 mrc.bin-type := 0xab -$(obj)/mrc.cache: +$(obj)/mrc.cache: $(obj)/config.h dd if=/dev/zero count=1 \ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ tr '\000' '\377' > $@

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Patch merged into coreboot/master: 5a9c081 falco: Add ACPI code to describe the I2C touchpad device
by gerrit＠coreboot.org 12 Feb '14

12 Feb '14

the following patch was just integrated into master: commit 5a9c0814ff5d2064e17f4696ac05ab6dce8404aa Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Feb 11 10:43:21 2014 -0800 falco: Add ACPI code to describe the I2C touchpad device If the SerialIO devices are put into ACPI mode then it is possible to use ACPI to instantiate the touchpad in the kernel without needing to have a platform level driver to do the binding. This is the "new way" of describing on-board I2C devices and the upstream kernel is starting to add ACPI IDs to drivers so they can be used in this fashion. For the Cypress touchpad use a generic ACPI ID of "CYPA0000" to describe it. In order to support the proper scoping of the touchpad device under the appropriate I2C controller device the mainboard.asl file needs to be included after pch.asl so the I2C device exists. Change-Id: I81e053d27be478f3a19b6f9b13cd2b4fabcb88c0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/5194 for details. -gerrit

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coreboot-gerrit February 2014