coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: eab86e6 lenovo/x201: Support digitizer on x201t variant
by Vladimir Serbinenko 14 Feb '14

14 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5096 -gerrit commit eab86e66a6a8247cb67cce3aefa525bb0dd2e008 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 1 18:39:26 2014 +0100 lenovo/x201: Support digitizer on x201t variant Since ACPI declaration of Wacom tablet when there is none causes hangs, split x201 port to x201 and x201t. Thanks to Peter Stuge for his helpful insights Thanks to Carl-Daniel Hailfinger for info on PnP superio. Thanks to Jens Erat for letting me to experiment with his X201t. Change-Id: Idb504fabf1ac1a55d8ada8d2b2268038110e32e0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/acpi/Makefile.inc | 1 + src/ec/lenovo/h8/acpi/ec.asl | 2 +- src/ec/lenovo/h8/acpi/thermal.asl | 4 ++-- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x201/Kconfig | 6 +++++- src/mainboard/lenovo/x201/acpi/superio.asl | 18 ++++++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 14 ++++++++++++++ src/mainboard/lenovo/x201/mainboard.c | 12 ++++++++++-- src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x201t/Kconfig | 22 ++++++++++++++++++++++ src/mainboard/lenovo/x201t/board_info.txt | 6 ++++++ 11 files changed, 86 insertions(+), 7 deletions(-) diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..3b5712b 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_X201T) += ec.c diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 4b3fb12..9e983f0 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -227,7 +227,7 @@ Device(EC) ^HKEY.RHK (0x18) } -#if CONFIG_BOARD_LENOVO_X201 +#if CONFIG_BOARD_LENOVO_X201 || CONFIG_BOARD_LENOVO_X201T Method (_Q1C, 0, NotSerialized) { ^HKEY.RHK (0x19) diff --git a/src/ec/lenovo/h8/acpi/thermal.asl b/src/ec/lenovo/h8/acpi/thermal.asl index 83d66c6..cecf520 100644 --- a/src/ec/lenovo/h8/acpi/thermal.asl +++ b/src/ec/lenovo/h8/acpi/thermal.asl @@ -1,6 +1,6 @@ Scope(\_TZ) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) Name (MEBT, 0) #endif @@ -24,7 +24,7 @@ Scope(\_TZ) Return (C2K(127)) } Method(_TMP) { -#if defined (CONFIG_BOARD_LENOVO_X201) && CONFIG_BOARD_LENOVO_X201 +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201) || IS_ENABLED (CONFIG_BOARD_LENOVO_X201T) /* Avoid tripping alarm if ME isn't booted at all yet */ If (LAnd (LNot (MEBT), LEqual (\_SB.PCI0.LPCB.EC.TMP0, 128))) { Return (C2K(40)) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index b16ef7d..55dbb05 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X201 help Lenovo X201 laptop. Consult wiki for details. +config BOARD_LENOVO_X201T + bool "ThinkPad X201 Tablet" + help + Lenovo X201 convertible tablet. Consult wiki for details. + config BOARD_LENOVO_X230 bool "ThinkPad X230" help @@ -40,6 +45,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" +source "src/mainboard/lenovo/x201t/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..344aa40 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X201 +if BOARD_LENOVO_X201 || BOARD_LENOVO_X201T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -23,6 +23,8 @@ config MAINBOARD_DIR string default lenovo/x201 +if BOARD_LENOVO_X201 + config MAINBOARD_PART_NUMBER string default "3626EN1" @@ -31,6 +33,8 @@ config MAINBOARD_VERSION string default "ThinkPad X201" +endif + config MAINBOARD_VENDOR string default "LENOVO" diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl index a2657f1..19bb4c5 100644 --- a/src/mainboard/lenovo/x201/acpi/superio.asl +++ b/src/mainboard/lenovo/x201/acpi/superio.asl @@ -1 +1,19 @@ #include "../../../../drivers/pc80/ps2_controller.asl" + +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..0b978de 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index c16c3a4..775583a 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -90,7 +90,11 @@ static int int15_handler(void) const char *smbios_mainboard_version(void) { - return "Lenovo X201"; +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X201T) + return "ThinkPad X201 Tablet"; +#else + return "ThinkPad X201"; +#endif } /* Audio Setup */ @@ -106,7 +110,7 @@ static void verb_setup(void) static void mainboard_enable(device_t dev) { - device_t dev0; + device_t dev0, devwacom; u16 pmbase; printk(BIOS_SPEW, "starting SPI configuration\n"); @@ -153,6 +157,10 @@ static void mainboard_enable(device_t dev) if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) ec_write(0x0c, 0xc7); + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X201T); + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f0874d3..9b99c4e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x201t/Kconfig b/src/mainboard/lenovo/x201t/Kconfig new file mode 100644 index 0000000..45e30a2 --- /dev/null +++ b/src/mainboard/lenovo/x201t/Kconfig @@ -0,0 +1,22 @@ +if BOARD_LENOVO_X201T + +config TABLET_SPECIFIC_OPTIONS # dummy + def_bool y + select SUPERIO_NSC_PC87382 + # Following ones are for scripts benefit + select ARCH_X86 + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + +config MAINBOARD_PART_NUMBER + string + default "0831CTO" + +config MAINBOARD_VERSION + string + default "ThinkPad X201 Tablet" + +endif diff --git a/src/mainboard/lenovo/x201t/board_info.txt b/src/mainboard/lenovo/x201t/board_info.txt new file mode 100644 index 0000000..6a168fe --- /dev/null +++ b/src/mainboard/lenovo/x201t/board_info.txt @@ -0,0 +1,6 @@ +Board name: X201 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n

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Patch set updated for coreboot: 5512468 lenovo/x60: Add X60T variant as separate port.
by Vladimir Serbinenko 14 Feb '14

14 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5113 -gerrit commit 55124685f1e8b98d2cbb3870806eb18229e7065c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Feb 4 15:01:04 2014 +0100 lenovo/x60: Add X60T variant as separate port. X60 and X60T differ only by presence of wacom table on serial port on internal SuperI/O. However detecting this difference would cost in boot time and code complexity as detecting requires an attempt to communicate with wacom over slow serial connection and waiting for it to wakeup. Since presence of wacom is a characteristic of model and known to user at compile time, add it as separate mobo instead. Change-Id: If2e699cfa5d11f2cb2b9c254fc6fc71781dce228 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x60/Kconfig | 6 +++++- src/mainboard/lenovo/x60/acpi/superio.asl | 34 +++++++++++++++++++++++++++++++ src/mainboard/lenovo/x60/devicetree.cb | 7 +++++-- src/mainboard/lenovo/x60/mainboard.c | 5 +++++ src/mainboard/lenovo/x60t/Kconfig | 10 +++++++++ src/mainboard/lenovo/x60t/board_info.txt | 7 +++++++ 7 files changed, 72 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..b16ef7d 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -12,6 +12,11 @@ config BOARD_LENOVO_X60 ThinkPad X60s (Model 1702, 1703) ThinkPad X60 (Model 1709) +config BOARD_LENOVO_X60T + bool "ThinkPad X60 Tablet" + help + Lenovo X60 convertible tablet + config BOARD_LENOVO_X201 bool "ThinkPad X201" help @@ -33,6 +38,7 @@ config BOARD_LENOVO_T60 endchoice source "src/mainboard/lenovo/x60/Kconfig" +source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..36c00bc 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X60 +if BOARD_LENOVO_X60 || BOARD_LENOVO_X60T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -39,10 +39,14 @@ config DCACHE_RAM_SIZE hex default 0x8000 +if BOARD_LENOVO_X60 + config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +endif + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl index e69de29..6786da7 100644 --- a/src/mainboard/lenovo/x60/acpi/superio.asl +++ b/src/mainboard/lenovo/x60/acpi/superio.asl @@ -0,0 +1,34 @@ +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X60T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif + + Device (COMA) // Serial + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x3f8, 0x3f8, 0x01, 0x08) + IRQNoFlags () {4} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..5b4e37f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -127,8 +127,11 @@ chip northbridge/intel/i945 io 0x60 = 0x2f8 end - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 end device pnp 164e.7 on # GPIO diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index d1fcb7b..be39674 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -150,8 +150,13 @@ static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *curre static void mainboard_enable(device_t dev) { + device_t devwacom; dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X60T); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x60t/Kconfig b/src/mainboard/lenovo/x60t/Kconfig new file mode 100644 index 0000000..57c99ca --- /dev/null +++ b/src/mainboard/lenovo/x60t/Kconfig @@ -0,0 +1,10 @@ +if BOARD_LENOVO_X60T + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad X60 Tablet" + +endif diff --git a/src/mainboard/lenovo/x60t/board_info.txt b/src/mainboard/lenovo/x60t/board_info.txt new file mode 100644 index 0000000..6ecdbd5 --- /dev/null +++ b/src/mainboard/lenovo/x60t/board_info.txt @@ -0,0 +1,7 @@ +Board name: X60 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lenovo/x60

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Patch merged into coreboot/master: 2ee650f crossgcc: Update IASL to latest version (20140114)
by gerrit＠coreboot.org 14 Feb '14

14 Feb '14

the following patch was just integrated into master: commit 2ee650fb647c0cfad6db19cafdb62705d3035eb7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Feb 4 10:46:51 2014 -0600 crossgcc: Update IASL to latest version (20140114) Change-Id: I2450cad4a43907b8ca6d8f4d35932d7f451f71ea Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5116 for details. -gerrit

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Patch set updated for coreboot: 22576b3 lenovo/x60: Add X60T variant as separate port.
by Vladimir Serbinenko 14 Feb '14

14 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5113 -gerrit commit 22576b37642f84468668259992ca085567f26131 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Feb 4 15:01:04 2014 +0100 lenovo/x60: Add X60T variant as separate port. X60 and X60T differ only by presence of wacom table on serial port on internal SuperI/O. However detecting this difference would cost in boot time and code complexity as detecting requires an attempt to communicate with wacom over slow serial connection and waiting for it to wakeup. Since presence of wacom is a characterisitc of model and know to user at compile time, add it as separate mobo instead. Change-Id: If2e699cfa5d11f2cb2b9c254fc6fc71781dce228 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 6 ++++++ src/mainboard/lenovo/x60/Kconfig | 6 +++++- src/mainboard/lenovo/x60/acpi/superio.asl | 34 +++++++++++++++++++++++++++++++ src/mainboard/lenovo/x60/devicetree.cb | 7 +++++-- src/mainboard/lenovo/x60/mainboard.c | 5 +++++ src/mainboard/lenovo/x60t/Kconfig | 10 +++++++++ src/mainboard/lenovo/x60t/board_info.txt | 7 +++++++ 7 files changed, 72 insertions(+), 3 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..b16ef7d 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -12,6 +12,11 @@ config BOARD_LENOVO_X60 ThinkPad X60s (Model 1702, 1703) ThinkPad X60 (Model 1709) +config BOARD_LENOVO_X60T + bool "ThinkPad X60 Tablet" + help + Lenovo X60 convertible tablet + config BOARD_LENOVO_X201 bool "ThinkPad X201" help @@ -33,6 +38,7 @@ config BOARD_LENOVO_T60 endchoice source "src/mainboard/lenovo/x60/Kconfig" +source "src/mainboard/lenovo/x60t/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..36c00bc 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -1,4 +1,4 @@ -if BOARD_LENOVO_X60 +if BOARD_LENOVO_X60 || BOARD_LENOVO_X60T config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -39,10 +39,14 @@ config DCACHE_RAM_SIZE hex default 0x8000 +if BOARD_LENOVO_X60 + config MAINBOARD_PART_NUMBER string default "ThinkPad X60 / X60s" +endif + config MMCONF_BASE_ADDRESS hex default 0xf0000000 diff --git a/src/mainboard/lenovo/x60/acpi/superio.asl b/src/mainboard/lenovo/x60/acpi/superio.asl index e69de29..6786da7 100644 --- a/src/mainboard/lenovo/x60/acpi/superio.asl +++ b/src/mainboard/lenovo/x60/acpi/superio.asl @@ -0,0 +1,34 @@ +#if IS_ENABLED(CONFIG_BOARD_LENOVO_X60T) + Device (DTR) // Digitizer + { + Name(_HID, EISAID("WACF004")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x200, 0x200, 0x01, 0x08) + IRQNoFlags () {5} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } +#endif + + Device (COMA) // Serial + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x3f8, 0x3f8, 0x01, 0x08) + IRQNoFlags () {4} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..5b4e37f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -127,8 +127,11 @@ chip northbridge/intel/i945 io 0x60 = 0x2f8 end - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 end device pnp 164e.7 on # GPIO diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index d1fcb7b..be39674 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -150,8 +150,13 @@ static int mainboard_smbios_data(device_t dev, int *handle, unsigned long *curre static void mainboard_enable(device_t dev) { + device_t devwacom; dev->ops->init = mainboard_init; dev->ops->get_smbios_data = mainboard_smbios_data; + + devwacom = dev_find_slot_pnp (0x164e, 3); + if (devwacom) + devwacom->enabled = IS_ENABLED(CONFIG_BOARD_LENOVO_X60T); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x60t/Kconfig b/src/mainboard/lenovo/x60t/Kconfig new file mode 100644 index 0000000..57c99ca --- /dev/null +++ b/src/mainboard/lenovo/x60t/Kconfig @@ -0,0 +1,10 @@ +if BOARD_LENOVO_X60T + +# Dummy for abuild +#select ARCH_X86 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad X60 Tablet" + +endif diff --git a/src/mainboard/lenovo/x60t/board_info.txt b/src/mainboard/lenovo/x60t/board_info.txt new file mode 100644 index 0000000..6ecdbd5 --- /dev/null +++ b/src/mainboard/lenovo/x60t/board_info.txt @@ -0,0 +1,7 @@ +Board name: X60 Tablet +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Clone of: lenovo/x60

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Patch set updated for coreboot: 2b4ca9c libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 14 Feb '14

14 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit 2b4ca9c6f92f6eb67673cdca0c59202bc784db05 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 74 +++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..c7ef32d 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,76 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* + * Alignment-agnostic encode/decode bytestream to/from little/big endian. + */ + +static inline uint16_t be16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[0] << 8) | p[1]); +} + +static inline uint32_t be32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]); +} + +static inline uint16_t le16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static inline uint32_t le32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static inline void bebitenc(void *pp, uint32_t u, uint8_t b) +{ + uint8_t *p = (uint8_t *)pp; + int i; + + for(i=(b-1); i >= 0; i++) + p[i] = (u >> i*8) & 0xFF; +} + +static inline void be16enc(void *pp, uint16_t u) +{ + bebitenc(pp, u, 2); +} + +static inline void be32enc(void *pp, uint32_t u) +{ + bebitenc(pp, u, 4); +} + +static inline void lebitenc(void *pp, uint32_t u, uint8_t b) +{ + uint8_t *p = (uint8_t *)pp; + int i; + + for(i=0; i < b; i++) + p[i] = (u >> i*8) & 0xFF; +} + +static inline void le16enc(void *pp, uint16_t u) +{ + lebitenc(pp, u, 2); +} + +static inline void le32enc(void *pp, uint32_t u) +{ + lebitenc(pp, u, 4); +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +171,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

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Patch set updated for coreboot: eebd9af libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 14 Feb '14

14 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit eebd9af3b318164e606dfc9e4719db8c6b2866df Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 74 +++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..2eaddf6 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,76 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* + * Alignment-agnostic encode/decode bytestream to/from little/big endian. + */ + +static inline uint16_t be16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[0] << 8) | p[1]); +} + +static inline uint32_t be32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]); +} + +static inline uint16_t le16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static inline uint32_t le32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static inline void bebitenc(void *pp, uint32_t u, uint8_t b) +{ + uint8_t *p = (uint8_t *)pp; + int i; + + for(i=(b-1); i >= 0; i++) + p[i] = (u >> i*8) & 0xFF; +} + +static inline void be16enc(void *pp, uint16_t u) +{ + bebitenc(pp, u, 2); +} + +static inline void be32enc(void *pp, uint32_t u) +{ + bebitenc(pp, u, 4); +} + +static inline void lebitenc(void *pp, uint32_t u, uint8_t b) +{ + uint8_t *p = (uint8_t *)pp; + int i; + + for(i=0; i < b; i++) + p[i] = (u >> i*8) & 0xFF; +} + +static inline void le16enc(void *pp, uint16_t u) +{ + lebitenc(pp, u, 2); +} + +static inline void le32enc(void *pp, uint32_t u) +{ + lebitenc(pp, u, 4); +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +171,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

1 0

Patch set updated for coreboot: 5df5159 superio/nuvoton: Add support for Nuvoton NCT6779D
by Alec Ari 13 Feb '14

13 Feb '14

Alec Ari (neotheuser(a)ymail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4589 -gerrit commit 5df5159b24610dd950ac2c02cf2909f54b625d60 Author: Alec Ari <neotheuser(a)ymail.com> Date: Sun Dec 29 23:48:38 2013 -0600 superio/nuvoton: Add support for Nuvoton NCT6779D Adds initial support for the Nuvoton NCT6779D Super I/O Change-Id: I03b3c39e4409bd57e8c0759d9c3fdd160f0376d4 Signed-off-by: Alec Ari <neotheuser(a)ymail.com> --- src/superio/nuvoton/Kconfig | 2 + src/superio/nuvoton/Makefile.inc | 1 + src/superio/nuvoton/nct6779d/Makefile.inc | 23 ++++++++++ src/superio/nuvoton/nct6779d/early_serial.c | 45 +++++++++++++++++++ src/superio/nuvoton/nct6779d/nct6779d.h | 48 ++++++++++++++++++++ src/superio/nuvoton/nct6779d/superio.c | 68 +++++++++++++++++++++++++++++ 6 files changed, 187 insertions(+) diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig index 142738d..8bbfdb0 100644 --- a/src/superio/nuvoton/Kconfig +++ b/src/superio/nuvoton/Kconfig @@ -21,3 +21,5 @@ config SUPERIO_NUVOTON_WPCM450 bool config SUPERIO_NUVOTON_NCT5104D bool +config SUPERIO_NUVOTON_NCT6779D + bool diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index 18025c9..d115bac 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -19,3 +19,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d diff --git a/src/superio/nuvoton/nct6779d/Makefile.inc b/src/superio/nuvoton/nct6779d/Makefile.inc new file mode 100644 index 0000000..9b2ee9c --- /dev/null +++ b/src/superio/nuvoton/nct6779d/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Alec Ari (neotheuser(a)ymail.com) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += early_serial.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c + diff --git a/src/superio/nuvoton/nct6779d/early_serial.c b/src/superio/nuvoton/nct6779d/early_serial.c new file mode 100644 index 0000000..e33abbc --- /dev/null +++ b/src/superio/nuvoton/nct6779d/early_serial.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include "nct6779d.h" + +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +void nct6779d_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); +} diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h new file mode 100644 index 0000000..6013d87 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_NUVOTON_NCT6779D_NCT6779D_H +#define SUPERIO_NUVOTON_NCT6779D_NCT6779D_H + +#define NCT6779D_PAR 0x01 /* Parallel Port */ +#define NCT6779D_SP1 0x02 /* Com1 */ +#define NCT6779D_SP2 0x03 /* Com2 (UART B & IR) */ +#define NCT6779D_KBC 0x05 /* Keyboard Controller */ +#define NCT6779D_CIR 0x06 /* CIR */ +#define NCT6779D_HWMN 0x0b /* Hw-mon / Front panel LED */ + +#define NCT6779D_WDT_GPIO_V 0x08 +#define NCT6779D_GPIO_ALL_V 0x09 + +#define NCT6779D_WDT1 ((0 << 8) | NCT6779D_WDT_GPIO_V) +#define NCT6779D_GPIO0 ((1 << 8) | NCT6779D_WDT_GPIO_V) + +#define NCT6779D_GPIO1 ((1 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO2 ((2 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO3 ((3 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO4 ((4 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO5 ((5 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO6 ((6 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO7 ((7 << 8) | NCT6779D_GPIO_ALL_V) +#define NCT6779D_GPIO8 ((0 << 8) | NCT6779D_GPIO_ALL_V) + +void nct6779d_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_NUVOTON_NCT6779D_NCT6779D_H */ diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c new file mode 100644 index 0000000..eb15905 --- /dev/null +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <stdlib.h> +#include "nct6779d.h" + +static void nct6779d_init(device_t dev) +{ +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct6779d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, NCT6779D_PAR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x07f8, 0}, }, + { &ops, NCT6779D_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, {0x07f8, 0}, }, + { &ops, NCT6779D_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, {0x07f8, 0}, }, + { &ops, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, {0x07f8, 0}, }, + { &ops, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, {0x07f8, 0}, }, + { &ops, NCT6779D_HWMN, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1, {0x07f8, 0}, }, + { &ops, NCT6779D_WDT1, PNP_IO0 | PNP_MSC0 | PNP_MSC1, {0x07f8, 0}, }, + { &ops, NCT6779D_GPIO0, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO1, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO2, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO4, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO5, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO6, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO7, PNP_EN | PNP_MSC0 | PNP_MSC1, }, + { &ops, NCT6779D_GPIO8, PNP_EN | PNP_MSC0 | PNP_MSC1, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct6779d_ops = { + CHIP_NAME("NUVOTON NCT6779D Super I/O") + .enable_dev = enable_dev, +};

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New patch to review for coreboot: bb38049 google/rambi: Re-add option to hardcode location of spd.bin
by Alexandru Gagniuc 13 Feb '14

13 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5219 -gerrit commit bb3804969974c2df0d7be71b831cd9b9606a9f8a Author: Alexandru Gagniuc <mr.nuk.me(a)gmail.com> Date: Thu Feb 13 00:16:56 2014 +0100 google/rambi: Re-add option to hardcode location of spd.bin This is a partial revert of: * 76e25b6 google boards: Do not hardcode location of spd.bin Hardcoding the location of spd.bin is apparently useful during manufacturing. Exactly how and why is irrelevant for coreboot master, but we try to be a good citizen and accomodate all reasonable use cases. As such, allow the location of spd.bin to be specified when running a CHROMEOS build. Change-Id: Ic1412245125dd4241728e10fb340d801d86c5dcf Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/rambi/Kconfig | 7 +++++++ src/mainboard/google/rambi/spd/Makefile.inc | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1748862..d316feb 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -31,4 +31,11 @@ config HAVE_ME_BIN bool default n +# Positioning spd.bin at a fixed address is useful during manufacturing, but +# offers no benefit otherwise, hence only present the option with ChromeOS +config SPD_CBFS_ADDRESS + depends on CHROMEOS + hex "Location of SPD in CBFS" + default 0xfffec000 + endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc index 36f4b66..0ec7b39 100644 --- a/src/mainboard/google/rambi/spd/Makefile.inc +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -43,3 +43,7 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +# See comment in rambi/Kconfig for why this is done like this +ifeq ($(CONFIG_CHROMEOS),y) +spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS) +endif

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New patch to review for coreboot: 97e93b2 google/rambi: Do not select CHROMEOS in Kconfig
by Alexandru Gagniuc 13 Feb '14

13 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5218 -gerrit commit 97e93b22b1f51f86c0841667549e256158724fc2 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Feb 13 14:33:08 2014 -0600 google/rambi: Do not select CHROMEOS in Kconfig CHROMEOS is the meant to be selected by the user. The correct variable for a mainboard to select is MAINBOARD_HAS_CHROMEOS. This will then default to a CHROMEOS build, but when the mainboard selects CHROMEOS, the user can no longer disable CHROMEOS. Change-Id: I78fb15a0a9fef733e2de064d6c09cf774b7bce78 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/rambi/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 292d321..1748862 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS - select CHROMEOS config MAINBOARD_DIR string

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Patch set updated for coreboot: a3279df google/rambi: Re-add option to hardcode location of spd.bin
by Alexandru Gagniuc 13 Feb '14

13 Feb '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5212 -gerrit commit a3279df5bbb61cfbad44614a8028e270adf12849 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Feb 13 00:16:56 2014 +0100 google/rambi: Re-add option to hardcode location of spd.bin This is a partial revert of: * 76e25b6 google boards: Do not hardcode location of spd.bin Hardcoding the location of spd.bin is apparently useful during manufacturing. Exactly how and why is irrelevant for coreboot master, but we try to be a good citizen and accomodate all reasonable use cases. As such, allow the location of spd.bin to be specified when running a CHROMEOS build. Change-Id: I6ca0238e9a11566ec1129a16b5cd507d9951cbd3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/google/rambi/Kconfig | 7 +++++++ src/mainboard/google/rambi/spd/Makefile.inc | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1748862..d316feb 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -31,4 +31,11 @@ config HAVE_ME_BIN bool default n +# Positioning spd.bin at a fixed address is useful during manufacturing, but +# offers no benefit otherwise, hence only present the option with ChromeOS +config SPD_CBFS_ADDRESS + depends on CHROMEOS + hex "Location of SPD in CBFS" + default 0xfffec000 + endif # BOARD_INTEL_BAYLEYBAY diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc index 36f4b66..0ec7b39 100644 --- a/src/mainboard/google/rambi/spd/Makefile.inc +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -43,3 +43,7 @@ $(SPD_BIN): $(SPD_DEPS) cbfs-files-y += spd.bin spd.bin-file := $(SPD_BIN) spd.bin-type := 0xab +# See comment in rambi/Kconfig for why this is done like this +ifeq ($(CONFIG_CHROMEOS),y) +spd.bin-position := $(CONFIG_SPD_CBFS_ADDRESS) +endif

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coreboot-gerrit February 2014