coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: f85e3a1 pl011 UART: Move under drivers/uart
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5162 -gerrit commit f85e3a15928d3755cbc3f8876d21e0d4e1850bfc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 10 23:21:14 2014 +0200 pl011 UART: Move under drivers/uart Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/Kconfig | 4 ++ src/drivers/uart/Makefile.inc | 9 ++++ src/drivers/uart/pl011.c | 51 +++++++++++++++++++++ src/mainboard/emulation/qemu-armv7/Kconfig | 8 +++- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 -- src/mainboard/emulation/qemu-armv7/uart.c | 60 ------------------------- 6 files changed, 70 insertions(+), 66 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index c1c3090..5c9a9d1 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -12,3 +12,7 @@ config HAVE_UART_SPECIAL bool default n +config DRIVERS_UART_PL011 + bool + default n + select HAVE_UART_SPECIAL diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc new file mode 100644 index 0000000..9a8121e --- /dev/null +++ b/src/drivers/uart/Makefile.inc @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) + +ifeq ($(CONFIG_DRIVERS_UART_PL011),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c +romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c +ramstage-y += pl011.c +endif + +endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c new file mode 100644 index 0000000..a880c77 --- /dev/null +++ b/src/drivers/uart/pl011.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/uart.h> + +static const uint32_t uart_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + +static void pl011_uart_tx_byte(unsigned int *tx_fifo, unsigned char data) +{ + *tx_fifo = (unsigned int)data; +} + +#if !defined(__PRE_RAM__) + +static const struct console_driver pl011_uart_console __console = { + .init = pl011_init_dev, + .tx_byte = pl011_uart_tx_byte, + .tx_flush = pl011_uart_tx_flush, +}; + +uint32_t uartmem_getbaseaddr(void) +{ + return VEXPRESS_UART0_IO_ADDRESS; +} +#else +void uart_init(void) +{ +} + +void uart_tx_byte(unsigned char data) +{ + pl011_uart_tx_byte((unsigned int *)uart_base, data); +} + +void uart_tx_flush(void) +{ +} +#endif diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 9ab9767..edba627 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -25,8 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 - select HAVE_UART_MEMORY_MAPPED - select HAVE_UART_SPECIAL + select DRIVERS_UART_PL011 select BOARD_ROMSIZE_KB_4096 config MAINBOARD_DIR @@ -49,6 +48,11 @@ config DRAM_SIZE_MB int default 1024 +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x10009000 + # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index 431d9ab..d15495f 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,7 +21,3 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c - -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -ramstage-y += uart.c diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c deleted file mode 100644 index 0be1cf9..0000000 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <console/uart.h> - -#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) - -static void pl011_init_dev(void) { -} - -static void pl011_uart_tx_byte(unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *)VEXPRESS_UART0_IO_ADDRESS; - - *uart0_address = (unsigned int)data; -} - -static void pl011_uart_tx_flush(void) { -} - -#if !defined(__PRE_RAM__) - -static const struct console_driver pl011_uart_console __console = { - .init = pl011_init_dev, - .tx_byte = pl011_uart_tx_byte, - .tx_flush = pl011_uart_tx_flush, -}; - -uint32_t uartmem_getbaseaddr(void) -{ - return VEXPRESS_UART0_IO_ADDRESS; -} -#else -void uart_init(void) -{ - pl011_init_dev(); -} - -void uart_tx_byte(unsigned char data) -{ - pl011_uart_tx_byte(data); -} - -void uart_tx_flush(void) { - pl011_uart_tx_flush(); -} -#endif

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Patch set updated for coreboot: de765d9 console: Fix includes
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5232 -gerrit commit de765d9c48ce5cb60595b21fa7d4e6a76bde455c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 06:11:01 2014 +0200 console: Fix includes Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 1 + src/arch/x86/lib/romstage_console.c | 14 +++++--------- src/console/console.c | 6 ++++++ src/include/console/console.h | 16 ---------------- src/lib/cbmem.c | 1 + src/lib/cbmem_console.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + 7 files changed, 15 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index e517428..0f0e017 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/ne2k.h> /* __PRE_RAM__ */ /* Using a global varible can cause problems when we reset the stack diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4ef702f..4981f39 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -19,20 +19,16 @@ #include <smp/node.h> #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> +#include <console/usb.h> +#include <console/ne2k.h> +#include <console/spkmodem.h> #include <console/vtxprintf.h> #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif -#if CONFIG_USBDEBUG -#include <console/usb.h> -#endif -#if CONFIG_CONSOLE_NE2K -#include <console/ne2k.h> -#endif -#if CONFIG_SPKMODEM -#include <console/spkmodem.h> -#endif void console_tx_byte(unsigned char byte) { diff --git a/src/console/console.c b/src/console/console.c index 081113c..334e140 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -18,6 +18,12 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> +#include <console/usb.h> +#include <console/ne2k.h> +#include <console/spkmodem.h> + #include <build.h> #include <arch/hlt.h> #include <arch/io.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 4df8cb6..a089729 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,22 +24,6 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL -#include <console/uart.h> -#endif -#if CONFIG_USBDEBUG && !defined(__ROMCC__) -#include <console/usb.h> -#endif -#if CONFIG_CONSOLE_NE2K -#include <console/ne2k.h> -#endif -#if CONFIG_CONSOLE_CBMEM -#include <console/cbmem_console.h> -#endif -#if CONFIG_SPKMODEM -#include <console/spkmodem.h> -#endif - #ifndef __PRE_RAM__ unsigned char console_rx_byte(void); int console_tst_byte(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index d97f6af..3fea49a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,6 +23,7 @@ #include <cbmem.h> #include <boot/coreboot_tables.h> #include <console/console.h> +#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 83d44e3..9d5419a 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> #include <cbmem.h> #include <arch/early_variables.h> #include <string.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b9c3839..bfb4033 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <console/usb.h> #include <string.h> #include <arch/hlt.h> #include <arch/io.h>

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Patch set updated for coreboot: e3665be pl011 UART: Move under drivers/uart
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5162 -gerrit commit e3665be2e71f9678c2f4ec6ff27546495b2878f8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 10 23:21:14 2014 +0200 pl011 UART: Move under drivers/uart Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/Kconfig | 4 ++ src/drivers/uart/Makefile.inc | 9 ++++ src/drivers/uart/pl011.c | 51 +++++++++++++++++++++ src/mainboard/emulation/qemu-armv7/Kconfig | 8 +++- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 -- src/mainboard/emulation/qemu-armv7/uart.c | 60 ------------------------- 6 files changed, 70 insertions(+), 66 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index c1c3090..5c9a9d1 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -12,3 +12,7 @@ config HAVE_UART_SPECIAL bool default n +config DRIVERS_UART_PL011 + bool + default n + select HAVE_UART_SPECIAL diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc new file mode 100644 index 0000000..9a8121e --- /dev/null +++ b/src/drivers/uart/Makefile.inc @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) + +ifeq ($(CONFIG_DRIVERS_UART_PL011),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c +romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c +ramstage-y += pl011.c +endif + +endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c new file mode 100644 index 0000000..a880c77 --- /dev/null +++ b/src/drivers/uart/pl011.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <console/uart.h> + +static const uint32_t uart_base = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + +static void pl011_uart_tx_byte(unsigned int *tx_fifo, unsigned char data) +{ + *tx_fifo = (unsigned int)data; +} + +#if !defined(__PRE_RAM__) + +static const struct console_driver pl011_uart_console __console = { + .init = pl011_init_dev, + .tx_byte = pl011_uart_tx_byte, + .tx_flush = pl011_uart_tx_flush, +}; + +uint32_t uartmem_getbaseaddr(void) +{ + return VEXPRESS_UART0_IO_ADDRESS; +} +#else +void uart_init(void) +{ +} + +void uart_tx_byte(unsigned char data) +{ + pl011_uart_tx_byte((unsigned int *)uart_base, data); +} + +void uart_tx_flush(void) +{ +} +#endif diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 9ab9767..edba627 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -25,8 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 - select HAVE_UART_MEMORY_MAPPED - select HAVE_UART_SPECIAL + select DRIVERS_UART_PL011 select BOARD_ROMSIZE_KB_4096 config MAINBOARD_DIR @@ -49,6 +48,11 @@ config DRAM_SIZE_MB int default 1024 +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x10009000 + # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index 431d9ab..d15495f 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,7 +21,3 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c - -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -ramstage-y += uart.c diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c deleted file mode 100644 index 0be1cf9..0000000 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <console/uart.h> - -#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) - -static void pl011_init_dev(void) { -} - -static void pl011_uart_tx_byte(unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *)VEXPRESS_UART0_IO_ADDRESS; - - *uart0_address = (unsigned int)data; -} - -static void pl011_uart_tx_flush(void) { -} - -#if !defined(__PRE_RAM__) - -static const struct console_driver pl011_uart_console __console = { - .init = pl011_init_dev, - .tx_byte = pl011_uart_tx_byte, - .tx_flush = pl011_uart_tx_flush, -}; - -uint32_t uartmem_getbaseaddr(void) -{ - return VEXPRESS_UART0_IO_ADDRESS; -} -#else -void uart_init(void) -{ - pl011_init_dev(); -} - -void uart_tx_byte(unsigned char data) -{ - pl011_uart_tx_byte(data); -} - -void uart_tx_flush(void) { - pl011_uart_tx_flush(); -} -#endif

1 0

Patch set updated for coreboot: bff38b8 console: Move generic UART header
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5231 -gerrit commit bff38b83fc08a5273ff25c7d2a4e92086f2486ee Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 09:20:19 2014 +0200 console: Move generic UART header Change-Id: I3ae773a32e65e4645919998bc08a3a0d0f686121 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/util.c | 2 +- src/cpu/allwinner/a10/uart_console.c | 2 +- src/cpu/samsung/exynos5250/uart.c | 2 +- src/cpu/samsung/exynos5420/uart.c | 2 +- src/cpu/ti/am335x/uart.c | 2 +- src/include/console/console.h | 2 +- src/include/console/uart.h | 35 ++++++++++++++++++++ src/include/uart.h | 44 -------------------------- src/include/uart8250.h | 7 ++-- src/mainboard/cubietech/cubieboard/bootblock.c | 2 +- src/mainboard/emulation/qemu-armv7/uart.c | 2 +- src/mainboard/ti/beaglebone/bootblock.c | 2 +- 12 files changed, 46 insertions(+), 58 deletions(-) diff --git a/src/console/util.c b/src/console/util.c index 405657d..741a0d4 100644 --- a/src/console/util.c +++ b/src/console/util.c @@ -16,7 +16,7 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> #if CONFIG_USE_OPTION_TABLE #include <option.h> #include "option_table.h" diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index 58930dd..94ab7f7 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -8,7 +8,7 @@ #include <config.h> #include <types.h> -#include <uart.h> +#include <console/uart.h> #include <arch/io.h> #include <console/console.h> diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index dbf7202..80e9f4e 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -18,7 +18,7 @@ */ #include <console/console.h> /* for __console definition */ -#include <uart.h> +#include <console/uart.h> #include <arch/io.h> #include "uart.h" #include "clk.h" diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index c5c8a8c..ac01488 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -18,7 +18,7 @@ */ #include <console/console.h> /* for __console definition */ -#include <uart.h> +#include <console/uart.h> #include <arch/io.h> #include "uart.h" #include "clk.h" diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index bd2ff44..448b1c2 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -18,7 +18,7 @@ #include <config.h> #include <types.h> -#include <uart.h> +#include <console/uart.h> #include <arch/io.h> #include <console/console.h> /* for __console definition */ diff --git a/src/include/console/console.h b/src/include/console/console.h index 451a46a..4df8cb6 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -25,7 +25,7 @@ #include <console/post_codes.h> #if CONFIG_CONSOLE_SERIAL -#include <uart.h> +#include <console/uart.h> #endif #if CONFIG_USBDEBUG && !defined(__ROMCC__) #include <console/usb.h> diff --git a/src/include/console/uart.h b/src/include/console/uart.h new file mode 100644 index 0000000..6cd3beb --- /dev/null +++ b/src/include/console/uart.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CONSOLE_UART_H +#define CONSOLE_UART_H + +void uart_init(void); +void uart_tx_byte(unsigned char data); +void uart_tx_flush(void); +unsigned char uart_rx_byte(void); + + +unsigned uart_divisor(unsigned basefreq); +unsigned uart_platform_divisor(void); + + +uint32_t uartmem_getbaseaddr(void); + +#endif /* CONSOLE_UART_H */ diff --git a/src/include/uart.h b/src/include/uart.h deleted file mode 100644 index 9601bfa..0000000 --- a/src/include/uart.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* madness. Uarts are a mess. If you include this file, it - * includes ALL uart implementations which may be needed. - * No need to include them separately, and include this file FIRST. - * At least one (but at most one) of the files needs to define - * uart_init(). - */ -#ifndef UART_H -#define UART_H - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - -#if CONFIG_CONSOLE_SERIAL_UART -unsigned char uart_rx_byte(void); -void uart_tx_byte(unsigned char data); -void uart_tx_flush(void); -void uart_init(void); -#endif - -#if CONFIG_HAVE_UART_MEMORY_MAPPED -uint32_t uartmem_getbaseaddr(void); -#endif - -#endif /* UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 83b4535..15cf3b4 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -111,8 +111,8 @@ #error Bad ttyS0 baud rate #endif -unsigned uart_platform_divisor(void); -unsigned uart_divisor(unsigned basefreq); +/* Quick hack to build. */ +#include <console/uart.h> #if CONFIG_CONSOLE_SERIAL8250 unsigned char uart8250_rx_byte(unsigned base_port); @@ -123,7 +123,6 @@ void uart8250_tx_flush(unsigned base_port); * have three different sets of uart code, so it's an improvement. */ void uart8250_init(unsigned base_port, unsigned divisor); -void uart_init(void); #endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); @@ -139,8 +138,6 @@ u32 uart_mem_init(void); #if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE /* and special init for OXPCIe based cards */ extern int oxford_oxpcie_present; - -void oxford_init(void); #endif #endif diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index 2e5929c..e22c1d8 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -7,7 +7,7 @@ */ #include <arch/io.h> -#include <uart.h> +#include <console/uart.h> #include <console/console.h> #include <delay.h> #include <cpu/allwinner/a10/gpio.h> diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c index dfe5d0a..0be1cf9 100644 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ b/src/mainboard/emulation/qemu-armv7/uart.c @@ -14,7 +14,7 @@ */ #include <console/console.h> -#include <uart.h> +#include <console/uart.h> #define VEXPRESS_UART0_IO_ADDRESS (0x10009000) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index dd46040..9e0a62e 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -19,7 +19,7 @@ #include <arch/io.h> #include <types.h> -#include <uart.h> +#include <console/uart.h> #include <console/console.h> #include <cpu/ti/am335x/pinmux.h>

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New patch to review for coreboot: 5f3e48b OxPCIe uart: Split PCI bridge control
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237 -gerrit commit 5f3e48beb341bb43f1bf00660370d83bb697b387 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 12:45:09 2014 +0200 OxPCIe uart: Split PCI bridge control None of the bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid but originate from lumpy and/or stumpy devices. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_early.c | 45 ++++++++++++++++++ src/drivers/Kconfig | 1 + src/drivers/oxford/oxpcie/Kconfig | 64 ++----------------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 81 ++++++-------------------------- src/drivers/pci/Kconfig | 31 ++++++++++++ src/drivers/pci/pci_early.c | 58 +++++++++++++++++++++++ src/include/device/pci.h | 6 +++ src/southbridge/intel/bd82x6x/Kconfig | 20 ++++++++ 8 files changed, 179 insertions(+), 127 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index c15a4d0..d7c48de 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2011 Google Inc + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -66,3 +68,46 @@ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } + +void pci_bridge_reset_secondary(device_t p2p_bridge) +{ + u16 reg16; + /* Disable all access through bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + + /* First we reset the secondary bus. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +{ + /* Disable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + /* Enable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); +} + +void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base) +{ + /* MMIO window behind the bridge. */ + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + ((base & 0xffff0000) | ((base >> 16) & 0xff00))); + + /* Enable memory access through bridge */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); +} diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 01bed21..5d9a801 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -32,6 +32,7 @@ source src/drivers/parade/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig endif +source src/drivers/pci/Kconfig source src/drivers/realtek/Kconfig source src/drivers/sil/Kconfig source src/drivers/spi/Kconfig diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 899a153..bd5001c 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,68 +1,10 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n + depends on PCI select HAVE_UART_MEMORY_MAPPED + select EARLY_PCI_BRIDGE help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 will work. - NOTE: Right now you have to set the base address of your OXPCIe952 - card to exactly the value that the device allocator would set them - later on, or serial console functionality will stop as soon as the - resource allocator assigns a new base address to the device. - -config OXFORD_OXPCIE_BRIDGE_BUS - hex "OXPCIe's PCIe bridge bus number" - default 0x0 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_DEVICE - hex "OXPCIe's PCIe bridge device number" - default 0x1c - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_FUNCTION - hex "OXPCIe's PCIe bridge function number" - default 0x2 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_SUBORDINATE - hex "OXPCIe's PCIe bridge subordinate bus" - default 0x3 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BASE_ADDRESS - hex "Base address for rom stage console" - default 0xe0400000 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up a temporary address - for the OXPCIe952 controller. - + 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index b2004c4..122f3a4 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -25,94 +25,43 @@ #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; -#define PCIE_BRIDGE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) - -#define OXPCIE_DEVICE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) - -#define OXPCIE_DEVICE_3 \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) - -static void oxpcie_init_bridge(void) +static int oxpcie_probe(u8 bus, u8 dev, u32 mmio_base, u16 io_base) { - u16 reg16; - - /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ - - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Set up subordinate bus number */ - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); + pci_devfn_t device = PCI_DEV(bus, dev, 0); - /* Memory window for the OXPCIe952 card */ - // XXX is the calculation of base and limit correct? - pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); - - /* Enable memory access through bridge */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - - u32 timeout = 20000; // Timeout in 10s of microseconds. - u32 id = 0; - for (;;) { - id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); - if (!timeout-- || (id != 0 && id != 0xffffffff)) - break; - udelay(10); - } - - u32 device = OXPCIE_DEVICE; /* unknown default */ + u32 id = pci_read_config32(device, PCI_VENDOR_ID); switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI */ + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and * function 3 is the serial port. So let's go look for * the UART. */ - id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; - device = OXPCIE_DEVICE_3; + return -1; break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ case 0xc1581415: /* e.g. Startech MPEX2S952 */ - device = OXPCIE_DEVICE; break; default: /* No UART here. */ - return; + return -1; } /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); + return 0; } static int oxpcie_uart_active(void) @@ -149,6 +98,6 @@ uint32_t uartmem_getbaseaddr(void) void oxford_init(void) { - oxpcie_init_bridge(); + pci_bridge_early_init(&oxpcie_probe); uart_init(); } diff --git a/src/drivers/pci/Kconfig b/src/drivers/pci/Kconfig new file mode 100644 index 0000000..bb6d2bf --- /dev/null +++ b/src/drivers/pci/Kconfig @@ -0,0 +1,31 @@ +config EARLY_PCI_BRIDGE + bool "Early PCI bridge" + depends on PCI + default n + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. + + This option enables static configuration for a single pre-defined + PCI bridge function on bus 0. + +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex "bridge device" + default 0x0 + +config EARLY_PCI_BRIDGE_FUNCTION + hex "bridge function" + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex "MMIO window base" + default 0x0 + +config EARLY_PCI_BRIDGE_SECONDARY + hex "Early PCI bridge secondary bus" + default 0x0 + +endif # EARLY_PCI_BRIDGE diff --git a/src/drivers/pci/pci_early.c b/src/drivers/pci/pci_early.c new file mode 100644 index 0000000..6e1a6f7 --- /dev/null +++ b/src/drivers/pci/pci_early.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_def.h> + + +{ + /* No PCI-to-PCI bridges are enabled yet, so the one we try to + * configure must have its primary on bus 0. + */ + pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + u8 bus = CONFIG_EARLY_PCI_BRIDGE_SECONDARY; + + pci_bridge_reset_secondary(p2p_bridge); + pci_bridge_set_secondary(p2p_bridge, bus); + + u3 timeout = 20000; // Timeout in 10s of microseconds. + u32 id = 0; + for (;;) { + id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + if (!timeout-- || (id != 0 && id != 0xffffffff)) + break; + udelay(10); + } + + ret = probe(bus, dev, mmio_base, io_base); + + /* Enable both MMIO and IO window with static allocation + * if we found any suitable device behind bridge. + */ + pci_bridge_enable_mmio(p2p_bridge, base, limit); + + /* Resource allocator will reconfigure bridges and secondary bus + * number may change. Early device must not use config transactions + * from here on. + */ + pci_bridge_set_secondary(p2p_bridge, 0); +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 29d988f..881c2ac 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -98,6 +98,12 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } +#else + +void pci_bridge_reset_secondary(device_t p2p_bridge); +void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base); +void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary); + #endif /* ! __SIMPLE_DEVICE__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 9cfa5d5..69c1fc9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,6 +41,26 @@ config EHCI_BAR hex default 0xfef00000 +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + default 0xe0400000 + +config EARLY_PCI_BRIDGE_SECONDARY + hex + default 0x3 + +endif + config DRAM_RESET_GATE_GPIO int default 60

1 0

New patch to review for coreboot: 888cc0b uart8250: Move under drivers/uart
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5236 -gerrit commit 888cc0b821d7f5d21d311b07bf0591baa1c3a157 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 30 15:45:16 2014 +0200 uart8250: Move under drivers/uart Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 2 +- src/drivers/uart/Makefile.inc | 12 ++++ src/drivers/uart/uart8250io.c | 125 ++++++++++++++++++++++++++++++++++++ src/drivers/uart/uart8250mem.c | 135 +++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 4 -- src/lib/uart8250.c | 125 ------------------------------------ src/lib/uart8250mem.c | 135 --------------------------------------- 7 files changed, 273 insertions(+), 265 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 5a88146..5b88a98 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -33,7 +33,7 @@ #include <console/util.c> #if CONFIG_CONSOLE_SERIAL8250 -#include "lib/uart8250.c" +#include "drivers/uart/uart8250io.c" #endif #if CONFIG_CONSOLE_NE2K #include "drivers/net/ne2k.c" diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 9a8121e..aec6a58 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,3 +1,15 @@ +ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +romstage-y += uart8250io.c +ramstage-y += uart8250io.c +smm-$(CONFIG_DEBUG_SMI) += uart8250io.c +endif + +ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +romstage-y += uart8250mem.c +ramstage-y += uart8250mem.c +smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c +endif + ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) ifeq ($(CONFIG_DRIVERS_UART_PL011),y) diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c new file mode 100644 index 0000000..ecd77b7 --- /dev/null +++ b/src/drivers/uart/uart8250io.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <trace.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static inline int uart8250_can_tx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_THRE; +} + +static inline void uart8250_wait_to_tx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_tx_byte(base_port)); +} + +static inline void uart8250_wait_until_sent(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); +} + +static void uart8250_tx_byte(unsigned base_port, unsigned char data) +{ + uart8250_wait_to_tx_byte(base_port); + outb(data, base_port + UART_TBR); +} + +static void uart8250_tx_flush(unsigned base_port) +{ + uart8250_wait_until_sent(base_port); +} + +static int uart8250_can_rx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_rx_byte(base_port)); + + if (i) + return inb(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_init(unsigned base_port, unsigned divisor) +{ + DISABLE_TRACE; + /* Disable interrupts */ + outb(0x0, base_port + UART_IER); + /* Enable FIFOs */ + outb(UART_FCR_FIFO_EN, base_port + UART_FCR); + + /* assert DTR and RTS so the other end is happy */ + outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); + + /* DLAB on */ + outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + outb(divisor & 0xFF, base_port + UART_DLL); + outb((divisor >> 8) & 0xFF, base_port + UART_DLM); + + /* Set to 3 for 8N1 */ + outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); + ENABLE_TRACE; +} + +static const unsigned base = CONFIG_TTYS0_BASE; + +void uart_init(void) +{ + unsigned int div = uart_divisor(115200); + uart8250_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(base); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(base); +} diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c new file mode 100644 index 0000000..210b9a8 --- /dev/null +++ b/src/drivers/uart/uart8250mem.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <delay.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static inline int uart8250_mem_can_tx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_THRE; +} + +static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_tx_byte(base_port)) + udelay(1); +} + +static inline void uart8250_mem_wait_until_sent(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) + udelay(1); +} + +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +{ + uart8250_mem_wait_to_tx_byte(base_port); + write8(base_port + UART_TBR, data); +} + +static void uart8250_mem_tx_flush(unsigned base_port) +{ + uart8250_mem_wait_until_sent(base_port); +} + +static int uart8250_mem_can_rx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_mem_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_rx_byte(base_port)) + udelay(1); + if (i) + return read8(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_mem_init(unsigned base_port, unsigned divisor) +{ + /* Disable interrupts */ + write8(base_port + UART_IER, 0x0); + /* Enable FIFOs */ + write8(base_port + UART_FCR, UART_FCR_FIFO_EN); + + /* Assert DTR and RTS so the other end is happy */ + write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); + + /* DLAB on */ + write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + write8(base_port + UART_DLL, divisor & 0xFF); + write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); + + /* Set to 3 for 8N1 */ + write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); +} + + +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} + +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 076bdd7..941c0ba 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -45,8 +45,6 @@ romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -86,8 +84,6 @@ ramstage-y += stack.c ramstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += clog2.c romstage-y += clog2.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c deleted file mode 100644 index 75caa06..0000000 --- a/src/lib/uart8250.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <trace.h> -#include "drivers/uart/uart8250reg.h" - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - * - * Estimated that inb() from UART takes 1 microsecond. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static inline int uart8250_can_tx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_THRE; -} - -static inline void uart8250_wait_to_tx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_tx_byte(base_port)); -} - -static inline void uart8250_wait_until_sent(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); -} - -static void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_wait_to_tx_byte(base_port); - outb(data, base_port + UART_TBR); -} - -static void uart8250_tx_flush(unsigned base_port) -{ - uart8250_wait_until_sent(base_port); -} - -static int uart8250_can_rx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_rx_byte(base_port)); - - if (i) - return inb(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_init(unsigned base_port, unsigned divisor) -{ - DISABLE_TRACE; - /* Disable interrupts */ - outb(0x0, base_port + UART_IER); - /* Enable FIFOs */ - outb(UART_FCR_FIFO_EN, base_port + UART_FCR); - - /* assert DTR and RTS so the other end is happy */ - outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); - - /* DLAB on */ - outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - outb(divisor & 0xFF, base_port + UART_DLL); - outb((divisor >> 8) & 0xFF, base_port + UART_DLM); - - /* Set to 3 for 8N1 */ - outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); - ENABLE_TRACE; -} - -static const unsigned base = CONFIG_TTYS0_BASE; - -void uart_init(void) -{ - unsigned int div = uart_divisor(115200); - uart8250_init(base, div); -} - -void uart_tx_byte(unsigned char data) -{ - uart8250_tx_byte(base, data); -} - -unsigned char uart_rx_byte(void) -{ - return uart8250_rx_byte(base); -} - -void uart_tx_flush(void) -{ - uart8250_tx_flush(base); -} diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c deleted file mode 100644 index 3540c4b..0000000 --- a/src/lib/uart8250mem.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <delay.h> -#include "drivers/uart/uart8250reg.h" - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static inline int uart8250_mem_can_tx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_THRE; -} - -static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); -} - -static inline void uart8250_mem_wait_until_sent(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) - udelay(1); -} - -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_mem_wait_to_tx_byte(base_port); - write8(base_port + UART_TBR, data); -} - -static void uart8250_mem_tx_flush(unsigned base_port) -{ - uart8250_mem_wait_until_sent(base_port); -} - -static int uart8250_mem_can_rx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read8(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned base_port, unsigned divisor) -{ - /* Disable interrupts */ - write8(base_port + UART_IER, 0x0); - /* Enable FIFOs */ - write8(base_port + UART_FCR, UART_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); - - /* DLAB on */ - write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - write8(base_port + UART_DLL, divisor & 0xFF); - write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); -} - - -void uart_init(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - - unsigned div = uart_platform_divisor(); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(unsigned char data) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_byte(base, data); -} - -unsigned char uart_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0xff; - return uart8250_mem_rx_byte(base); -} - -void uart_tx_flush(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_flush(base); -}

1 0

New patch to review for coreboot: 500cbda uart8250mem: Unify calls with generic UART
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5235 -gerrit commit 500cbda84801acd2fcee103230d600fe1c18f932 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 10:19:23 2014 +0200 uart8250mem: Unify calls with generic UART Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 11 +----- src/console/uart8250mem_console.c | 30 ++++---------- src/drivers/oxford/oxpcie/oxpcie.c | 3 +- src/drivers/oxford/oxpcie/oxpcie_early.c | 48 +++++++++++++++++------ src/include/console/uart.h | 5 ++- src/include/uart8250.h | 53 ------------------------- src/lib/uart8250mem.c | 67 ++++++++++++++++---------------- 7 files changed, 86 insertions(+), 131 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 89d7f82..6566b2f 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,20 +26,13 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - void console_tx_byte(unsigned char byte) { if (byte == '\n') console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_byte(byte); @@ -61,7 +54,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_flush(); diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index 3833e47..7e52aed 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -18,47 +18,31 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> -static u32 uart_bar = 0; - -void uartmem_init(void) -{ - uart_bar = uart_mem_init(); -} - -u32 uartmem_getbaseaddr(void) +static void uartmem_init(void) { - return uart_bar; + uart_init(); } static void uartmem_tx_byte(unsigned char data) { - if (!uart_bar) - return; - - uart8250_mem_tx_byte(uart_bar, data); + uart_tx_byte(data); } static void uartmem_tx_flush(void) { - uart8250_mem_tx_flush(uart_bar); + uart_tx_flush(); } static unsigned char uartmem_rx_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_rx_byte(uart_bar); + return uart_rx_byte(); } static int uartmem_tst_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_can_rx_byte(uart_bar); + return uart_can_rx_byte(); } static const struct console_driver uart8250mem_console __console = { diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index f719fc7..0b9081f 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -48,7 +48,8 @@ static void oxford_oxpcie_set_resources(struct device *dev) #if CONFIG_CONSOLE_SERIAL8250MEM /* Re-initialize OXPCIe base address after set_resources */ - uartmem_init(); + u32 mmio_base = pci_read_config32(device, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); #endif } diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 693c1e9..b2004c4 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -21,9 +21,13 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> -#include <uart8250.h> +#include <console/uart.h> #include <device/pci_def.h> +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; + #define PCIE_BRIDGE \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ @@ -35,13 +39,9 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) -#if defined(__PRE_RAM__) -int oxford_oxpcie_present CAR_GLOBAL; - -void oxford_init(void) +static void oxpcie_init_bridge(void) { u16 reg16; - oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -100,7 +100,6 @@ void oxford_init(void) break; default: /* No UART here. */ - oxford_oxpcie_present = 0; return; } @@ -113,16 +112,43 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); - /* Now the UART initialization */ - u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; + car_set_var(oxpcie_present, 1); +} - unsigned div = uart_platform_divisor(); - uart8250_mem_init(uart0_base, div); +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); } +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} #endif +unsigned uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + unsigned uart_platform_divisor(void) { return uart_divisor(4000000); } + +uint32_t uartmem_getbaseaddr(void) +{ + return uart_platform_base(0); +} + +void oxford_init(void) +{ + oxpcie_init_bridge(); + uart_init(); +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 6cd3beb..6b1d70b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -29,7 +29,10 @@ unsigned char uart_rx_byte(void); unsigned uart_divisor(unsigned basefreq); unsigned uart_platform_divisor(void); - +unsigned uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); +void oxford_init(void); +void oxford_remap(u32 new_base): + #endif /* CONSOLE_UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h deleted file mode 100644 index 6a2518b..0000000 --- a/src/include/uart8250.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef UART8250_H -#define UART8250_H - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - -#if ((115200 % CONFIG_TTYS0_BAUD) != 0) -#error Bad ttyS0 baud rate -#endif - -unsigned uart_platform_divisor(void); -unsigned uart_divisor(unsigned basefreq); - -#if CONFIG_CONSOLE_SERIAL8250MEM -void uartmem_init(void); - -/* and the same for memory mapped uarts */ -unsigned char uart8250_mem_rx_byte(unsigned base_port); -int uart8250_mem_can_rx_byte(unsigned base_port); -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); -void uart8250_mem_tx_flush(unsigned base_port); -void uart8250_mem_init(unsigned base_port, unsigned divisor); -u32 uart_mem_init(void); - -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; - -void oxford_init(void); -#endif -#endif - -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - -#endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index cff67d7..3540c4b 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -19,8 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> -#include <device/device.h> +#include <console/uart.h> #include <delay.h> #include "drivers/uart/uart8250reg.h" @@ -52,23 +51,23 @@ static inline void uart8250_mem_wait_until_sent(unsigned base_port) udelay(1); } -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) { uart8250_mem_wait_to_tx_byte(base_port); write8(base_port + UART_TBR, data); } -void uart8250_mem_tx_flush(unsigned base_port) +static void uart8250_mem_tx_flush(unsigned base_port) { uart8250_mem_wait_until_sent(base_port); } -int uart8250_mem_can_rx_byte(unsigned base_port) +static int uart8250_mem_can_rx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_mem_rx_byte(unsigned base_port) +static unsigned char uart8250_mem_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base_port)) @@ -79,7 +78,7 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port) return 0x0; } -void uart8250_mem_init(unsigned base_port, unsigned divisor) +static void uart8250_mem_init(unsigned base_port, unsigned divisor) { /* Disable interrupts */ write8(base_port + UART_IER, 0x0); @@ -100,35 +99,37 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -u32 uart_mem_init(void) -{ - u32 uart_bar = 0; - unsigned div = uart_platform_divisor(); - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - if (dev) { - struct resource *res = find_resource(dev, 0x10); +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART -#endif +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} - if (uart_bar) - uart8250_mem_init(uart_bar, div); +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} - return uart_bar; +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); }

1 0

New patch to review for coreboot: 5841f15 uart8250io: Unify calls with generic UART
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5234 -gerrit commit 5841f155c4332e62170528569dd39a2d5a6dbecf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 07:53:18 2014 +0200 uart8250io: Unify calls with generic UART Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 8 +++----- src/arch/x86/lib/romstage_console.c | 6 +++--- src/console/uart8250_console.c | 10 +++++----- src/include/uart8250.h | 11 ----------- src/lib/uart8250.c | 31 ++++++++++++++++++++++++------- 5 files changed, 35 insertions(+), 31 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 0f0e017..5a88146 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/uart.h> #include <console/ne2k.h> /* __PRE_RAM__ */ @@ -28,9 +29,6 @@ * we could use the same code on all architectures. */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 -#include <uart8250.h> -#endif #include <console/util.c> @@ -44,7 +42,7 @@ static void __console_tx_byte(unsigned char byte) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -65,7 +63,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4981f39..89d7f82 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,7 +26,7 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -42,7 +42,7 @@ void console_tx_byte(unsigned char byte) } #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usb_tx_byte(0, byte); @@ -64,7 +64,7 @@ void console_tx_flush(void) uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 196412c..52f59f6 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -18,7 +18,7 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> static void ttyS0_init(void) { @@ -27,22 +27,22 @@ static void ttyS0_init(void) static void ttyS0_tx_byte(unsigned char data) { - uart8250_tx_byte(CONFIG_TTYS0_BASE, data); + uart_tx_byte(data); } static void ttyS0_tx_flush(void) { - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); } static unsigned char ttyS0_rx_byte(void) { - return uart8250_rx_byte(CONFIG_TTYS0_BASE); + return uart_rx_byte(); } static int ttyS0_tst_byte(void) { - return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); + return uart_can_rx_byte(); } static const struct console_driver uart8250_console __console = { diff --git a/src/include/uart8250.h b/src/include/uart8250.h index f2d59da..6a2518b 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -29,17 +29,6 @@ unsigned uart_platform_divisor(void); unsigned uart_divisor(unsigned basefreq); -#if CONFIG_CONSOLE_SERIAL8250 -unsigned char uart8250_rx_byte(unsigned base_port); -int uart8250_can_rx_byte(unsigned base_port); -void uart8250_tx_byte(unsigned base_port, unsigned char data); -void uart8250_tx_flush(unsigned base_port); -/* Yes it is silly to have three different uart init functions. But we used to - * have three different sets of uart code, so it's an improvement. - */ -void uart8250_init(unsigned base_port, unsigned divisor); -void uart_init(void); -#endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 4d2cb63..75caa06 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -19,7 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> +#include <console/uart.h> #include <trace.h> #include "drivers/uart/uart8250reg.h" @@ -51,23 +51,23 @@ static inline void uart8250_wait_until_sent(unsigned base_port) while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); } -void uart8250_tx_byte(unsigned base_port, unsigned char data) +static void uart8250_tx_byte(unsigned base_port, unsigned char data) { uart8250_wait_to_tx_byte(base_port); outb(data, base_port + UART_TBR); } -void uart8250_tx_flush(unsigned base_port) +static void uart8250_tx_flush(unsigned base_port) { uart8250_wait_until_sent(base_port); } -int uart8250_can_rx_byte(unsigned base_port) +static int uart8250_can_rx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_rx_byte(unsigned base_port) +static unsigned char uart8250_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_rx_byte(base_port)); @@ -78,7 +78,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) return 0x0; } -void uart8250_init(unsigned base_port, unsigned divisor) +static void uart8250_init(unsigned base_port, unsigned divisor) { DISABLE_TRACE; /* Disable interrupts */ @@ -101,8 +101,25 @@ void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } +static const unsigned base = CONFIG_TTYS0_BASE; + void uart_init(void) { unsigned int div = uart_divisor(115200); - uart8250_init(CONFIG_TTYS0_BASE, div); + uart8250_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(base); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(base); }

1 0

New patch to review for coreboot: 14a4965 uart8250: Split register definitions
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5233 -gerrit commit 14a4965643115e87818d50ccc8e67fa9827ccc5c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 06:59:51 2014 +0200 uart8250: Split register definitions Change-Id: Ideb7f55f329e1ae037debc156d3cb4a5b95bde22 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 7 +-- src/drivers/uart/uart8250reg.h | 108 +++++++++++++++++++++++++++++++++++++++++ src/include/uart8250.h | 85 -------------------------------- src/lib/uart8250.c | 1 + src/lib/uart8250mem.c | 1 + 5 files changed, 111 insertions(+), 91 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index dc98bff..83f677a 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -7,12 +7,7 @@ #include "uart.h" #include <arch/io.h> - -/* Give me my 8250 UART definitions!!!! */ -/* TODO: Clean this up when uart8250mem works on ARM */ -#undef CONFIG_CONSOLE_SERIAL8250MEM -#define CONFIG_CONSOLE_SERIAL8250MEM 1 -#include <uart8250.h> +#include "drivers/uart8250/uart8250reg.h" /** * \brief Configure line control settings for UART diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h new file mode 100644 index 0000000..cdfbb1b --- /dev/null +++ b/src/drivers/uart/uart8250reg.h @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef UART8250REG_H +#define UART8250REG_H + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +#define UART_IIR 0x02 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_FCR 0x02 +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_LCR 0x03 +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity enable */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +#define UART_MCR 0x04 +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR 0x06 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +#define UART_SCR 0x07 +#define UART_SPR 0x07 + +#endif /* UART8250REG_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 83b4535..f2d59da 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -22,91 +22,6 @@ #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -#define UART_IIR 0x02 -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ - -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -#define UART_FCR 0x02 -#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ - -#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ - -#define UART_LCR 0x03 -#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ -#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ -#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ -#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART_LCR_PEN 0x08 /* Parity enable */ -#define UART_LCR_EPS 0x10 /* Even Parity Select */ -#define UART_LCR_STKP 0x20 /* Stick Parity */ -#define UART_LCR_SBRK 0x40 /* Set Break */ -#define UART_LCR_BKSE 0x80 /* Bank select enable */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ - -#define UART_MCR 0x04 -#define UART_MCR_DTR 0x01 /* DTR */ -#define UART_MCR_RTS 0x02 /* RTS */ -#define UART_MCR_OUT1 0x04 /* Out 1 */ -#define UART_MCR_OUT2 0x08 /* Out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ - -#define UART_MCR_DMA_EN 0x04 -#define UART_MCR_TX_DFR 0x08 - -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_OE 0x02 /* Overrun */ -#define UART_LSR_PE 0x04 /* Parity error */ -#define UART_LSR_FE 0x08 /* Framing error */ -#define UART_LSR_BI 0x10 /* Break */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART_LSR_ERR 0x80 /* Error */ - -#define UART_MSR 0x06 -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ - -#define UART_SCR 0x07 -#define UART_SPR 0x07 - #if ((115200 % CONFIG_TTYS0_BAUD) != 0) #error Bad ttyS0 baud rate #endif diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index bcb137a..4d2cb63 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <uart8250.h> #include <trace.h> +#include "drivers/uart/uart8250reg.h" /* Should support 8250, 16450, 16550, 16550A type UARTs */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 26c83fa..cff67d7 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -22,6 +22,7 @@ #include <uart8250.h> #include <device/device.h> #include <delay.h> +#include "drivers/uart/uart8250reg.h" /* Should support 8250, 16450, 16550, 16550A type UARTs */

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New patch to review for coreboot: db9a10d console: Fix includes
by Kyösti Mälkki 15 Feb '14

15 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5232 -gerrit commit db9a10dce33c66945cc8d97303cf98e816d9d95a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 06:11:01 2014 +0200 console: Fix includes Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 1 + src/arch/x86/lib/romstage_console.c | 14 +++++--------- src/console/console.c | 6 ++++++ src/include/console/console.h | 16 ---------------- src/lib/cbmem.c | 1 + src/lib/cbmem_console.c | 1 + src/northbridge/intel/sandybridge/raminit.c | 1 + 7 files changed, 15 insertions(+), 25 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index e517428..0f0e017 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/ne2k.h> /* __PRE_RAM__ */ /* Using a global varible can cause problems when we reset the stack diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4ef702f..4981f39 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -19,20 +19,16 @@ #include <smp/node.h> #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> +#include <console/usb.h> +#include <console/ne2k.h> +#include <console/spkmodem.h> #include <console/vtxprintf.h> #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif -#if CONFIG_USBDEBUG -#include <console/usb.h> -#endif -#if CONFIG_CONSOLE_NE2K -#include <console/ne2k.h> -#endif -#if CONFIG_SPKMODEM -#include <console/spkmodem.h> -#endif void console_tx_byte(unsigned char byte) { diff --git a/src/console/console.c b/src/console/console.c index 081113c..334e140 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -18,6 +18,12 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> +#include <console/uart.h> +#include <console/usb.h> +#include <console/ne2k.h> +#include <console/spkmodem.h> + #include <build.h> #include <arch/hlt.h> #include <arch/io.h> diff --git a/src/include/console/console.h b/src/include/console/console.h index 4df8cb6..a089729 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -24,22 +24,6 @@ #include <console/loglevel.h> #include <console/post_codes.h> -#if CONFIG_CONSOLE_SERIAL -#include <console/uart.h> -#endif -#if CONFIG_USBDEBUG && !defined(__ROMCC__) -#include <console/usb.h> -#endif -#if CONFIG_CONSOLE_NE2K -#include <console/ne2k.h> -#endif -#if CONFIG_CONSOLE_CBMEM -#include <console/cbmem_console.h> -#endif -#if CONFIG_SPKMODEM -#include <console/spkmodem.h> -#endif - #ifndef __PRE_RAM__ unsigned char console_rx_byte(void); int console_tst_byte(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index d97f6af..3fea49a 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,6 +23,7 @@ #include <cbmem.h> #include <boot/coreboot_tables.h> #include <console/console.h> +#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 83d44e3..9d5419a 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <console/cbmem_console.h> #include <cbmem.h> #include <arch/early_variables.h> #include <string.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b9c3839..bfb4033 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <console/usb.h> #include <string.h> #include <arch/hlt.h> #include <arch/io.h>

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coreboot-gerrit February 2014