coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 390099d libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 12 Feb '14

12 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit 390099d7f8843071c09ae53648df41dff4ecd3cc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 44 ++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..1ac2b63 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,46 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* Alignment-agnostic encode/decode bytestream to/from little/big endian. + * Note: Trimmed down from FreeBSD 10.0 (sys/endian.h). + */ + +static inline uint16_t +le16dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static inline uint32_t +le32dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static inline void +le16enc(void *pp, uint16_t u) +{ + unsigned char *p = (unsigned char *)pp; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; +} + +static inline void +le32enc(void *pp, uint32_t u) +{ + unsigned char *p = (unsigned char *)pp; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; + p[2] = (u >> 16) & 0xff; + p[3] = (u >> 24) & 0xff; +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +141,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

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New patch to review for coreboot: 20fa65e libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 12 Feb '14

12 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit 20fa65e11d53f4aeddf2f93370202a81bdbf6f98 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any align- ment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 44 ++++++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..c670fb1 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,46 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* Alignment-agnostic encode/decode bytestream to/from little/big endian. + * Note: Trimmed down from FreeBSD 10.0 (sys/endian.h). + */ + +static __inline uint16_t +le16dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static __inline uint32_t +le32dec(const void *pp) +{ + unsigned char const *p = (unsigned char const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static __inline void +le16enc(void *pp, uint16_t u) +{ + unsigned char *p = (unsigned char *)pp; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; +} + +static __inline void +le32enc(void *pp, uint32_t u) +{ + unsigned char *p = (unsigned char *)pp; + + p[0] = u & 0xff; + p[1] = (u >> 8) & 0xff; + p[2] = (u >> 16) & 0xff; + p[3] = (u >> 24) & 0xff; +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +141,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

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Patch set updated for coreboot: b778a56 intel/fsp_sandybridge/acpi/sandybridge.asl: Increase range length of buffer to 0x8000
by Paul Menzel 12 Feb '14

12 Feb '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5192 -gerrit commit b778a563a2762872c0ba05af935b126747579f94 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Feb 11 10:38:27 2014 +0100 intel/fsp_sandybridge/acpi/sandybridge.asl: Increase range length of buffer to 0x8000 Linux kernel 2.6.31 reports the following warning. resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01 Indeed `src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl` contains OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) so instead of 16 kB specify that 32 kB are decoded in that memory range. Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f Reported-by: Norwich in #coreboot on <irc.freenode.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl index 7d51135..e6012ff 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl @@ -30,7 +30,7 @@ Device (PDRC) Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)

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Patch set updated for coreboot: 476986e winbond/w83627hf/acpi: Fix some ASL warnings
by Ronald G. Minnich 12 Feb '14

12 Feb '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5190 -gerrit commit 476986e4e4493dd773f3ea4df83d3287e47a9f02 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 23:20:14 2014 +0100 winbond/w83627hf/acpi: Fix some ASL warnings There were ASL compiler warnings about "Size mismatch". This commit eliminates the warnings by changing the ASL declarations of those fields. Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66 Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> --- src/superio/winbond/w83627hf/acpi/superio.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index a8a184a..41f3588 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -712,7 +712,7 @@ Device(SIO) { IRQNoFlags (IRQX) {} }) CreateWordField (Arg0, IO0._MIN, IOA0) - CreateByteField (Arg0, IRQX._INT, IRQL) + CreateWordField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) @@ -1153,7 +1153,7 @@ Device(SIO) { }) CreateWordField (Arg0, IO0._MIN, IOA0) CreateWordField (Arg0, IO1._MIN, IOA1) - CreateByteField (Arg0, IRQX._INT, IRQL) + CreateWordField (Arg0, IRQX._INT, IRQL) Divide(IOA0, 256, Local0, Local1) Divide(IOA1, 256, Local2, Local3) @@ -1235,7 +1235,7 @@ Device(SIO) { Name (TMPL, ResourceTemplate () { IRQNoFlags (IRQX) {} }) - CreateByteField (Arg0, IRQX._INT, IRQL) + CreateWordField (Arg0, IRQX._INT, IRQL) Subtract(FindSetLeftBit (IRQL), 1, Local0)

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New patch to review for coreboot: 1c13148 usbdebug: Split to USB host/device
by Kyösti Mälkki 12 Feb '14

12 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5197 -gerrit commit 1c1314868101a34c71a9bbaa107222913fc115cf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 9 23:35:39 2014 +0200 usbdebug: Split to USB host/device Top-level interface to console over USB mut not require low-level details of ECHI debug port internals. Change-Id: If3ca3b1f479e3f20976cd4abd8f5e682a58d5650 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/Makefile.inc | 4 +-- src/drivers/usb/console.c | 64 ++++++++++++++++++++++++++++++++++++++++++++ src/drivers/usb/ehci_debug.c | 63 ++----------------------------------------- src/drivers/usb/ehci_debug.h | 22 +++++++++++++++ 4 files changed, 90 insertions(+), 63 deletions(-) diff --git a/src/drivers/usb/Makefile.inc b/src/drivers/usb/Makefile.inc index 043ebe1..bab6737 100644 --- a/src/drivers/usb/Makefile.inc +++ b/src/drivers/usb/Makefile.inc @@ -1,3 +1,3 @@ -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c pci_ehci.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ehci_debug.c pci_ehci.c console.c -ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c +ramstage-$(CONFIG_USBDEBUG) += ehci_debug.c pci_ehci.c console.c diff --git a/src/drivers/usb/console.c b/src/drivers/usb/console.c new file mode 100644 index 0000000..c47610a --- /dev/null +++ b/src/drivers/usb/console.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Eric Biederman (ebiederm(a)xmission.com) + * Copyright (C) 2007 AMD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <stddef.h> +#include <console/console.h> +#include <console/usb.h> +#include "ehci_debug.h" + +void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data) +{ + if (!dbgp_try_get(pipe)) + return; + pipe->buf[pipe->bufidx++] = data; + if (pipe->bufidx >= 8) { + dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); + pipe->bufidx = 0; + } + dbgp_put(pipe); +} + +void usbdebug_tx_flush(struct dbgp_pipe *pipe) +{ + if (!dbgp_try_get(pipe)) + return; + if (pipe->bufidx > 0) { + dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); + pipe->bufidx = 0; + } + dbgp_put(pipe); +} + +unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe) +{ + unsigned char data = 0xff; + if (!dbgp_try_get(pipe)) + return 0xff; + while (pipe->bufidx >= pipe->buflen) { + pipe->buflen = 0; + pipe->bufidx = 0; + int count = dbgp_bulk_read_x(pipe, pipe->buf, 8); + if (count>0) + pipe->buflen = count; + } + data = pipe->buf[pipe->bufidx++]; + dbgp_put(pipe); + return data; +} diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index beb553e..c60fbaa 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -31,25 +31,6 @@ #include "usb_ch9.h" #include "ehci.h" - -#define DBGP_EP_VALID (1<<0) -#define DBGP_EP_ENABLED (1<<1) -#define DBGP_EP_BUSY (1<<2) -#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) - -struct dbgp_pipe -{ - u8 devnum; - u8 endpoint; - u8 pid; - u8 status; - int timeout; - - u8 bufidx; - u8 buflen; - char buf[8]; -}; - #define DBGP_MAX_ENDPOINTS 4 #define DBGP_SETUP_EP0 0 /* Compulsory endpoint 0. */ #define DBGP_CONSOLE_EPOUT 1 @@ -852,7 +833,7 @@ static int dbgp_enabled(void) } #endif -static int dbgp_try_get(struct dbgp_pipe *pipe) +int dbgp_try_get(struct dbgp_pipe *pipe) { struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0]; if (!dbgp_ep_is_active(pipe) || (globals->status & DBGP_EP_BUSY)) @@ -862,53 +843,13 @@ static int dbgp_try_get(struct dbgp_pipe *pipe) return 1; } -static void dbgp_put(struct dbgp_pipe *pipe) +void dbgp_put(struct dbgp_pipe *pipe) { struct dbgp_pipe *globals = &dbgp_ehci_info()->ep_pipe[DBGP_SETUP_EP0]; globals->status &= ~DBGP_EP_BUSY; pipe->status &= ~DBGP_EP_BUSY; } -void usbdebug_tx_byte(struct dbgp_pipe *pipe, unsigned char data) -{ - if (!dbgp_try_get(pipe)) - return; - pipe->buf[pipe->bufidx++] = data; - if (pipe->bufidx >= 8) { - dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); - pipe->bufidx = 0; - } - dbgp_put(pipe); -} - -void usbdebug_tx_flush(struct dbgp_pipe *pipe) -{ - if (!dbgp_try_get(pipe)) - return; - if (pipe->bufidx > 0) { - dbgp_bulk_write_x(pipe, pipe->buf, pipe->bufidx); - pipe->bufidx = 0; - } - dbgp_put(pipe); -} - -unsigned char usbdebug_rx_byte(struct dbgp_pipe *pipe) -{ - unsigned char data = 0xff; - if (!dbgp_try_get(pipe)) - return 0xff; - while (pipe->bufidx >= pipe->buflen) { - pipe->buflen = 0; - pipe->bufidx = 0; - int count = dbgp_bulk_read_x(pipe, pipe->buf, 8); - if (count>0) - pipe->buflen = count; - } - data = pipe->buf[pipe->bufidx++]; - dbgp_put(pipe); - return data; -} - #if !defined(__PRE_RAM__) && !defined(__SMM__) void usbdebug_re_enable(unsigned ehci_base) { diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index 2e549d2..c470ad6 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -27,4 +27,26 @@ void usbdebug_disable(void); int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset); void ehci_debug_select_port(unsigned int port); + +#define DBGP_EP_VALID (1<<0) +#define DBGP_EP_ENABLED (1<<1) +#define DBGP_EP_BUSY (1<<2) +#define DBGP_EP_STATMASK (DBGP_EP_VALID | DBGP_EP_ENABLED) + +struct dbgp_pipe +{ + u8 devnum; + u8 endpoint; + u8 pid; + u8 status; + int timeout; + + u8 bufidx; + u8 buflen; + char buf[8]; +}; + +void dbgp_put(struct dbgp_pipe *pipe); +int dbgp_try_get(struct dbgp_pipe *pipe); + #endif /* _EHCI_DEBUG_H_ */

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New patch to review for coreboot: 7464180 PCI: Add some utility functions for romstage
by Kyösti Mälkki 12 Feb '14

12 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5196 -gerrit commit 74641808995b85270e30a70c0d21a0992be515a7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 11 19:56:57 2014 +0200 PCI: Add some utility functions for romstage These are almost one-to-one copies from pci_device.c. However, devicetree has not been enumerated yet and we have no console. Change-Id: Ic80c781626521d03adde05bdb1916acce31290ea Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/Makefile.inc | 3 ++- src/device/pci_early.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci.h | 7 +++-- 3 files changed, 75 insertions(+), 3 deletions(-) diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 1dbb510..ce412b7 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -13,7 +13,8 @@ ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-y += smbus_ops.c -romstage-y+= device_romstage.c +romstage-y += device_romstage.c +romstage-$(CONFIG_PCI) += pci_early.c subdirs-y += oprom diff --git a/src/device/pci_early.c b/src/device/pci_early.c new file mode 100644 index 0000000..c15a4d0 --- /dev/null +++ b/src/device/pci_early.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_def.h> + +unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) +{ + unsigned pos = 0; + u16 status; + unsigned reps = 48; + + status = pci_read_config16(dev, PCI_STATUS); + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + u8 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE); + switch (hdr_type & 0x7f) { + case PCI_HEADER_TYPE_NORMAL: + case PCI_HEADER_TYPE_BRIDGE: + pos = PCI_CAPABILITY_LIST; + break; + case PCI_HEADER_TYPE_CARDBUS: + pos = PCI_CB_CAPABILITY_LIST; + break; + default: + return 0; + } + + pos = pci_read_config8(dev, pos); + while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */ + int this_cap; + + pos &= ~3; + this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID); + if (this_cap == 0xff) + break; + + if (!last && (this_cap == cap)) + return pos; + + if (last == pos) + last = 0; + + pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT); + } + return 0; +} + +unsigned pci_find_capability(device_t dev, unsigned cap) +{ + return pci_find_next_capability(dev, cap, 0); +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1741c0d..038da2f 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -18,6 +18,7 @@ #include <stdint.h> #include <stddef.h> #include <arch/rules.h> +#include <arch/io.h> #include <device/pci_def.h> #include <device/resource.h> #include <device/device.h> @@ -74,8 +75,6 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devf uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); -unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); @@ -98,4 +97,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) } #endif /* ! __SIMPLE_DEVICE__ */ + +unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); +unsigned pci_find_capability(device_t dev, unsigned cap); + #endif /* PCI_H */

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Patch set updated for coreboot: ced2d12 usbdebug: Remove EHCI_DEBUG_OFFSET
by Kyösti Mälkki 12 Feb '14

12 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5176 -gerrit commit ced2d125f44eeb21f440e368dc54e0742b55c295 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 9 19:21:30 2014 +0200 usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/ehci_debug.c | 9 ++++++--- src/drivers/usb/ehci_debug.h | 2 +- src/drivers/usb/pci_ehci.c | 22 ++++++++++++++++++++-- src/southbridge/amd/agesa/hudson/Kconfig | 4 ---- src/southbridge/amd/cimx/sb700/Kconfig | 4 ---- src/southbridge/amd/cimx/sb800/Kconfig | 4 ---- src/southbridge/amd/sb600/Kconfig | 4 ---- src/southbridge/amd/sb700/Kconfig | 4 ---- src/southbridge/amd/sb800/Kconfig | 4 ---- src/southbridge/intel/bd82x6x/Kconfig | 4 ---- src/southbridge/intel/fsp_bd82x6x/Kconfig | 4 ---- src/southbridge/intel/i82801dx/Kconfig | 4 ---- src/southbridge/intel/i82801ex/Kconfig | 4 ---- src/southbridge/intel/i82801gx/Kconfig | 4 ---- src/southbridge/intel/i82801ix/Kconfig | 4 ---- src/southbridge/intel/ibexpeak/Kconfig | 4 ---- src/southbridge/intel/lynxpoint/Kconfig | 4 ---- src/southbridge/intel/sch/Kconfig | 4 ---- src/southbridge/nvidia/ck804/Kconfig | 4 ---- src/southbridge/nvidia/mcp55/Kconfig | 4 ---- src/southbridge/sis/sis966/Kconfig | 3 --- 21 files changed, 27 insertions(+), 77 deletions(-) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 26d61fb..beb553e 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -588,6 +588,8 @@ static int usbdebug_init_(unsigned ehci_bar, unsigned offset, struct ehci_debug_ int port_map_tried; int playtimes = 3; + dprintk(BIOS_INFO, "ehci_bar: 0x%x debug_offset 0x%x\n", ehci_bar, offset); + ehci_caps = (struct ehci_caps *)ehci_bar; ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32((unsigned long)&ehci_caps->hc_capbase))); @@ -608,7 +610,6 @@ try_next_port: debug_port = HCS_DEBUG_PORT(hcs_params); n_ports = HCS_N_PORTS(hcs_params); - dprintk(BIOS_INFO, "ehci_bar: 0x%x\n", ehci_bar); dprintk(BIOS_INFO, "debug_port: %d\n", debug_port); dprintk(BIOS_INFO, "n_ports: %d\n", n_ports); @@ -985,11 +986,13 @@ struct dbgp_pipe *dbgp_console_input(void) int usbdebug_init(void) { struct ehci_debug_info *dbg_info = dbgp_ehci_info(); + unsigned int ehci_base, dbg_offset; #if !defined(__PRE_RAM__) && !defined(__SMM__) if (!get_usbdebug_from_cbmem(dbg_info)) return 0; #endif - ehci_debug_hw_enable(); - return usbdebug_init_(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info); + if (ehci_debug_hw_enable(&ehci_base, &dbg_offset)) + return -1; + return usbdebug_init_(ehci_base, dbg_offset, dbg_info); } diff --git a/src/drivers/usb/ehci_debug.h b/src/drivers/usb/ehci_debug.h index 462eb23..2e549d2 100644 --- a/src/drivers/usb/ehci_debug.h +++ b/src/drivers/usb/ehci_debug.h @@ -24,7 +24,7 @@ void usbdebug_re_enable(unsigned ehci_base); void usbdebug_disable(void); -void ehci_debug_hw_enable(void); +int ehci_debug_hw_enable(unsigned *base, unsigned *dbg_offset); void ehci_debug_select_port(unsigned int port); #endif /* _EHCI_DEBUG_H_ */ diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 7c715f6..3a83454 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -34,12 +34,30 @@ static struct device_operations *ehci_drv_ops; static struct device_operations ehci_dbg_ops; #endif -void ehci_debug_hw_enable(void) +int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { -#if defined(__PRE_RAM__) || !CONFIG_USBDEBUG_IN_ROMSTAGE pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); pci_ehci_dbg_enable(dbg_dev, CONFIG_EHCI_BAR); +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev = dbg_dev; +#else + device_t dev = dev_find_slot(PCI_DEV2SEGBUS(dbg_dev), PCI_DEV2DEVFN(dbg_dev)); #endif + + u8 pos = pci_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); + if (!pos) + return 1; + + u32 cap = pci_read_config32(dev, pos); + + /* FIXME: We should remove static EHCI_BAR_INDEX. */ + u8 dbg_bar = 0x10 + 4 * ((cap >> 29) - 1); + if (dbg_bar != EHCI_BAR_INDEX) + return 1; + + *base = CONFIG_EHCI_BAR; + *dbg_offset = (cap>>16) & 0x1ffc; + return 0; } void ehci_debug_select_port(unsigned int port) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 1550cb4..dd5120d 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -43,10 +43,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" default y diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 4304357..d8bad86 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -54,10 +54,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/cimx/sb700/bootblock.c" diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 37aff9e..832655d 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -209,10 +209,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - choice prompt "Fan Control" default SB800_NO_FAN_CONTROL diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index fe9468d..4d5fff4 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -32,10 +32,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - choice prompt "SATA Mode" default SATA_MODE_IDE diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index b0c92dc..e391fc8 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -45,8 +45,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - endif # SOUTHBRIDGE_AMD_SB700 diff --git a/src/southbridge/amd/sb800/Kconfig b/src/southbridge/amd/sb800/Kconfig index 9547d3e..24dc007 100644 --- a/src/southbridge/amd/sb800/Kconfig +++ b/src/southbridge/amd/sb800/Kconfig @@ -37,8 +37,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xe0 - endif # SOUTHBRIDGE_AMD_SB800 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index d060dae..9cfa5d5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,10 +41,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 1a8e80a..b2b4929 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -37,10 +37,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/fsp_bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index f7f93a7..8ef778f 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -33,8 +33,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x80 - endif diff --git a/src/southbridge/intel/i82801ex/Kconfig b/src/southbridge/intel/i82801ex/Kconfig index e4e9160..caa5c79 100644 --- a/src/southbridge/intel/i82801ex/Kconfig +++ b/src/southbridge/intel/i82801ex/Kconfig @@ -11,8 +11,4 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - endif diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 62c6b43..777b69b 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -32,10 +32,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801gx/bootblock.c" diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 8a4a53e..493be60 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -33,10 +33,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/i82801ix/bootblock.c" diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 97d5883..c05fe43 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -39,10 +39,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..bfb7b73 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -44,10 +44,6 @@ config EHCI_BAR hex default 0xe8000000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/lynxpoint/bootblock.c" diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index 432fb8d..d320a53 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -30,10 +30,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0xa0 - config HAVE_CMC bool "Add a CMC state machine binary" help diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index b6f718e..e21f79e 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -14,10 +14,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x98 - config CK804_USE_NIC bool default n diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index cd6009d..89aa452 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -14,10 +14,6 @@ config EHCI_BAR hex default 0xfef00000 -config EHCI_DEBUG_OFFSET - hex - default 0x98 - config MCP55_USE_NIC bool default n diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 03dd6b1..1fbd57d 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -12,6 +12,3 @@ config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 -config EHCI_DEBUG_OFFSET - hex - default 0x98 if SOUTHBRIDGE_SIS_SIS966

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Patch set updated for coreboot: d8526c8 option: Add arch-agnostic get_option()
by Kyösti Mälkki 12 Feb '14

12 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5157 -gerrit commit d8526c8b8bfbd1cacaab685962df7db0e0bc59d4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 10:02:53 2014 +0200 option: Add arch-agnostic get_option() We should not have pc80/ includes in UARTs or generally in lib/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 13 +------------ src/console/uart8250_console.c | 1 - src/console/uart8250mem_console.c | 1 - src/include/option.h | 19 +++++++++++++++++++ src/lib/uart8250.c | 2 +- src/lib/uart8250mem.c | 2 +- src/mainboard/intel/jarrell/watchdog.c | 1 + 7 files changed, 23 insertions(+), 16 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 38ac3e7..081113c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -25,18 +25,7 @@ #ifndef __PRE_RAM__ #include <string.h> #include <types.h> - -/* - * FIXME: get_option() needs to be abstracted better so that other non-volatile - * storage can be used. This will benefit machines without CMOS as well as those - * without a battery-backed CMOS (e.g. some laptops). - */ -#if CONFIG_USE_OPTION_TABLE -#include <pc80/mc146818rtc.h> -#else -static inline enum cb_err get_option(void *dest, const char *name) - { return CB_CMOS_OTABLE_DISABLED; } -#endif +#include <option.h> /* initialize the console */ void console_init(void) diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 330ed68..196412c 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static void ttyS0_init(void) { diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index ed77237..3833e47 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> static u32 uart_bar = 0; diff --git a/src/include/option.h b/src/include/option.h new file mode 100644 index 0000000..83f3a84 --- /dev/null +++ b/src/include/option.h @@ -0,0 +1,19 @@ +#ifndef _OPTION_H_ +#define _OPTION_H_ + +/* + * FIXME: get_option() needs to be abstracted better so that other non-volatile + * storage can be used. This will benefit machines without CMOS as well as those + * without a battery-backed CMOS (e.g. some laptops). + */ +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#else +#include <types.h> +static inline enum cb_err get_option(void *dest, const char *name) +{ + return CB_CMOS_OTABLE_DISABLED; +} +#endif + +#endif /* _OPTION_H_ */ diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index aa18d2a..b253ea4 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #include <trace.h> #if CONFIG_USE_OPTION_TABLE diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..c2298a8 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> +#include <option.h> #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..7f7a039 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -1,4 +1,5 @@ #include <device/pnp_def.h> +#include <pc80/mc146818rtc.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) #define NSC_WDBASE 0x600

1 0

Patch merged into coreboot/master: 8a41a2e hp/dl145_g1: Add missing copyright notes
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit 8a41a2e28ff0f94fdc0fd20d3f1a483b78bb9138 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:19:35 2014 +0100 hp/dl145_g1: Add missing copyright notes Missing copyright notes added. Change-Id: I55b320a169b1125017c63b7a2384078465e7ce6e Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> See http://review.coreboot.org/5188 for details. -gerrit

1 0

Patch merged into coreboot/master: bdeedfe hp/dl145_g1: Fix some commented out code
by gerrit＠coreboot.org 11 Feb '14

11 Feb '14

the following patch was just integrated into master: commit bdeedfee46ba632dec112d8d11b9e87c27de7b23 Author: Oskar Enoksson <enok(a)lysator.liu.se> Date: Tue Feb 11 22:15:18 2014 +0100 hp/dl145_g1: Fix some commented out code Some out-commented code contained variables which changed name. This commit fixes the "problem". Change-Id: I8d9168c9f4b2cb6810b3e4dfeff2155f3c08357d Signed-off-by: Oskar Enoksson <enok(a)lysator.liu.se> See http://review.coreboot.org/5187 for details. -gerrit

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coreboot-gerrit February 2014