coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch merged into coreboot/master: 898f576 lenovo/x201: Fix wrong declaration in devicetree.cb
by gerrit＠coreboot.org 17 Feb '14

17 Feb '14

the following patch was just integrated into master: commit 898f576b78b3a6c332aba414e5edf33c4e3bc34c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 18:03:45 2014 +0100 lenovo/x201: Fix wrong declaration in devicetree.cb Change-Id: I90c6ff14ab819368ccc874008a7fb1410a543984 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5255 for details. -gerrit

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Patch merged into coreboot/master: 21e6d85 baytrail: enable monotonic timer
by gerrit＠coreboot.org 17 Feb '14

17 Feb '14

the following patch was just integrated into master: commit 21e6d85606306c4e094c03d5a07bd2b5f99e16b6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 24 08:42:10 2013 -0500 baytrail: enable monotonic timer Enabling the monotonic timer allows for collecting boot stage times as well as each device initialization time. BUG=chrome-os-partner:23166 BRANCH=None TEST=Built and booted. Noted timings in console output. Change-Id: I5fdc703ea21710fd26de352f367c6fc0c767ab6a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174422 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4894 for details. -gerrit

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Patch merged into coreboot/master: c2ba9d6 src/drivers/spi: introduce AMIC support
by gerrit＠coreboot.org 17 Feb '14

17 Feb '14

the following patch was just integrated into master: commit c2ba9d6578d7c708085f34981f5e2fcbc0a2210d Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Feb 16 00:32:13 2014 +0000 src/drivers/spi: introduce AMIC support Add support for the AMIC A25L032 flash chip. Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/5252 for details. -gerrit

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Patch merged into coreboot/master: 0e23020 vortex86ex: Drop baudrate programming for 10 UARTs
by gerrit＠coreboot.org 17 Feb '14

17 Feb '14

the following patch was just integrated into master: commit 0e230203fe50e037d3a92f7bc4dd5c03834ce93c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 16 06:55:41 2014 +0200 vortex86ex: Drop baudrate programming for 10 UARTs This is responsibility of end-user application. When coreboot does it, it is only for the purpose of debug console. Change-Id: Idbbf9528c60b9b819b7bea9dfe84078a3f055bc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5251 for details. -gerrit

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Patch merged into coreboot/master: a08ab5b sandy/ivy: Fix mrc.cache file in CBFS
by gerrit＠coreboot.org 17 Feb '14

17 Feb '14

the following patch was just integrated into master: commit a08ab5b59d9f5ec56bbe339e5f2e19a41363078a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 00:33:40 2014 +0200 sandy/ivy: Fix mrc.cache file in CBFS The file was not recreated when configuration changed. One would hit this bug when turning CHROMEOS on/off. Also do not create mrc.cache with CHROMEOS at all. Change-Id: I5b0ecde66589396b24967ce289bf65e20bb08825 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5211 for details. -gerrit

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New patch to review for coreboot: 075d161 chromeos: provide option to dynamically allocate ram oops buffer
by Aaron Durbin 17 Feb '14

17 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5257 -gerrit commit 075d16112fe73b788e99e7236053198d7307dcc9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 14 00:30:04 2014 -0600 chromeos: provide option to dynamically allocate ram oops buffer Fixing the location of the ram oops buffer can lead to certain kernel and boot loaders being confused when there is a ram reservation low in the address space. Alternatively provide a mechanism to allocate the ram oops buffer in cbmem. As cbmem is usually high in the address space it avoids low reservation confusion. BUG=None BRANCH=baytrail,haswell TEST=Built and booted with and w/o dynamic ram oops. With the corresponding kernel change things behave correctly. Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + src/vendorcode/google/chromeos/Kconfig | 7 +++- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/acpi/chromeos.asl | 2 ++ src/vendorcode/google/chromeos/acpi/gnvs.asl | 4 ++- src/vendorcode/google/chromeos/acpi/ramoops.asl | 43 ++++++++++++++++++++++ src/vendorcode/google/chromeos/chromeos.h | 15 ++++++++ src/vendorcode/google/chromeos/gnvs.c | 2 ++ src/vendorcode/google/chromeos/gnvs.h | 3 +- src/vendorcode/google/chromeos/ramoops.c | 46 ++++++++++++++++++++++++ 11 files changed, 122 insertions(+), 3 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index eb307d4..7d4d0ad 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -62,6 +62,7 @@ #define CBMEM_ID_REFCODE 0x04efc0de #define CBMEM_ID_REFCODE_CACHE 0x4efc0de5 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee +#define CBMEM_ID_RAM_OOPS 0x05430095 #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_HOB_POINTER 0x484f4221 diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 339e6b9..42348e4 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -52,6 +52,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_REFCODE, "REFCODE " }, { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, + { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 2f17b7e..ed358f8 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -53,10 +53,15 @@ config CHROMEOS_RAMOOPS bool "Reserve space for Chrome OS ramoops" default y +config CHROMEOS_RAMOOPS_DYNAMIC + bool "Allocate RAM oops buffer in cbmem" + default n + depends on CHROMEOS_RAMOOPS + config CHROMEOS_RAMOOPS_RAM_START hex "Physical address of preserved RAM" default 0x00f00000 - depends on CHROMEOS_RAMOOPS + depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC config CHROMEOS_RAMOOPS_RAM_SIZE hex "Size of preserved RAM" diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 4fa22ea..007bd57 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -25,6 +25,7 @@ romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c +ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c smm-y += fmap.c ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/chromeos.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 278296c..8f63f12 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -107,3 +107,5 @@ Device (CRHW) Return (TSLM) } } + +#include "ramoops.asl" diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index dc4a0bf..5377a85 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -34,4 +34,6 @@ VBT9, 32, // 0x196 - FMAP base address CHVD, 24576, // 0x19a - VDAT space filled by verified boot VBTA, 32, // 0xd9a - pointer to smbios FWID MEHH, 256, // 0xd9e - Management Engine Hash - // 0xdbe +RMOB, 32, // 0xdbe - RAM oops base address +RMOL, 32, // 0xdc2 - RAM oops length + // 0xdc6 diff --git a/src/vendorcode/google/chromeos/acpi/ramoops.asl b/src/vendorcode/google/chromeos/acpi/ramoops.asl new file mode 100644 index 0000000..e435489 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi/ramoops.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device(RMOP) + { + Name (_HID, "GOOG9999") + Name (_CID, "GOOG9999") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, MRES) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^MRES._BAS, RBAS) + CreateDwordField (^RBUF, ^MRES._LEN, RLEN) + Store (\RMOB, RBAS) + Store (\RMOL, RLEN) + Return (^RBUF) + } + } +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 0359c91..2c86be0 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -52,4 +52,19 @@ void *vboot_get_payload(size_t *len); int vboot_get_handoff_info(void **addr, uint32_t *size); #endif +#if CONFIG_CHROMEOS_RAMOOPS +#include "gnvs.h" +struct device; + +#if CONFIG_CHROMEOS_RAMOOPS_DYNAMIC +static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} +void chromeos_reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos); +#else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ +void chromeos_reserve_ram_oops(struct device *dev, int idx); +static inline void chromeos_reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) +{ +} +#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ +#endif + #endif diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 9f51097..509baa2 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -72,6 +72,8 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) reason ? reason : ELOG_CROS_RECOVERY_MODE_BUTTON); } #endif + + chromeos_reserve_ram_oops_dynamic(chromeos); } void chromeos_set_me_hash(u32 *hash, int len) diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 00fe443..9307e0d 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -58,7 +58,8 @@ typedef struct { u8 vdat[3072]; // 19a u32 vbt10; // d9a smbios bios version u32 mehh[8]; // d9e management engine hash - // dbe + u32 ramoops_base; // dbe ramoops base address + u32 ramoops_len; // dc2 ramoops length } __attribute__((packed)) chromeos_acpi_t; extern chromeos_acpi_t *vboot_data; diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c new file mode 100644 index 0000000..f0b5c39 --- /dev/null +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <stddef.h> +#include <stdint.h> +#include <cbmem.h> +#include <device/device.h> +#include "chromeos.h" + +#if CONFIG_CHROMEOS_RAMOOPS_DYNAMIC +void chromeos_reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) +{ + const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; + void *ram_oops; + + ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size); + + chromeos->ramoops_base = (uintptr_t)ram_oops; + chromeos->ramoops_len = size; +} +#else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ +void chromeos_reserve_ram_oops(struct device *dev, int idx) +{ + const unsigned long base = CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10; + const unsigned long size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10; + + reserved_ram_resource(dev, idx, base, size); +} +#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */

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Patch set updated for coreboot: c2ba9d6 src/drivers/spi: introduce AMIC support
by Idwer Vollering 17 Feb '14

17 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5252 -gerrit commit c2ba9d6578d7c708085f34981f5e2fcbc0a2210d Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Feb 16 00:32:13 2014 +0000 src/drivers/spi: introduce AMIC support Add support for the AMIC A25L032 flash chip. Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/spi/Kconfig | 8 ++ src/drivers/spi/Makefile.inc | 4 +- src/drivers/spi/amic.c | 179 +++++++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 3 + src/drivers/spi/spi_flash_internal.h | 1 + 5 files changed, 194 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index a99199a..c5db969 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -31,6 +31,14 @@ config SPI_FLASH_SMM help Select this option if you want SPI flash support in SMM. +config SPI_FLASH_AMIC + bool + default y + depends on SPI_FLASH + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by AMIC. + config SPI_FLASH_EON bool default y diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 1a34ab5..641ad8d 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -2,6 +2,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +ramstage-$(CONFIG_SPI_FLASH_AMIC) += amic.c ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c @@ -16,6 +17,7 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +smm-$(CONFIG_SPI_FLASH_AMIC) += amic.c smm-$(CONFIG_SPI_FLASH_EON) += eon.c smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c @@ -24,4 +26,4 @@ smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c -endif \ No newline at end of file +endif diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c new file mode 100644 index 0000000..fa17036 --- /dev/null +++ b/src/drivers/spi/amic.c @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2014 Idwer Vollering <vidwer(a)gmail.com> + * + * Based on winbond.c + * + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* A25L-specific commands */ +#define CMD_A25_WREN 0x06 /* Write Enable */ +#define CMD_A25_WRDI 0x04 /* Write Disable */ +#define CMD_A25_RDSR 0x05 /* Read Status Register */ +#define CMD_A25_WRSR 0x01 /* Write Status Register */ +#define CMD_A25_READ 0x03 /* Read Data Bytes */ +#define CMD_A25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_A25_PP 0x02 /* Page Program */ +#define CMD_A25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_A25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_A25_CE 0xc7 /* Chip Erase */ +#define CMD_A25_DP 0xb9 /* Deep Power-down */ +#define CMD_A25_RES 0xab /* Release from DP, and Read Signature */ + +struct amic_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct amic_spi_flash { + struct spi_flash flash; + const struct amic_spi_flash_params *params; +}; + +static inline struct amic_spi_flash * +to_amic_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct amic_spi_flash, flash); +} + +static const struct amic_spi_flash_params amic_spi_flash_table[] = { + { + .id = 0x3016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "A25L032", + }, +}; + +static int amic_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct amic_spi_flash *amic = to_amic_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << amic->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_A25_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = spi_flash_cmd(flash->spi, CMD_A25_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: AMIC Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "SF: AMIC: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int amic_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_A25_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_amic(struct spi_slave *spi, u8 *idcode) +{ + const struct amic_spi_flash_params *params; + unsigned page_size; + struct amic_spi_flash *amic; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(amic_spi_flash_table); i++) { + params = &amic_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(amic_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported AMIC ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + amic = malloc(sizeof(struct amic_spi_flash)); + if (!amic) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + amic->params = params; + amic->flash.spi = spi; + amic->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + amic->flash.write = amic_write; + amic->flash.erase = amic_erase; +#if CONFIG_SPI_FLASH_NO_FAST_READ + amic->flash.read = spi_flash_cmd_read_slow; +#else + amic->flash.read = spi_flash_cmd_read_fast; +#endif + amic->flash.sector_size = (1 << amic->params->l2_page_size) * + amic->params->pages_per_sector; + amic->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &amic->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index ada4f3a..63093d2 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -218,6 +218,9 @@ static struct { struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); } flashes[] = { /* Keep it sorted by define name */ +#if CONFIG_SPI_FLASH_AMIC + { 0, 0x37, spi_flash_probe_amic, }, +#endif #if CONFIG_SPI_FLASH_EON { 0, 0x1c, spi_flash_probe_eon, }, #endif diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..fd5c7a8 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -72,6 +72,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, /* Manufacturer-specific probe functions */ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_amic(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);

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Patch merged into coreboot/master: f15b070 ibexpeak/azalia: Remove C4-register extended init.
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit f15b070e892a327a47311866a88c302e84830deb Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Jan 28 14:28:49 2014 +0100 ibexpeak/azalia: Remove C4-register extended init. This sequence was derived from BD82X6X and on ibexpeak it inadvertently disables interrupts. In older kernels it wasn't a problem but in new kernel it makes codec probe fail. Change-Id: I40184ae8c4cfe758869af1a1565b88f0a238150e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5074 for details. -gerrit

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Patch merged into coreboot/master: e5e516a ibexpeak/sata: Add PCI ID from Easynote LM.
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit e5e516aee35fbb9b3f008bfbcd8298474ee0896e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 18:04:05 2014 +0100 ibexpeak/sata: Add PCI ID from Easynote LM. Change-Id: I979a40ad3692cd474920f3ee5c6b10c41f75bfdb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5256 for details. -gerrit

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Patch set updated for coreboot: 178603a nehalem: Make SPD address map into parameter.
by Vladimir Serbinenko 16 Feb '14

16 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5253 -gerrit commit 178603aaafb3c0066147b31367323cf5fc52b91f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 17:22:26 2014 +0100 nehalem: Make SPD address map into parameter. It's mobo dependent. Change-Id: I7a9ba0fb7374a61178e9282acd8f10098435f1fd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 3 ++- src/northbridge/intel/nehalem/raminit.c | 8 ++++---- src/northbridge/intel/nehalem/raminit.h | 2 +- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f0874d3..07687b8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -207,6 +207,7 @@ void main(unsigned long bist) { u32 reg32; int s3resume = 0; + const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; timestamp_init(rdtsc ()); @@ -286,7 +287,7 @@ void main(unsigned long bist) timestamp_add_now(TS_BEFORE_INITRAM); - raminit(s3resume); + raminit(s3resume, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a855982..c503555 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3810,7 +3810,7 @@ set_fsb_frequency (void) } #endif -void raminit(const int s3resume) +void raminit(const int s3resume, const u8 *spd_addrmap) { unsigned channel, slot, lane, rank; int i; @@ -3956,10 +3956,10 @@ void raminit(const int s3resume) 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95 }; - if (slot) + if (!spd_addrmap[2 * channel + slot]) continue; for (try = 0; try < 5; try++) { - v = smbus_read_byte(0x50 + channel, + v = smbus_read_byte(spd_addrmap[2 * channel + slot], DEVICE_TYPE); if (v >= 0) break; @@ -3973,7 +3973,7 @@ void raminit(const int s3resume) gav(info. spd[channel][0][useful_addresses [addr]] = - smbus_read_byte(0x50 + channel, + smbus_read_byte(spd_addrmap[2 * channel + slot], useful_addresses [addr])); if (info.spd[channel][0][DEVICE_TYPE] != 11) diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h index b66b60e..381c317 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/nehalem/raminit.h @@ -22,6 +22,6 @@ #include "nehalem.h" -void raminit(int s3resume); +void raminit(const int s3resume, const u8 *spd_addrmap); #endif /* RAMINIT_H */

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coreboot-gerrit February 2014