coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 2441fcb intel/jarrell: Fix missing include
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5228 -gerrit commit 2441fcb37421ee001fa053dab46ecb3a7c84bd30 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 07:20:13 2014 +0200 intel/jarrell: Fix missing include To unconditionally get cmos_read(). Change-Id: I0af0e85c8a1f42113bd32b51c4e29e86b3c28112 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/jarrell/watchdog.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..7f7a039 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -1,4 +1,5 @@ #include <device/pnp_def.h> +#include <pc80/mc146818rtc.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) #define NSC_WDBASE 0x600

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Patch set updated for coreboot: c69acf2 jarrell: Fix missing include
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5228 -gerrit commit c69acf2172feef9f84e0505f0f1165fdf58b18da Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 07:20:13 2014 +0200 jarrell: Fix missing include To unconditionally get cmos_read(). Change-Id: I0af0e85c8a1f42113bd32b51c4e29e86b3c28112 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/jarrell/watchdog.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/jarrell/watchdog.c b/src/mainboard/intel/jarrell/watchdog.c index f7c42ca..7f7a039 100644 --- a/src/mainboard/intel/jarrell/watchdog.c +++ b/src/mainboard/intel/jarrell/watchdog.c @@ -1,4 +1,5 @@ #include <device/pnp_def.h> +#include <pc80/mc146818rtc.h> #define NSC_WD_DEV PNP_DEV(0x2e, 0xa) #define NSC_WDBASE 0x600

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Patch merged into coreboot/master: 118f351 usbdebug: Remove EHCI_DEBUG_OFFSET
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 118f35140c10b7616e1b7b3d84a61276c803b088 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 9 19:21:30 2014 +0200 usbdebug: Remove EHCI_DEBUG_OFFSET Read this variable from PCI configuration capabilities list instead. Change-Id: I0cfe981833873397c32cd3aa2af307f35f01784b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5176 for details. -gerrit

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New patch to review for coreboot: e5e516a ibexpeak/sata: Add PCI ID from Easynote LM.
by Vladimir Serbinenko 16 Feb '14

16 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5256 -gerrit commit e5e516aee35fbb9b3f008bfbcd8298474ee0896e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 18:04:05 2014 +0100 ibexpeak/sata: Add PCI ID from Easynote LM. Change-Id: I979a40ad3692cd474920f3ee5c6b10c41f75bfdb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 078dc8e..5f3c4d3 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -263,7 +263,7 @@ static struct device_operations sata_ops = { .ops_pci = &sata_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b2e, 0 }; +static const unsigned short pci_device_ids[] = { 0x3b28, 0x3b29, 0x3b2e, 0 }; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops,

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New patch to review for coreboot: 898f576 lenovo/x201: Fix wrong declaration in devicetree.cb
by Vladimir Serbinenko 16 Feb '14

16 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5255 -gerrit commit 898f576b78b3a6c332aba414e5edf33c4e3bc34c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 18:03:45 2014 +0100 lenovo/x201: Fix wrong declaration in devicetree.cb Change-Id: I90c6ff14ab819368ccc874008a7fb1410a543984 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 37a430c..6c5229b 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -76,7 +76,7 @@ chip northbridge/intel/nehalem end device cpu_cluster 0 on - chip cpu/intel/model_206ax + chip cpu/intel/model_2065x device lapic 0 on end end end

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New patch to review for coreboot: 7a5ed6e bd82x6x, ibexpeak: Unify SPI.
by Vladimir Serbinenko 16 Feb '14

16 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5254 -gerrit commit 7a5ed6e24170a45de09523009f7bad265f11aa5d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 17:13:19 2014 +0100 bd82x6x, ibexpeak: Unify SPI. SPI registers didnt change since ICH8. No need to have separate files for them. Unify. Change-Id: I4e2ac3221b419c007e135c9ee615fc3b84424cbc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/spi.c | 3 +- src/southbridge/intel/ibexpeak/Makefile.inc | 4 +- src/southbridge/intel/ibexpeak/spi.c | 1067 --------------------------- 3 files changed, 4 insertions(+), 1070 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 1f2511e..4f4a38f 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -337,7 +337,8 @@ static inline int get_ich_version(uint16_t device_id) if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) + || device_id == 0x3b07 || device_id == 0x3b09) return 9; return 0; diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index e7f7d99..d02f1a5 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -39,8 +39,8 @@ ramstage-y += ../bd82x6x/reset.c ramstage-y += ../bd82x6x/watchdog.c ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c -ramstage-y += spi.c -smm-$(CONFIG_SPI_FLASH_SMM) += spi.c +ramstage-y += ../bd82x6x/spi.c +smm-$(CONFIG_SPI_FLASH_SMM) += ../bd82x6x/spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c diff --git a/src/southbridge/intel/ibexpeak/spi.c b/src/southbridge/intel/ibexpeak/spi.c deleted file mode 100644 index 7080fe1..0000000 --- a/src/southbridge/intel/ibexpeak/spi.c +++ /dev/null @@ -1,1067 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger - * Copyright (C) 2011 Stefan Tauner - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but without any warranty; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* This file is derived from the flashrom project. */ -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <delay.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci.h> -#include <spi_flash.h> - -#include <spi-generic.h> -#include "pch.h" - -#define min(a, b) ((a)<(b)?(a):(b)) - -#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ -#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) -#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ -#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) - - -#ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !__SMM__ */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - *(targ) = pci_read_config8(dev, reg) -#define pci_read_config_word(dev, reg, targ)\ - *(targ) = pci_read_config16(dev, reg) -#define pci_read_config_dword(dev, reg, targ)\ - *(targ) = pci_read_config32(dev, reg) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* !__SMM__ */ - -static int spi_is_multichip(void); -static struct spi_flash *spi_flash_hwseq(struct spi_slave *spi); - -typedef struct spi_slave ich_spi_slave; - -static int ichspi_lock = 0; - -typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; - -typedef struct ich9_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[5]; - uint32_t _reserved1[3]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __attribute__((packed)) ich9_spi_regs; - -typedef struct ich_spi_controller { - int locked; - int revision; - uint32_t flmap0; - uint32_t hsfs; - - ich9_spi_regs *ich9_spi; - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} ich_spi_controller; - -static ich_spi_controller cntlr; - -enum { - SPIS_SCIP = 0x0001, - SPIS_GRANT = 0x0002, - SPIS_CDS = 0x0004, - SPIS_FCERR = 0x0008, - SSFS_AEL = 0x0010, - SPIS_LOCK = 0x8000, - SPIS_RESERVED_MASK = 0x7ff0, - SSFS_RESERVED_MASK = 0x7fe2 -}; - -enum { - SPIC_SCGO = 0x000002, - SPIC_ACS = 0x000004, - SPIC_SPOP = 0x000008, - SPIC_DBC = 0x003f00, - SPIC_DS = 0x004000, - SPIC_SME = 0x008000, - SSFC_SCF_MASK = 0x070000, - SSFC_RESERVED = 0xf80000 -}; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -enum { - SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, - SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, - SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, - SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 -}; - -#if CONFIG_DEBUG_SPI_FLASH - -static u8 readb_(const void *addr) -{ - u8 v = read8((unsigned long)addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16((unsigned long)addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32((unsigned long)addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, const void *addr) -{ - write8((unsigned long)addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, const void *addr) -{ - write16((unsigned long)addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, const void *addr) -{ - write32((unsigned long)addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8((uint32_t)a) -#define readw_(a) read16((uint32_t)a) -#define readl_(a) read32((uint32_t)a) -#define writeb_(val, addr) write8((uint32_t)addr, val) -#define writew_(val, addr) write16((uint32_t)addr, val) -#define writel_(val, addr) write32((uint32_t)addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void write_reg(const void *value, void *dest, uint32_t size) -{ - const uint8_t *bvalue = value; - uint8_t *bdest = dest; - - while (size >= 4) { - writel_(*(const uint32_t *)bvalue, bdest); - bdest += 4; bvalue += 4; size -= 4; - } - while (size) { - writeb_(*bvalue, bdest); - bdest++; bvalue++; size--; - } -} - -static void read_reg(const void *src, void *value, uint32_t size) -{ - const uint8_t *bsrc = src; - uint8_t *bvalue = value; - - while (size >= 4) { - *(uint32_t *)bvalue = readl_(bsrc); - bsrc += 4; bvalue += 4; size -= 4; - } - while (size) { - *bvalue = readb_(bsrc); - bsrc++; bvalue++; size--; - } -} - -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n"); - return 0; -} - -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - - slave->bus = bus; - slave->cs = cs; - if (cntlr.revision == 9) { - slave->force_programmer_specific = spi_is_multichip (); - slave->programmer_specific_probe = spi_flash_hwseq; - } - return slave; -} - -/* - * Check if this device ID matches one of supported Intel PCH devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static inline int get_ich_version(uint16_t device_id) -{ - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) - return 7; - - if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || - (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && - device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) - || device_id == 0x3b07) - return 9; - - return 0; -} - -void spi_init(void) -{ - int ich_version = 0; - - uint8_t *rcrb; /* Root Complex Register Block */ - uint32_t rcba; /* Root Complex Base Address */ - uint8_t bios_cntl; - device_t dev; - uint32_t ids; - uint16_t vendor_id, device_id; - -#ifdef __SMM__ - dev = PCI_DEV(0, 31, 0); -#else - dev = dev_find_slot(0, PCI_DEVFN(31, 0)); -#endif - pci_read_config_dword(dev, 0, &ids); - vendor_id = ids; - device_id = (ids >> 16); - - if (vendor_id != PCI_VENDOR_ID_INTEL) { - printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); - return; - } - - ich_version = get_ich_version(device_id); - - if (!ich_version) { - printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); - return; - } - - pci_read_config_dword(dev, 0xf0, &rcba); - /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ - rcrb = (uint8_t *)(rcba & 0xffffc000); - cntlr.revision = ich_version; - switch (ich_version) { - case 7: - { - const uint16_t ich7_spibar_offset = 0x3020; - ich7_spi_regs *ich7_spi = - (ich7_spi_regs *)(rcrb + ich7_spibar_offset); - - ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; - cntlr.opmenu = ich7_spi->opmenu; - cntlr.menubytes = sizeof(ich7_spi->opmenu); - cntlr.optype = &ich7_spi->optype; - cntlr.addr = &ich7_spi->spia; - cntlr.data = (uint8_t *)ich7_spi->spid; - cntlr.databytes = sizeof(ich7_spi->spid); - cntlr.status = (uint8_t *)&ich7_spi->spis; - cntlr.control = &ich7_spi->spic; - cntlr.bbar = &ich7_spi->bbar; - cntlr.preop = &ich7_spi->preop; - break; - } - case 9: - { - const uint16_t ich9_spibar_offset = 0x3800; - ich9_spi_regs *ich9_spi = - (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - uint16_t hsfs; - cntlr.ich9_spi = ich9_spi; - hsfs = readw_(&ich9_spi->hsfs); - ichspi_lock = hsfs & HSFS_FLOCKDN; - cntlr.hsfs = hsfs; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - - if (cntlr.hsfs & HSFS_FDV) - { - writel_ (4, &ich9_spi->fdoc); - cntlr.flmap0 = readl_(&ich9_spi->fdod); - } - break; - } - default: - printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); - } - - ich_set_bbar(0); - - /* Disable the BIOS write protect so write commands are allowed. */ - pci_read_config_byte(dev, 0xdc, &bios_cntl); - switch (ich_version) { - case 9: - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - break; - - default: - break; - } - pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); -} - -int spi_claim_bus(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - -void spi_cs_activate(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - -typedef struct spi_transaction { - const uint8_t *out; - uint32_t bytesout; - uint8_t *in; - uint32_t bytesin; - uint8_t type; - uint8_t opcode; - uint32_t offset; -} spi_transaction; - -static inline void spi_use_out(spi_transaction *trans, unsigned bytes) -{ - trans->out += bytes; - trans->bytesout -= bytes; -} - -static inline void spi_use_in(spi_transaction *trans, unsigned bytes) -{ - trans->in += bytes; - trans->bytesin -= bytes; -} - -static void spi_setup_type(spi_transaction *trans) -{ - trans->type = 0xFF; - - /* Try to guess spi type from read/write sizes. */ - if (trans->bytesin == 0) { - if (trans->bytesout > 4) - /* - * If bytesin = 0 and bytesout > 4, we presume this is - * a write data operation, which is accompanied by an - * address. - */ - trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; - else - trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; - return; - } - - if (trans->bytesout == 1) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; - return; - } - - if (trans->bytesout == 4) { /* and bytesin is > 0 */ - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - } - - /* Fast read command is called with 5 bytes instead of 4 */ - if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { - trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; - --trans->bytesout; - } -} - -static int spi_setup_opcode(spi_transaction *trans) -{ - uint16_t optypes; - uint8_t opmenu[cntlr.menubytes]; - - trans->opcode = trans->out[0]; - spi_use_out(trans, 1); - if (!ichspi_lock) { - /* The lock is off, so just use index 0. */ - writeb_(trans->opcode, cntlr.opmenu); - optypes = readw_(cntlr.optype); - optypes = (optypes & 0xfffc) | (trans->type & 0x3); - writew_(optypes, cntlr.optype); - return 0; - } else { - /* The lock is on. See if what we need is on the menu. */ - uint8_t optype; - uint16_t opcode_index; - - /* Write Enable is handled as atomic prefix */ - if (trans->opcode == SPI_OPCODE_WREN) - return 0; - - read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); - for (opcode_index = 0; opcode_index < cntlr.menubytes; - opcode_index++) { - if (opmenu[opcode_index] == trans->opcode) - break; - } - - if (opcode_index == cntlr.menubytes) { - printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", - trans->opcode); - return -1; - } - - optypes = readw_(cntlr.optype); - optype = (optypes >> (opcode_index * 2)) & 0x3; - if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && - optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && - trans->bytesout >= 3) { - /* We guessed wrong earlier. Fix it up. */ - trans->type = optype; - } - if (optype != trans->type) { - printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", - optype); - return -1; - } - return opcode_index; - } -} - -static int spi_setup_offset(spi_transaction *trans) -{ - /* Separate the SPI address and data. */ - switch (trans->type) { - case SPI_OPCODE_TYPE_READ_NO_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: - return 0; - case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: - case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: - trans->offset = ((uint32_t)trans->out[0] << 16) | - ((uint32_t)trans->out[1] << 8) | - ((uint32_t)trans->out[2] << 0); - spi_use_out(trans, 3); - return 1; - default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); - return -1; - } -} - -/* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set - * below is True) or 0. In case the wait was for the bit(s) to set - write - * those bits back, which would cause resetting them. - * - * Return the last read status value on success or -1 on failure. - */ -static int ich_status_poll(u16 bitmask, int wait_til_set) -{ - int timeout = 6000; /* This will result in 60 ms */ - u16 status = 0; - - while (timeout--) { - status = readw_(cntlr.status); - if (wait_til_set ^ ((status & bitmask) == 0)) { - if (wait_til_set) - writew_((status & bitmask), cntlr.status); - return status; - } - udelay(10); - } - - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", - status, bitmask); - return -1; -} - -static int spi_is_multichip (void) -{ - if (cntlr.revision != 9) - return 0; - if (!(cntlr.hsfs & HSFS_FDV)) - return 0; - return !!((cntlr.flmap0 >> 8) & 3); -} - -int spi_xfer(struct spi_slave *slave, const void *dout, - unsigned int bitsout, void *din, unsigned int bitsin) -{ - uint16_t control; - int16_t opcode_index; - int with_address; - int status; - - spi_transaction trans = { - dout, bitsout / 8, - din, bitsin / 8, - 0xff, 0xff, 0 - }; - - /* There has to always at least be an opcode. */ - if (!bitsout || !dout) { - printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); - return -1; - } - /* Make sure if we read something we have a place to put it. */ - if (bitsin != 0 && !din) { - printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); - return -1; - } - /* Right now we don't support writing partial bytes. */ - if (bitsout % 8 || bitsin % 8) { - printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); - return -1; - } - - if (ich_status_poll(SPIS_SCIP, 0) == -1) - return -1; - - writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); - - spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) - return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) - return -1; - - if (trans.opcode == SPI_OPCODE_WREN) { - /* - * Treat Write Enable as Atomic Pre-Op if possible - * in order to prevent the Management Engine from - * issuing a transaction between WREN and DATA. - */ - if (!ichspi_lock) - writew_(trans.opcode, cntlr.preop); - return 0; - } - - /* Preset control fields */ - control = SPIC_SCGO | ((opcode_index & 0x07) << 4); - - /* Issue atomic preop cycle if needed */ - if (readw_(cntlr.preop)) - control |= SPIC_ACS; - - if (!trans.bytesout && !trans.bytesin) { - /* SPI addresses are 24 bit only */ - if (with_address) - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - /* - * This is a 'no data' command (like Write Enable), its - * bitesout size was 1, decremented to zero while executing - * spi_setup_opcode() above. Tell the chip to send the - * command. - */ - writew_(control, cntlr.control); - - /* wait for the result */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); - return -1; - } - - return 0; - } - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); - return -1; - } - - /* - * Read or write up to databytes bytes at a time until everything has - * been sent. - */ - while (trans.bytesout || trans.bytesin) { - uint32_t data_length; - - /* SPI addresses are 24 bit only */ - writel_(trans.offset & 0x00FFFFFF, cntlr.addr); - - if (trans.bytesout) - data_length = min(trans.bytesout, cntlr.databytes); - else - data_length = min(trans.bytesin, cntlr.databytes); - - /* Program data into FDATA0 to N */ - if (trans.bytesout) { - write_reg(trans.out, cntlr.data, data_length); - spi_use_out(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - - /* Add proper control fields' values */ - control &= ~((cntlr.databytes - 1) << 8); - control |= SPIC_DS; - control |= (data_length - 1) << 8; - - /* write it */ - writew_(control, cntlr.control); - - /* Wait for Cycle Done Status or Flash Cycle Error. */ - status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); - if (status == -1) - return -1; - - if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); - return -1; - } - - if (trans.bytesin) { - read_reg(cntlr.data, trans.in, data_length); - spi_use_in(&trans, data_length); - if (with_address) - trans.offset += data_length; - } - } - - /* Clear atomic preop now that xfer is done */ - writew_(0, cntlr.preop); - - return 0; -} - -/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ -static void ich_hwseq_set_addr(uint32_t addr) -{ - uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF; - writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr); -} - -/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. - Resets all error flags in HSFS. - Returns 0 if the cycle completes successfully without errors within - timeout us, 1 on errors. */ -static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len) -{ - uint16_t hsfs; - uint32_t addr; - - timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) & - (HSFS_FDONE | HSFS_FCERR)) == 0) && - --timeout) { - udelay(8); - } - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); - - if (!timeout) { - uint16_t hsfc; - addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr.ich9_spi->hsfc); - printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and " - "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", - addr, addr + len - 1, addr, len - 1, - hsfc, hsfs); - return 1; - } - - if (hsfs & HSFS_FCERR) { - uint16_t hsfc; - addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF; - hsfc = readw_(&cntlr.ich9_spi->hsfc); - printk(BIOS_ERR, "Transaction error between offset 0x%08x and " - "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", - addr, addr + len - 1, addr, len - 1, - hsfc, hsfs); - return 1; - } - return 0; -} - - -static int ich_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) -{ - u32 start, end, erase_size; - int ret; - uint16_t hsfc; - uint16_t timeout = 1000 * 60; - - erase_size = flash->sector_size; - if (offset % erase_size || len % erase_size) { - printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); - return -1; - } - - flash->spi->rw = SPI_WRITE_FLAG; - ret = spi_claim_bus(flash->spi); - if (ret) { - printk(BIOS_ERR, "SF: Unable to claim SPI bus\n"); - return ret; - } - - start = offset; - end = start + len; - - while (offset < end) { - /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); - - ich_hwseq_set_addr(offset); - - offset += erase_size; - - hsfc = readw_(&cntlr.ich9_spi->hsfc); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ - hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.ich9_spi->hsfc); - if (ich_hwseq_wait_for_cycle_complete(timeout, len)) - { - printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); - ret = -1; - goto out; - } - } - - printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); - -out: - spi_release_bus(flash->spi); - return ret; -} - -static void ich_read_data(uint8_t *data, int len) -{ - int i; - uint32_t temp32 = 0; - - for (i = 0; i < len; i++) { - if ((i % 4) == 0) - temp32 = readl_(cntlr.data + i); - - data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; - } -} - -static int ich_hwseq_read(struct spi_flash *flash, - u32 addr, size_t len, void *buf) -{ - uint16_t hsfc; - uint16_t timeout = 100 * 60; - uint8_t block_len; - - if (addr + len > flash->size) { - printk (BIOS_ERR, - "Attempt to read %x-%x which is out of chip\n", - (unsigned) addr, - (unsigned) addr+(unsigned) len); - return -1; - } - - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); - - while (len > 0) { - block_len = min(len, cntlr.databytes); - if (block_len > (~addr & 0xff)) - block_len = (~addr & 0xff) + 1; - ich_hwseq_set_addr(addr); - hsfc = readw_(&cntlr.ich9_spi->hsfc); - hsfc &= ~HSFC_FCYCLE; /* set read operation */ - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.ich9_spi->hsfc); - - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) - return 1; - ich_read_data(buf, block_len); - addr += block_len; - buf += block_len; - len -= block_len; - } - return 0; -} - -/* Fill len bytes from the data array into the fdata/spid registers. - * - * Note that using len > flash->pgm->spi.max_data_write will trash the registers - * following the data registers. - */ -static void ich_fill_data(const uint8_t *data, int len) -{ - uint32_t temp32 = 0; - int i; - - if (len <= 0) - return; - - for (i = 0; i < len; i++) { - if ((i % 4) == 0) - temp32 = 0; - - temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); - - if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, cntlr.data + (i - (i % 4))); - } - i--; - if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, cntlr.data + (i - (i % 4))); -} - -static int ich_hwseq_write(struct spi_flash *flash, - u32 addr, size_t len, const void *buf) -{ - uint16_t hsfc; - uint16_t timeout = 100 * 60; - uint8_t block_len; - uint32_t start = addr; - - if (addr + len > flash->size) { - printk (BIOS_ERR, - "Attempt to write 0x%x-0x%x which is out of chip\n", - (unsigned)addr, (unsigned) (addr+len)); - return -1; - } - - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs); - - while (len > 0) { - block_len = min(len, cntlr.databytes); - if (block_len > (~addr & 0xff)) - block_len = (~addr & 0xff) + 1; - - ich_hwseq_set_addr(addr); - - ich_fill_data(buf, block_len); - hsfc = readw_(&cntlr.ich9_spi->hsfc); - hsfc &= ~HSFC_FCYCLE; /* clear operation */ - hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ - hsfc &= ~HSFC_FDBC; /* clear byte count */ - /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); - hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.ich9_spi->hsfc); - - if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) - { - printk (BIOS_ERR, "SF: write failure at %x\n", - addr); - return -1; - } - addr += block_len; - buf += block_len; - len -= block_len; - } - printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", - (unsigned) (addr - start), start); - return 0; -} - - -static struct spi_flash *spi_flash_hwseq(struct spi_slave *spi) -{ - struct spi_flash *flash = NULL; - uint32_t flcomp; - - flash = malloc(sizeof(*flash)); - if (!flash) { - printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); - return NULL; - } - - flash->spi = spi; - flash->name = "Opaque HW-sequencing"; - - flash->write = ich_hwseq_write; - flash->erase = ich_hwseq_erase; - flash->read = ich_hwseq_read; - ich_hwseq_set_addr (0); - switch ((cntlr.hsfs >> 3) & 3) - { - case 0: - flash->sector_size = 256; - break; - case 1: - flash->sector_size = 4096; - break; - case 2: - flash->sector_size = 8192; - break; - case 3: - flash->sector_size = 65536; - break; - } - - writel_ (0x1000, &cntlr.ich9_spi->fdoc); - flcomp = readl_(&cntlr.ich9_spi->fdod); - - flash->size = 1 << (19 + (flcomp & 7)); - - if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3)) - flash->size += 1 << (19 + ((flcomp >> 3) & 7)); - printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size); - - return flash; -}

1 0

New patch to review for coreboot: 0c4f46c nehalem: Make SPD address map into parameter.
by Vladimir Serbinenko 16 Feb '14

16 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5253 -gerrit commit 0c4f46c094d5052dd2a7af3b042f56bd86f3939a Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 16 17:22:26 2014 +0100 nehalem: Make SPD address map into parameter. It's mobo dependent. Change-Id: I7a9ba0fb7374a61178e9282acd8f10098435f1fd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 3 ++- src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/raminit.c | 8 ++++---- src/northbridge/intel/nehalem/raminit.h | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index f0874d3..07687b8 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -207,6 +207,7 @@ void main(unsigned long bist) { u32 reg32; int s3resume = 0; + const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; timestamp_init(rdtsc ()); @@ -286,7 +287,7 @@ void main(unsigned long bist) timestamp_add_now(TS_BEFORE_INITRAM); - raminit(s3resume); + raminit(s3resume, spd_addrmap); timestamp_add_now(TS_AFTER_INITRAM); diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 69d0eee..4cbaf22 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -23,6 +23,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select VGA + select INTEL_EDID if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a855982..c503555 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3810,7 +3810,7 @@ set_fsb_frequency (void) } #endif -void raminit(const int s3resume) +void raminit(const int s3resume, const u8 *spd_addrmap) { unsigned channel, slot, lane, rank; int i; @@ -3956,10 +3956,10 @@ void raminit(const int s3resume) 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94, 0x95 }; - if (slot) + if (!spd_addrmap[2 * channel + slot]) continue; for (try = 0; try < 5; try++) { - v = smbus_read_byte(0x50 + channel, + v = smbus_read_byte(spd_addrmap[2 * channel + slot], DEVICE_TYPE); if (v >= 0) break; @@ -3973,7 +3973,7 @@ void raminit(const int s3resume) gav(info. spd[channel][0][useful_addresses [addr]] = - smbus_read_byte(0x50 + channel, + smbus_read_byte(spd_addrmap[2 * channel + slot], useful_addresses [addr])); if (info.spd[channel][0][DEVICE_TYPE] != 11) diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h index b66b60e..381c317 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/nehalem/raminit.h @@ -22,6 +22,6 @@ #include "nehalem.h" -void raminit(int s3resume); +void raminit(const int s3resume, const u8 *spd_addrmap); #endif /* RAMINIT_H */

1 0

New patch to review for coreboot: c2bcf2e src/drivers/spi: introduce AMIC support
by Idwer Vollering 16 Feb '14

16 Feb '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5252 -gerrit commit c2bcf2ee46af585949d2a414ac5eba49d1e0b28e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Sun Feb 16 00:32:13 2014 +0000 src/drivers/spi: introduce AMIC support Add support for the AMIC A25L032 chip. Change-Id: Ie8d441a923c6fbd18c16440b4571321652d934d5 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- src/drivers/spi/Kconfig | 8 ++ src/drivers/spi/Makefile.inc | 4 +- src/drivers/spi/amic.c | 179 +++++++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 3 + src/drivers/spi/spi_flash_internal.h | 1 + 5 files changed, 194 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index a99199a..c5db969 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -31,6 +31,14 @@ config SPI_FLASH_SMM help Select this option if you want SPI flash support in SMM. +config SPI_FLASH_AMIC + bool + default y + depends on SPI_FLASH + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by AMIC. + config SPI_FLASH_EON bool default y diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 1a34ab5..641ad8d 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -2,6 +2,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +ramstage-$(CONFIG_SPI_FLASH_AMIC) += amic.c ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c @@ -16,6 +17,7 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +smm-$(CONFIG_SPI_FLASH_AMIC) += amic.c smm-$(CONFIG_SPI_FLASH_EON) += eon.c smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c @@ -24,4 +26,4 @@ smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c -endif \ No newline at end of file +endif diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c new file mode 100644 index 0000000..ceb153b --- /dev/null +++ b/src/drivers/spi/amic.c @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2014 Idwer Vollering <vidwer(a)gmail.com> + * + * Based on winbond.c + * + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* A25L-specific commands */ +#define CMD_A25_WREN 0x06 /* Write Enable */ +#define CMD_A25_WRDI 0x04 /* Write Disable */ +#define CMD_A25_RDSR 0x05 /* Read Status Register */ +#define CMD_A25_WRSR 0x01 /* Write Status Register */ +#define CMD_A25_READ 0x03 /* Read Data Bytes */ +#define CMD_A25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_A25_PP 0x02 /* Page Program */ +#define CMD_A25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_A25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_A25_CE 0xc7 /* Chip Erase */ +#define CMD_A25_DP 0xb9 /* Deep Power-down */ +#define CMD_A25_RES 0xab /* Release from DP, and Read Signature */ + +struct amic_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct amic_spi_flash { + struct spi_flash flash; + const struct amic_spi_flash_params *params; +}; + +static inline struct amic_spi_flash * +to_amic_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct amic_spi_flash, flash); +} + +static const struct amic_spi_flash_params amic_spi_flash_table[] = { + { + .id = 0x3016, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "A25L032", + }, +}; + +static int amic_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct amic_spi_flash *amic = to_amic_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << amic->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_A25_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = spi_flash_cmd(flash->spi, CMD_A25_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: AMIC Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "SF: AMIC: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int amic_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_A25_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_amic(struct spi_slave *spi, u8 *idcode) +{ + const struct amic_spi_flash_params *params; + unsigned page_size; + struct amic_spi_flash *amic; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(amic_spi_flash_table); i++) { + params = &amic_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(amic_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported AMIC ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + amic = malloc(sizeof(struct amic_spi_flash)); + if (!amic) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + amic->params = params; + amic->flash.spi = spi; + amic->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + amic->flash.write = amic_write; + amic->flash.erase = amic_erase; +#if CONFIG_SPI_FLASH_NO_FAST_READ + amic->flash.read = spi_flash_cmd_read_slow; +#else + amic->flash.read = spi_flash_cmd_read_fast; +#endif + amic->flash.sector_size = (1 << amic->params->l2_page_size) * + amic->params->pages_per_sector; + amic->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &amic->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index ada4f3a..63093d2 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -218,6 +218,9 @@ static struct { struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); } flashes[] = { /* Keep it sorted by define name */ +#if CONFIG_SPI_FLASH_AMIC + { 0, 0x37, spi_flash_probe_amic, }, +#endif #if CONFIG_SPI_FLASH_EON { 0, 0x1c, spi_flash_probe_eon, }, #endif diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..fd5c7a8 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -72,6 +72,7 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, /* Manufacturer-specific probe functions */ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_amic(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);

1 0

Patch set updated for coreboot: 6c07ada uart8250: Move under drivers/uart
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5236 -gerrit commit 6c07ada88ccfd2911f440dff84b87ac6c9d710aa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 30 15:45:16 2014 +0200 uart8250: Move under drivers/uart Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 2 +- src/drivers/uart/Makefile.inc | 12 ++++ src/drivers/uart/uart8250io.c | 123 ++++++++++++++++++++++++++++++++++++ src/drivers/uart/uart8250mem.c | 133 +++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 4 -- src/lib/uart8250.c | 123 ------------------------------------ src/lib/uart8250mem.c | 133 --------------------------------------- 7 files changed, 269 insertions(+), 261 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 5a88146..5b88a98 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -33,7 +33,7 @@ #include <console/util.c> #if CONFIG_CONSOLE_SERIAL8250 -#include "lib/uart8250.c" +#include "drivers/uart/uart8250io.c" #endif #if CONFIG_CONSOLE_NE2K #include "drivers/net/ne2k.c" diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 9a8121e..aec6a58 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,3 +1,15 @@ +ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +romstage-y += uart8250io.c +ramstage-y += uart8250io.c +smm-$(CONFIG_DEBUG_SMI) += uart8250io.c +endif + +ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +romstage-y += uart8250mem.c +ramstage-y += uart8250mem.c +smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c +endif + ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) ifeq ($(CONFIG_DRIVERS_UART_PL011),y) diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c new file mode 100644 index 0000000..efbaaba --- /dev/null +++ b/src/drivers/uart/uart8250io.c @@ -0,0 +1,123 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <trace.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static int uart8250_can_tx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_THRE; +} + +static void uart8250_tx_byte(unsigned base_port, unsigned char data) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_tx_byte(base_port)); + outb(data, base_port + UART_TBR); +} + +static void uart8250_tx_flush(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); +} + +static int uart8250_can_rx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_rx_byte(base_port)); + + if (i) + return inb(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_init(unsigned base_port, unsigned divisor) +{ + DISABLE_TRACE; + /* Disable interrupts */ + outb(0x0, base_port + UART_IER); + /* Enable FIFOs */ + outb(UART_FCR_FIFO_EN, base_port + UART_FCR); + + /* assert DTR and RTS so the other end is happy */ + outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); + + /* DLAB on */ + outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + outb(divisor & 0xFF, base_port + UART_DLL); + outb((divisor >> 8) & 0xFF, base_port + UART_DLM); + + /* Set to 3 for 8N1 */ + outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); + ENABLE_TRACE; +} + +/* FIXME: Needs uart index from Kconfig. + * Already use array as a work-around for ROMCC. + */ +static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; + +void uart_init(void) +{ + unsigned int div = uart_divisor(115200); + uart8250_init(bases[0], div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(bases[0], data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(bases[0]); +} + +int uart_can_rx_byte(void) +{ + return uart8250_can_rx_byte(bases[0]); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(bases[0]); +} diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c new file mode 100644 index 0000000..c9821c9 --- /dev/null +++ b/src/drivers/uart/uart8250mem.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <delay.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static int uart8250_mem_can_tx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_THRE; +} + +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_tx_byte(base_port)) + udelay(1); + write8(base_port + UART_TBR, data); +} + +static void uart8250_mem_tx_flush(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) + udelay(1); +} + +static int uart8250_mem_can_rx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_mem_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_rx_byte(base_port)) + udelay(1); + if (i) + return read8(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_mem_init(unsigned base_port, unsigned divisor) +{ + /* Disable interrupts */ + write8(base_port + UART_IER, 0x0); + /* Enable FIFOs */ + write8(base_port + UART_FCR, UART_FCR_FIFO_EN); + + /* Assert DTR and RTS so the other end is happy */ + write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); + + /* DLAB on */ + write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + write8(base_port + UART_DLL, divisor & 0xFF); + write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); + + /* Set to 3 for 8N1 */ + write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); +} + + +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} + +int uart_can_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0; + return uart8250_mem_can_rx_byte(base); +} + +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 076bdd7..941c0ba 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -45,8 +45,6 @@ romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -86,8 +84,6 @@ ramstage-y += stack.c ramstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += clog2.c romstage-y += clog2.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c deleted file mode 100644 index 38b1b7f..0000000 --- a/src/lib/uart8250.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <trace.h> -#include "drivers/uart/uart8250reg.h" - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - * - * Estimated that inb() from UART takes 1 microsecond. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static int uart8250_can_tx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_THRE; -} - -static void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_tx_byte(base_port)); - outb(data, base_port + UART_TBR); -} - -static void uart8250_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); -} - -static int uart8250_can_rx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_rx_byte(base_port)); - - if (i) - return inb(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_init(unsigned base_port, unsigned divisor) -{ - DISABLE_TRACE; - /* Disable interrupts */ - outb(0x0, base_port + UART_IER); - /* Enable FIFOs */ - outb(UART_FCR_FIFO_EN, base_port + UART_FCR); - - /* assert DTR and RTS so the other end is happy */ - outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); - - /* DLAB on */ - outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - outb(divisor & 0xFF, base_port + UART_DLL); - outb((divisor >> 8) & 0xFF, base_port + UART_DLM); - - /* Set to 3 for 8N1 */ - outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); - ENABLE_TRACE; -} - -/* FIXME: Needs uart index from Kconfig. - * Already use array as a work-around for ROMCC. - */ -static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; - -void uart_init(void) -{ - unsigned int div = uart_divisor(115200); - uart8250_init(bases[0], div); -} - -void uart_tx_byte(unsigned char data) -{ - uart8250_tx_byte(bases[0], data); -} - -unsigned char uart_rx_byte(void) -{ - return uart8250_rx_byte(bases[0]); -} - -int uart_can_rx_byte(void) -{ - return uart8250_can_rx_byte(bases[0]); -} - -void uart_tx_flush(void) -{ - uart8250_tx_flush(bases[0]); -} diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c deleted file mode 100644 index 029d055..0000000 --- a/src/lib/uart8250mem.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <delay.h> -#include "drivers/uart/uart8250reg.h" - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static int uart8250_mem_can_tx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_THRE; -} - -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); - write8(base_port + UART_TBR, data); -} - -static void uart8250_mem_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) - udelay(1); -} - -static int uart8250_mem_can_rx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read8(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned base_port, unsigned divisor) -{ - /* Disable interrupts */ - write8(base_port + UART_IER, 0x0); - /* Enable FIFOs */ - write8(base_port + UART_FCR, UART_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); - - /* DLAB on */ - write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - write8(base_port + UART_DLL, divisor & 0xFF); - write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); -} - - -void uart_init(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - - unsigned div = uart_platform_divisor(); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(unsigned char data) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_byte(base, data); -} - -unsigned char uart_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0xff; - return uart8250_mem_rx_byte(base); -} - -int uart_can_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0; - return uart8250_mem_can_rx_byte(base); -} - -void uart_tx_flush(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_flush(base); -}

1 0

Patch set updated for coreboot: 305ab6d uart8250mem: Unify calls with generic UART
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5235 -gerrit commit 305ab6dd095646b82af90783293cd0904e027e2b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 10:19:23 2014 +0200 uart8250mem: Unify calls with generic UART Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 11 +--- src/console/uart8250mem_console.c | 30 +++-------- src/drivers/oxford/oxpcie/oxpcie.c | 3 +- src/drivers/oxford/oxpcie/oxpcie_early.c | 49 ++++++++++++++---- src/include/console/uart.h | 5 +- src/include/uart8250.h | 50 ------------------ src/lib/uart8250mem.c | 87 ++++++++++++++++---------------- 7 files changed, 96 insertions(+), 139 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 89d7f82..6566b2f 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,20 +26,13 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - void console_tx_byte(unsigned char byte) { if (byte == '\n') console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_byte(byte); @@ -61,7 +54,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_flush(); diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index 3833e47..7e52aed 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -18,47 +18,31 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> -static u32 uart_bar = 0; - -void uartmem_init(void) -{ - uart_bar = uart_mem_init(); -} - -u32 uartmem_getbaseaddr(void) +static void uartmem_init(void) { - return uart_bar; + uart_init(); } static void uartmem_tx_byte(unsigned char data) { - if (!uart_bar) - return; - - uart8250_mem_tx_byte(uart_bar, data); + uart_tx_byte(data); } static void uartmem_tx_flush(void) { - uart8250_mem_tx_flush(uart_bar); + uart_tx_flush(); } static unsigned char uartmem_rx_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_rx_byte(uart_bar); + return uart_rx_byte(); } static int uartmem_tst_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_can_rx_byte(uart_bar); + return uart_can_rx_byte(); } static const struct console_driver uart8250mem_console __console = { diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index f719fc7..0b9081f 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -48,7 +48,8 @@ static void oxford_oxpcie_set_resources(struct device *dev) #if CONFIG_CONSOLE_SERIAL8250MEM /* Re-initialize OXPCIe base address after set_resources */ - uartmem_init(); + u32 mmio_base = pci_read_config32(device, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); #endif } diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 693c1e9..b60cd6c 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -18,12 +18,17 @@ */ #include <stdint.h> +#include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> -#include <uart8250.h> +#include <console/uart.h> #include <device/pci_def.h> +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; + #define PCIE_BRIDGE \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ @@ -35,13 +40,9 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) -#if defined(__PRE_RAM__) -int oxford_oxpcie_present CAR_GLOBAL; - -void oxford_init(void) +static void oxpcie_init_bridge(void) { u16 reg16; - oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -100,7 +101,6 @@ void oxford_init(void) break; default: /* No UART here. */ - oxford_oxpcie_present = 0; return; } @@ -113,16 +113,43 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); - /* Now the UART initialization */ - u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; + car_set_var(oxpcie_present, 1); +} - unsigned div = uart_platform_divisor(); - uart8250_mem_init(uart0_base, div); +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); } +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} #endif +unsigned uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + unsigned uart_platform_divisor(void) { return uart_divisor(4000000); } + +uint32_t uartmem_getbaseaddr(void) +{ + return uart_platform_base(0); +} + +void oxford_init(void) +{ + oxpcie_init_bridge(); + uart_init(); +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ac4455a..5ac7fda 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -30,7 +30,10 @@ int uart_can_rx_byte(void); unsigned uart_divisor(unsigned basefreq); unsigned uart_platform_divisor(void); - +unsigned uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); +void oxford_init(void); +void oxford_remap(u32 new_base); + #endif /* CONSOLE_UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h deleted file mode 100644 index 4d7ebcc..0000000 --- a/src/include/uart8250.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef UART8250_H -#define UART8250_H - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - -#if ((115200 % CONFIG_TTYS0_BAUD) != 0) -#error Bad ttyS0 baud rate -#endif - -#if CONFIG_CONSOLE_SERIAL8250MEM -void uartmem_init(void); - -/* and the same for memory mapped uarts */ -unsigned char uart8250_mem_rx_byte(unsigned base_port); -int uart8250_mem_can_rx_byte(unsigned base_port); -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); -void uart8250_mem_tx_flush(unsigned base_port); -void uart8250_mem_init(unsigned base_port, unsigned divisor); -u32 uart_mem_init(void); - -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; -#endif -#endif - -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - -#include <console/uart.h> - -#endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index cff67d7..029d055 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -19,8 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> -#include <device/device.h> +#include <console/uart.h> #include <delay.h> #include "drivers/uart/uart8250reg.h" @@ -33,42 +32,32 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static inline int uart8250_mem_can_tx_byte(unsigned base_port) +static int uart8250_mem_can_tx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_THRE; } -static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_tx_byte(base_port)) udelay(1); + write8(base_port + UART_TBR, data); } -static inline void uart8250_mem_wait_until_sent(unsigned base_port) +static void uart8250_mem_tx_flush(unsigned base_port) { unsigned long int i = FIFO_TIMEOUT; while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) udelay(1); } -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_mem_wait_to_tx_byte(base_port); - write8(base_port + UART_TBR, data); -} - -void uart8250_mem_tx_flush(unsigned base_port) -{ - uart8250_mem_wait_until_sent(base_port); -} - -int uart8250_mem_can_rx_byte(unsigned base_port) +static int uart8250_mem_can_rx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_mem_rx_byte(unsigned base_port) +static unsigned char uart8250_mem_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base_port)) @@ -79,7 +68,7 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port) return 0x0; } -void uart8250_mem_init(unsigned base_port, unsigned divisor) +static void uart8250_mem_init(unsigned base_port, unsigned divisor) { /* Disable interrupts */ write8(base_port + UART_IER, 0x0); @@ -100,35 +89,45 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -u32 uart_mem_init(void) -{ - u32 uart_bar = 0; - unsigned div = uart_platform_divisor(); - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; - if (dev) { - struct resource *res = find_resource(dev, 0x10); + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART -#endif +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} - if (uart_bar) - uart8250_mem_init(uart_bar, div); +int uart_can_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0; + return uart8250_mem_can_rx_byte(base); +} - return uart_bar; +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); }

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coreboot-gerrit February 2014