Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4915
-gerrit
commit 188aa23a504e16b1c987e2555548c04882010f39
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Oct 31 10:10:20 2013 -0700
rambi: Enable internal keyboard
The EC LPC init function needs to run to enable the internal keyboard.
I needed this to confirm that it is just USB keyboards that are causing
all sorts of issues.
BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=boot to recovery screen and hit tab
Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175207
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 10 +++++++++-
src/soc/intel/baytrail/southcluster.c | 2 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index e7f86ce..66d98ed 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -38,7 +38,15 @@ chip soc/intel/baytrail
device pci 1e.3 off end # HSUART1
device pci 1e.4 on end # HSUART2
device pci 1e.5 on end # SPI
- device pci 1f.0 on end # LPC Bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC Bridge
device pci 1f.3 off end # SMBus
end
end
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index b16a9cf..a3a1a22 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -321,7 +321,7 @@ static struct device_operations device_ops = {
.enable_resources = NULL,
.init = NULL,
.enable = southcluster_enable_dev,
- .scan_bus = NULL,
+ .scan_bus = scan_static_bus,
.ops_pci = &soc_pci_ops,
};
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4914
-gerrit
commit e52fe8301d4f9f8ae97e9fd15d4ca50e1af58fa3
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Oct 28 16:43:17 2013 -0700
rambi: Enable SATA port
Enable first SATA port in Rambi device tree.
BUG=chrome-os-partner:23643
TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is
detected, and kernel is found + booted.
Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174916
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 3086ebf..e7f86ce 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -1,4 +1,10 @@
chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
device cpu_cluster 0 on
device lapic 0 on end
end
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4912
-gerrit
commit f0f953360c98dad7799860f41107e6ca934cfdb3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Oct 29 17:00:07 2013 -0500
rambi: add all on-board devices
Add the on-board devices in the SoC to the device tree.
Also, disable the unused devices aside from TXE and HDA.
Those particular devices cause the system to shut down
when they are disabled.
BUG=chrome-os-partner:22871
BRANCH=None
TEST=Built and booted through depthcharge. Noted the calls to the
southcluster disable function.
Change-Id: I482c1c9609833054aeb2948144af54b57d3df086
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174645
Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
---
src/mainboard/google/rambi/devicetree.cb | 34 +++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index c6ea97c..3086ebf 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -3,8 +3,36 @@ chip soc/intel/baytrail
device lapic 0 on end
end
device domain 0 on
- device pci 00.0 on end # SoC router
- device pci 02.0 on end # GFX
- device pci 1f.0 on end # LPC Bridge
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 on end # HSUART2
+ device pci 1e.5 on end # SPI
+ device pci 1f.0 on end # LPC Bridge
+ device pci 1f.3 off end # SMBus
end
end
the following patch was just integrated into master:
commit 255753c39a48df9f76e83a1bde90ac7f9867a7e4
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Thu Oct 24 09:59:00 2013 -0700
rambi: Set VBOOT_RAMSTAGE_INDEX to point to ramstage image
The ramstage image is the third image in the partition (after ECRW hash
and depthcharge image).
TEST=Manual. Boot rambi, verify that ramstage image is correctly found:
"RW ramstage image at 0xffb1dc70, 0x0000f391 bytes"
BUG=None.
Change-Id: I628db3daf0b109106c51693960487a0c83b4e9f4
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174540
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/4899 for details.
-gerrit
the following patch was just integrated into master:
commit 7400d7b174e1c5223505abd0a4a7fae5b7899c05
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 10:21:43 2013 -0500
baytrail: add support to run reference code blob
The reference code blob is needed to bootstrap
certain pieces of hardware in bay trail. Provide
the ability to run reference code by loading
the reference code as an rmodule.
Note that support for vboot verification and S3
resume is omitted from this commit.
BUG=chrome-os-partner:22866
BRANCH=None
TEST=Built and booted with refcode loading.
Change-Id: I30334db441a57f4d87b4de6fca0a9a48e1c05c05
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174426
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See http://review.coreboot.org/4898 for details.
-gerrit
the following patch was just integrated into master:
commit b8f64dc31fb25c540ce7d03263c95744a8a0090d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Oct 24 00:05:31 2013 -0500
baytrail: add south cluster fixed resources
The PCU (platform controller unit) contains the
resources and IP blocks that used to reside in the
south bridge. Bay Trail has since renamed it south
cluster. There are quite a few fixed MMIO and I/O
resources. If these aren't added the resource allocator
will freely assign these addresses which causes conflicts
and other subtle bugs.
BUG=chrome-os-partner:23544
BUG=chrome-os-partner:23545
BRANCH=None
TEST=Built and booted through depthcharge. Verified
resource allocation not weird. And no more depthcharge
crashes.
Change-Id: I697fbda4538c03fded293bcb63a5823b1ed150ec
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174421
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See http://review.coreboot.org/4893 for details.
-gerrit
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4585
-gerrit
commit a40dd425bb15e15085941b8bb01c67c500140297
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sun Dec 29 18:13:58 2013 -0500
uart8250.h: Do not guard entire include file by config options
Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or
CONFIG_CONSOLE_SERIAL8250MEM. The config-specific options are already
properly guarded, and there is no need to guard the register and bit
definitions.
Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/include/uart8250.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index bec3637..a3868c5 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -20,8 +20,6 @@
#ifndef UART8250_H
#define UART8250_H
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-
/* Data */
#define UART_RBR 0x00
#define UART_TBR 0x00
@@ -141,6 +139,4 @@ void oxford_init(void);
#endif
#endif
-#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
-
#endif /* UART8250_H */