Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237
-gerrit
commit 2cc918c11f936eb58ed47e34595c0b7ca2a2b76a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Feb 14 12:45:09 2014 +0200
OxPCIe uart: Split PCI bridge control
None of the bridge management here is specific to the PCI UART
device/function. Also the Kconfig variable defaults are not globally
valid but originate from lumpy and/or stumpy devices.
Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/device/pci_early.c | 46 ++++++++++++++++++
src/drivers/Kconfig | 1 +
src/drivers/oxford/oxpcie/Kconfig | 64 ++-----------------------
src/drivers/oxford/oxpcie/oxpcie_early.c | 81 ++++++--------------------------
src/drivers/pci/Kconfig | 31 ++++++++++++
src/drivers/pci/pci_early.c | 58 +++++++++++++++++++++++
src/include/device/pci.h | 6 +++
src/southbridge/intel/bd82x6x/Kconfig | 20 ++++++++
8 files changed, 180 insertions(+), 127 deletions(-)
diff --git a/src/device/pci_early.c b/src/device/pci_early.c
index c15a4d0..fc14356 100644
--- a/src/device/pci_early.c
+++ b/src/device/pci_early.c
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2011 Google Inc
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -66,3 +68,47 @@ unsigned pci_find_capability(device_t dev, unsigned cap)
{
return pci_find_next_capability(dev, cap, 0);
}
+
+void pci_bridge_reset_secondary(device_t p2p_bridge)
+{
+ u16 reg16;
+ /* Disable all access through bridge. */
+ reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+ reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+
+ /* First we reset the secondary bus. */
+ reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+ reg16 |= (1 << 6); /* SRESET */
+ pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+
+ /* Assume we don't have to wait here forever */
+
+ /* Read back and clear reset bit. */
+ reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL);
+ reg16 &= ~(1 << 6); /* SRESET */
+ pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16);
+}
+
+void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary)
+{
+ /* Disable config transaction forwarding. */
+ pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00);
+ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00);
+ /* Enable config transaction forwarding. */
+ pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary);
+ pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary);
+}
+
+void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base)
+{
+ u16 reg16;
+ /* MMIO window behind the bridge. */
+ pci_write_config32(p2p_bridge, PCI_MEMORY_BASE,
+ ((base & 0xffff0000) | ((base >> 16) & 0xff00)));
+
+ /* Enable memory access through bridge */
+ reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND);
+ reg16 |= PCI_COMMAND_MEMORY;
+ pci_write_config16(p2p_bridge, PCI_COMMAND, reg16);
+}
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 01bed21..5d9a801 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -32,6 +32,7 @@ source src/drivers/parade/Kconfig
if PC80_SYSTEM
source src/drivers/pc80/Kconfig
endif
+source src/drivers/pci/Kconfig
source src/drivers/realtek/Kconfig
source src/drivers/sil/Kconfig
source src/drivers/spi/Kconfig
diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig
index 899a153..bd5001c 100644
--- a/src/drivers/oxford/oxpcie/Kconfig
+++ b/src/drivers/oxford/oxpcie/Kconfig
@@ -1,68 +1,10 @@
config DRIVERS_OXFORD_OXPCIE
bool "Oxford OXPCIe952"
default n
+ depends on PCI
select HAVE_UART_MEMORY_MAPPED
+ select EARLY_PCI_BRIDGE
help
Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
- 0xc158 will work.
- NOTE: Right now you have to set the base address of your OXPCIe952
- card to exactly the value that the device allocator would set them
- later on, or serial console functionality will stop as soon as the
- resource allocator assigns a new base address to the device.
-
-config OXFORD_OXPCIE_BRIDGE_BUS
- hex "OXPCIe's PCIe bridge bus number"
- default 0x0
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BRIDGE_DEVICE
- hex "OXPCIe's PCIe bridge device number"
- default 0x1c
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BRIDGE_FUNCTION
- hex "OXPCIe's PCIe bridge function number"
- default 0x2
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BRIDGE_SUBORDINATE
- hex "OXPCIe's PCIe bridge subordinate bus"
- default 0x3
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
- that controls the OXPCIe952 controller first.
-
-config OXFORD_OXPCIE_BASE_ADDRESS
- hex "Base address for rom stage console"
- default 0xe0400000
- depends on DRIVERS_OXFORD_OXPCIE
- help
- While coreboot is executing code from ROM, the coreboot resource
- allocator has not been running yet. Hence PCI devices living behind
- a bridge are not yet visible to the system. In order to use an
- OXPCIe952 based PCIe card, coreboot has to set up a temporary address
- for the OXPCIe952 controller.
-
+ 0xc158 or 0xc11b will work.
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 3fc19c3..9610f3e 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -28,94 +28,43 @@
#include <device/pci_def.h>
static unsigned int oxpcie_present CAR_GLOBAL;
-static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
-static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000;
+static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
+static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000;
-#define PCIE_BRIDGE \
- PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
- CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
- CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
-
-#define OXPCIE_DEVICE \
- PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
-
-#define OXPCIE_DEVICE_3 \
- PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
-
-static void oxpcie_init_bridge(void)
+static int oxpcie_probe(u8 bus, u8 dev, u32 mmio_base, u16 io_base)
{
- u16 reg16;
-
- /* First we reset the secondary bus */
- reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
- reg16 |= (1 << 6); /* SRESET */
- pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
-
- /* Assume we don't have to wait here forever */
-
- /* Read back and clear reset bit. */
- reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
- reg16 &= ~(1 << 6); /* SRESET */
- pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16);
-
- /* Set up subordinate bus number */
- pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00);
- pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00);
- pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS,
- CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
- pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS,
- CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE);
+ pci_devfn_t device = PCI_DEV(bus, dev, 0);
- /* Memory window for the OXPCIe952 card */
- // XXX is the calculation of base and limit correct?
- pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE,
- ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) |
- ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00)));
-
- /* Enable memory access through bridge */
- reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND);
- reg16 |= PCI_COMMAND_MEMORY;
- pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
-
- u32 timeout = 20000; // Timeout in 10s of microseconds.
- u32 id = 0;
- for (;;) {
- id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
- if (!timeout-- || (id != 0 && id != 0xffffffff))
- break;
- udelay(10);
- }
-
- u32 device = OXPCIE_DEVICE; /* unknown default */
+ u32 id = pci_read_config32(device, PCI_VENDOR_ID);
switch (id) {
- case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+ case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */
/* On this device function 0 is the parallel port, and
* function 3 is the serial port. So let's go look for
* the UART.
*/
- id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+ device = PCI_DEV(bus, dev, 3);
+ id = pci_read_config32(device, PCI_VENDOR_ID);
if (id != 0xc11b1415)
- return;
- device = OXPCIE_DEVICE_3;
+ return -1;
break;
+ case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */
case 0xc1581415: /* e.g. Startech MPEX2S952 */
- device = OXPCIE_DEVICE;
break;
default:
/* No UART here. */
- return;
+ return -1;
}
/* Setup base address on device */
- pci_write_config32(device, PCI_BASE_ADDRESS_0,
- CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
+ pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base);
/* Enable memory on device */
- reg16 = pci_read_config16(device, PCI_COMMAND);
+ u16 reg16 = pci_read_config16(device, PCI_COMMAND);
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(device, PCI_COMMAND, reg16);
car_set_var(oxpcie_present, 1);
+ return 0;
}
static int oxpcie_uart_active(void)
@@ -152,6 +101,6 @@ unsigned int uart_platform_refclk(void)
void oxford_init(void)
{
- oxpcie_init_bridge();
+ pci_bridge_early_init(&oxpcie_probe);
uart_init();
}
diff --git a/src/drivers/pci/Kconfig b/src/drivers/pci/Kconfig
new file mode 100644
index 0000000..bb6d2bf
--- /dev/null
+++ b/src/drivers/pci/Kconfig
@@ -0,0 +1,31 @@
+config EARLY_PCI_BRIDGE
+ bool "Early PCI bridge"
+ depends on PCI
+ default n
+ help
+ While coreboot is executing code from ROM, the coreboot resource
+ allocator has not been running yet. Hence PCI devices living behind
+ a bridge are not yet visible to the system.
+
+ This option enables static configuration for a single pre-defined
+ PCI bridge function on bus 0.
+
+if EARLY_PCI_BRIDGE
+
+config EARLY_PCI_BRIDGE_DEVICE
+ hex "bridge device"
+ default 0x0
+
+config EARLY_PCI_BRIDGE_FUNCTION
+ hex "bridge function"
+ default 0x0
+
+config EARLY_PCI_MMIO_BASE
+ hex "MMIO window base"
+ default 0x0
+
+config EARLY_PCI_BRIDGE_SECONDARY
+ hex "Early PCI bridge secondary bus"
+ default 0x0
+
+endif # EARLY_PCI_BRIDGE
diff --git a/src/drivers/pci/pci_early.c b/src/drivers/pci/pci_early.c
new file mode 100644
index 0000000..6e1a6f7
--- /dev/null
+++ b/src/drivers/pci/pci_early.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+
+{
+ /* No PCI-to-PCI bridges are enabled yet, so the one we try to
+ * configure must have its primary on bus 0.
+ */
+ pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE,
+ CONFIG_EARLY_PCI_BRIDGE_FUNCTION);
+
+ u8 bus = CONFIG_EARLY_PCI_BRIDGE_SECONDARY;
+
+ pci_bridge_reset_secondary(p2p_bridge);
+ pci_bridge_set_secondary(p2p_bridge, bus);
+
+ u3 timeout = 20000; // Timeout in 10s of microseconds.
+ u32 id = 0;
+ for (;;) {
+ id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+ if (!timeout-- || (id != 0 && id != 0xffffffff))
+ break;
+ udelay(10);
+ }
+
+ ret = probe(bus, dev, mmio_base, io_base);
+
+ /* Enable both MMIO and IO window with static allocation
+ * if we found any suitable device behind bridge.
+ */
+ pci_bridge_enable_mmio(p2p_bridge, base, limit);
+
+ /* Resource allocator will reconfigure bridges and secondary bus
+ * number may change. Early device must not use config transactions
+ * from here on.
+ */
+ pci_bridge_set_secondary(p2p_bridge, 0);
+}
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 29d988f..881c2ac 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -98,6 +98,12 @@ static inline const struct pci_operations *ops_pci(device_t dev)
return pops;
}
+#else
+
+void pci_bridge_reset_secondary(device_t p2p_bridge);
+void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base);
+void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary);
+
#endif /* ! __SIMPLE_DEVICE__ */
unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last);
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 9cfa5d5..69c1fc9 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -41,6 +41,26 @@ config EHCI_BAR
hex
default 0xfef00000
+if EARLY_PCI_BRIDGE
+
+config EARLY_PCI_BRIDGE_DEVICE
+ hex
+ default 0x1c
+
+config EARLY_PCI_BRIDGE_FUNCTION
+ hex
+ default 0x2
+
+config EARLY_PCI_MMIO_BASE
+ hex
+ default 0xe0400000
+
+config EARLY_PCI_BRIDGE_SECONDARY
+ hex
+ default 0x3
+
+endif
+
config DRAM_RESET_GATE_GPIO
int
default 60
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5236
-gerrit
commit 5f429ab8e0a8ca6f2e1cfb58a3cf85cc4337e4a6
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Jan 30 15:45:16 2014 +0200
uart8250: Move under drivers/uart
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/arch/x86/lib/romcc_console.c | 2 +-
src/cpu/allwinner/a10/uart.c | 2 +-
src/drivers/uart/Makefile.inc | 12 ++++
src/drivers/uart/uart8250io.c | 127 +++++++++++++++++++++++++++++++++++++
src/drivers/uart/uart8250mem.c | 134 +++++++++++++++++++++++++++++++++++++++
src/drivers/uart/uart8250reg.h | 108 +++++++++++++++++++++++++++++++
src/include/uart8250.h | 108 -------------------------------
src/lib/Makefile.inc | 6 --
src/lib/uart8250.c | 127 -------------------------------------
src/lib/uart8250mem.c | 134 ---------------------------------------
10 files changed, 383 insertions(+), 377 deletions(-)
diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index 1ed498a..66c81db 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -32,7 +32,7 @@
#if CONFIG_CONSOLE_SERIAL8250
#include "drivers/uart/util.c"
-#include "lib/uart8250.c"
+#include "drivers/uart/uart8250io.c"
#endif
#if CONFIG_CONSOLE_NE2K
#include "drivers/net/ne2k.c"
diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c
index 97ac302..7dad1ca 100644
--- a/src/cpu/allwinner/a10/uart.c
+++ b/src/cpu/allwinner/a10/uart.c
@@ -7,7 +7,7 @@
#include "uart.h"
#include <arch/io.h>
-#include <uart8250.h>
+#include <drivers/uart/uart8250reg.h>
/**
* \brief Configure line control settings for UART
diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc
index 52a7024..3a9ca3d 100644
--- a/src/drivers/uart/Makefile.inc
+++ b/src/drivers/uart/Makefile.inc
@@ -5,6 +5,18 @@ bootblock-y += util.c
smm-y += util.c
endif
+ifeq ($(CONFIG_CONSOLE_SERIAL8250),y)
+romstage-y += uart8250io.c
+ramstage-y += uart8250io.c
+smm-y += uart8250io.c
+endif
+
+ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
+romstage-y += uart8250mem.c
+ramstage-y += uart8250mem.c
+smm-y += uart8250mem.c
+endif
+
ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
ifeq ($(CONFIG_DRIVERS_UART_PL011),y)
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
new file mode 100644
index 0000000..6c08ce2
--- /dev/null
+++ b/src/drivers/uart/uart8250io.c
@@ -0,0 +1,127 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/uart.h>
+#include <trace.h>
+#include "uart8250reg.h"
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* No reports of super-IOs that would use different clock for
+ * baudrate reference. */
+#define BAUDRATE_REFCLK 115200
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ *
+ * Estimated that inb() from UART takes 1 microsecond.
+ */
+#define SINGLE_CHAR_TIMEOUT (50 * 1000)
+#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+
+static int uart8250_can_tx_byte(unsigned base_port)
+{
+ return inb(base_port + UART_LSR) & UART_LSR_THRE;
+}
+
+static void uart8250_tx_byte(unsigned base_port, unsigned char data)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_can_tx_byte(base_port));
+ outb(data, base_port + UART_TBR);
+}
+
+static void uart8250_tx_flush(unsigned base_port)
+{
+ unsigned long int i = FIFO_TIMEOUT;
+ while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
+}
+
+static int uart8250_can_rx_byte(unsigned base_port)
+{
+ return inb(base_port + UART_LSR) & UART_LSR_DR;
+}
+
+static unsigned char uart8250_rx_byte(unsigned base_port)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while (i-- && !uart8250_can_rx_byte(base_port));
+
+ if (i)
+ return inb(base_port + UART_RBR);
+ else
+ return 0x0;
+}
+
+static void uart8250_init(unsigned base_port, unsigned divisor)
+{
+ DISABLE_TRACE;
+ /* Disable interrupts */
+ outb(0x0, base_port + UART_IER);
+ /* Enable FIFOs */
+ outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
+
+ /* assert DTR and RTS so the other end is happy */
+ outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
+
+ /* DLAB on */
+ outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
+
+ /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
+ outb(divisor & 0xFF, base_port + UART_DLL);
+ outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
+
+ /* Set to 3 for 8N1 */
+ outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+ ENABLE_TRACE;
+}
+
+/* FIXME: Needs uart index from Kconfig.
+ * Already use array as a work-around for ROMCC.
+ */
+static const unsigned bases[1] = { CONFIG_TTYS0_BASE };
+
+void uart_init(void)
+{
+ unsigned int div = uart_baudrate_divisor(BAUDRATE_REFCLK);
+ uart8250_init(bases[0], div);
+}
+
+void uart_tx_byte(unsigned char data)
+{
+ uart8250_tx_byte(bases[0], data);
+}
+
+unsigned char uart_rx_byte(void)
+{
+ return uart8250_rx_byte(bases[0]);
+}
+
+int uart_can_rx_byte(void)
+{
+ return uart8250_can_rx_byte(bases[0]);
+}
+
+void uart_tx_flush(void)
+{
+ uart8250_tx_flush(bases[0]);
+}
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
new file mode 100644
index 0000000..dded007
--- /dev/null
+++ b/src/drivers/uart/uart8250mem.c
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2006-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/uart.h>
+#include <device/device.h>
+#include <delay.h>
+#include "uart8250reg.h"
+
+/* Should support 8250, 16450, 16550, 16550A type UARTs */
+
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ */
+#define SINGLE_CHAR_TIMEOUT (50 * 1000)
+#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+
+static int uart8250_mem_can_tx_byte(unsigned base_port)
+{
+ return read8(base_port + UART_LSR) & UART_LSR_THRE;
+}
+
+static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while(i-- && !uart8250_mem_can_tx_byte(base_port))
+ udelay(1);
+ write8(base_port + UART_TBR, data);
+}
+
+static void uart8250_mem_tx_flush(unsigned base_port)
+{
+ unsigned long int i = FIFO_TIMEOUT;
+ while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
+ udelay(1);
+}
+
+static int uart8250_mem_can_rx_byte(unsigned base_port)
+{
+ return read8(base_port + UART_LSR) & UART_LSR_DR;
+}
+
+static unsigned char uart8250_mem_rx_byte(unsigned base_port)
+{
+ unsigned long int i = SINGLE_CHAR_TIMEOUT;
+ while(i-- && !uart8250_mem_can_rx_byte(base_port))
+ udelay(1);
+ if (i)
+ return read8(base_port + UART_RBR);
+ else
+ return 0x0;
+}
+
+static void uart8250_mem_init(unsigned base_port, unsigned divisor)
+{
+ /* Disable interrupts */
+ write8(base_port + UART_IER, 0x0);
+ /* Enable FIFOs */
+ write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
+
+ /* Assert DTR and RTS so the other end is happy */
+ write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
+
+ /* DLAB on */
+ write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
+
+ /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
+ write8(base_port + UART_DLL, divisor & 0xFF);
+ write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
+
+ /* Set to 3 for 8N1 */
+ write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
+}
+
+void uart_init(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+
+ unsigned int refclk = uart_platform_refclk();
+ unsigned int div = uart_baudrate_divisor(refclk);
+ uart8250_mem_init(base, div);
+}
+
+void uart_tx_byte(unsigned char data)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+ uart8250_mem_tx_byte(base, data);
+}
+
+unsigned char uart_rx_byte(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return 0xff;
+ return uart8250_mem_rx_byte(base);
+}
+
+int uart_can_rx_byte(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return 0;
+ return uart8250_mem_can_rx_byte(base);
+}
+
+void uart_tx_flush(void)
+{
+ u32 base = uart_platform_base(0);
+ if (!base)
+ return;
+ uart8250_mem_tx_flush(base);
+}
diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h
new file mode 100644
index 0000000..cdfbb1b
--- /dev/null
+++ b/src/drivers/uart/uart8250reg.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef UART8250REG_H
+#define UART8250REG_H
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
+#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
+#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
+#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
+
+#define UART_IIR 0x02
+#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
+#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
+
+#define UART_IIR_MSI 0x00 /* Modem status interrupt */
+#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
+#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
+#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
+
+#define UART_FCR 0x02
+#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
+#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
+
+#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
+#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
+
+#define UART_LCR 0x03
+#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
+#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
+#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
+#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
+#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
+#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
+#define UART_LCR_PEN 0x08 /* Parity enable */
+#define UART_LCR_EPS 0x10 /* Even Parity Select */
+#define UART_LCR_STKP 0x20 /* Stick Parity */
+#define UART_LCR_SBRK 0x40 /* Set Break */
+#define UART_LCR_BKSE 0x80 /* Bank select enable */
+#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
+
+#define UART_MCR 0x04
+#define UART_MCR_DTR 0x01 /* DTR */
+#define UART_MCR_RTS 0x02 /* RTS */
+#define UART_MCR_OUT1 0x04 /* Out 1 */
+#define UART_MCR_OUT2 0x08 /* Out 2 */
+#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+
+#define UART_MCR_DMA_EN 0x04
+#define UART_MCR_TX_DFR 0x08
+
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_LSR_DR 0x01 /* Data ready */
+#define UART_LSR_OE 0x02 /* Overrun */
+#define UART_LSR_PE 0x04 /* Parity error */
+#define UART_LSR_FE 0x08 /* Framing error */
+#define UART_LSR_BI 0x10 /* Break */
+#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
+#define UART_LSR_TEMT 0x40 /* Xmitter empty */
+#define UART_LSR_ERR 0x80 /* Error */
+
+#define UART_MSR 0x06
+#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
+#define UART_MSR_RI 0x40 /* Ring Indicator */
+#define UART_MSR_DSR 0x20 /* Data Set Ready */
+#define UART_MSR_CTS 0x10 /* Clear to Send */
+#define UART_MSR_DDCD 0x08 /* Delta DCD */
+#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
+#define UART_MSR_DDSR 0x02 /* Delta DSR */
+#define UART_MSR_DCTS 0x01 /* Delta CTS */
+
+#define UART_SCR 0x07
+#define UART_SPR 0x07
+
+#endif /* UART8250REG_H */
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
deleted file mode 100644
index c63153c..0000000
--- a/src/include/uart8250.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Eric Biederman
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef UART8250_H
-#define UART8250_H
-
-/* Data */
-#define UART_RBR 0x00
-#define UART_TBR 0x00
-
-/* Control */
-#define UART_IER 0x01
-#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-#define UART_IIR 0x02
-#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
-
-#define UART_IIR_MSI 0x00 /* Modem status interrupt */
-#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-#define UART_FCR 0x02
-#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
-#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
-#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
-#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
-#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
-
-#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
-#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
-
-#define UART_LCR 0x03
-#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
-#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
-#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
-#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
-#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
-#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define UART_LCR_PEN 0x08 /* Parity enable */
-#define UART_LCR_EPS 0x10 /* Even Parity Select */
-#define UART_LCR_STKP 0x20 /* Stick Parity */
-#define UART_LCR_SBRK 0x40 /* Set Break */
-#define UART_LCR_BKSE 0x80 /* Bank select enable */
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-
-#define UART_MCR 0x04
-#define UART_MCR_DTR 0x01 /* DTR */
-#define UART_MCR_RTS 0x02 /* RTS */
-#define UART_MCR_OUT1 0x04 /* Out 1 */
-#define UART_MCR_OUT2 0x08 /* Out 2 */
-#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
-
-#define UART_MCR_DMA_EN 0x04
-#define UART_MCR_TX_DFR 0x08
-
-#define UART_DLL 0x00
-#define UART_DLM 0x01
-
-/* Status */
-#define UART_LSR 0x05
-#define UART_LSR_DR 0x01 /* Data ready */
-#define UART_LSR_OE 0x02 /* Overrun */
-#define UART_LSR_PE 0x04 /* Parity error */
-#define UART_LSR_FE 0x08 /* Framing error */
-#define UART_LSR_BI 0x10 /* Break */
-#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
-#define UART_LSR_TEMT 0x40 /* Xmitter empty */
-#define UART_LSR_ERR 0x80 /* Error */
-
-#define UART_MSR 0x06
-#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
-#define UART_MSR_RI 0x40 /* Ring Indicator */
-#define UART_MSR_DSR 0x20 /* Data Set Ready */
-#define UART_MSR_CTS 0x10 /* Clear to Send */
-#define UART_MSR_DDCD 0x08 /* Delta DCD */
-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
-#define UART_MSR_DDSR 0x02 /* Delta DSR */
-#define UART_MSR_DCTS 0x01 /* Delta CTS */
-
-#define UART_SCR 0x07
-#define UART_SPR 0x07
-
-#endif /* UART8250_H */
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 5c37329..6641318 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -46,8 +46,6 @@ romstage-y += cbfs.c
romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c
#romstage-y += lzmadecode.c
romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c
-romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
-romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ifeq ($(CONFIG_EARLY_CBMEM_INIT),y)
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
@@ -87,8 +85,6 @@ ramstage-y += stack.c
ramstage-$(CONFIG_ARCH_X86) += gcc.c
ramstage-y += clog2.c
romstage-y += clog2.c
-ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
-ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
@@ -125,8 +121,6 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y)
smm-y += memmove.c
endif
smm-y += cbfs.c memcmp.c
-smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
-smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
smm-y += gcc.c
$(obj)/lib/version.ramstage.o : $(obj)/build.h
diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
deleted file mode 100644
index d5e845c..0000000
--- a/src/lib/uart8250.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Eric Biederman
- * Copyright (C) 2006-2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/uart.h>
-#include <uart8250.h>
-#include <trace.h>
-
-/* Should support 8250, 16450, 16550, 16550A type UARTs */
-
-/* No reports of super-IOs that would use different clock for
- * baudrate reference. */
-#define BAUDRATE_REFCLK 115200
-
-/* Expected character delay at 1200bps is 9ms for a working UART
- * and no flow-control. Assume UART as stuck if shift register
- * or FIFO takes more than 50ms per character to appear empty.
- *
- * Estimated that inb() from UART takes 1 microsecond.
- */
-#define SINGLE_CHAR_TIMEOUT (50 * 1000)
-#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
-
-static int uart8250_can_tx_byte(unsigned base_port)
-{
- return inb(base_port + UART_LSR) & UART_LSR_THRE;
-}
-
-static void uart8250_tx_byte(unsigned base_port, unsigned char data)
-{
- unsigned long int i = SINGLE_CHAR_TIMEOUT;
- while (i-- && !uart8250_can_tx_byte(base_port));
- outb(data, base_port + UART_TBR);
-}
-
-static void uart8250_tx_flush(unsigned base_port)
-{
- unsigned long int i = FIFO_TIMEOUT;
- while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
-}
-
-static int uart8250_can_rx_byte(unsigned base_port)
-{
- return inb(base_port + UART_LSR) & UART_LSR_DR;
-}
-
-static unsigned char uart8250_rx_byte(unsigned base_port)
-{
- unsigned long int i = SINGLE_CHAR_TIMEOUT;
- while (i-- && !uart8250_can_rx_byte(base_port));
-
- if (i)
- return inb(base_port + UART_RBR);
- else
- return 0x0;
-}
-
-static void uart8250_init(unsigned base_port, unsigned divisor)
-{
- DISABLE_TRACE;
- /* Disable interrupts */
- outb(0x0, base_port + UART_IER);
- /* Enable FIFOs */
- outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
-
- /* assert DTR and RTS so the other end is happy */
- outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
-
- /* DLAB on */
- outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
-
- /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
- outb(divisor & 0xFF, base_port + UART_DLL);
- outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
-
- /* Set to 3 for 8N1 */
- outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
- ENABLE_TRACE;
-}
-
-/* FIXME: Needs uart index from Kconfig.
- * Already use array as a work-around for ROMCC.
- */
-static const unsigned bases[1] = { CONFIG_TTYS0_BASE };
-
-void uart_init(void)
-{
- unsigned int div = uart_baudrate_divisor(BAUDRATE_REFCLK);
- uart8250_init(bases[0], div);
-}
-
-void uart_tx_byte(unsigned char data)
-{
- uart8250_tx_byte(bases[0], data);
-}
-
-unsigned char uart_rx_byte(void)
-{
- return uart8250_rx_byte(bases[0]);
-}
-
-int uart_can_rx_byte(void)
-{
- return uart8250_can_rx_byte(bases[0]);
-}
-
-void uart_tx_flush(void)
-{
- uart8250_tx_flush(bases[0]);
-}
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
deleted file mode 100644
index fb471fb..0000000
--- a/src/lib/uart8250mem.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Eric Biederman
- * Copyright (C) 2006-2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <console/uart.h>
-#include <uart8250.h>
-#include <device/device.h>
-#include <delay.h>
-
-/* Should support 8250, 16450, 16550, 16550A type UARTs */
-
-/* Expected character delay at 1200bps is 9ms for a working UART
- * and no flow-control. Assume UART as stuck if shift register
- * or FIFO takes more than 50ms per character to appear empty.
- */
-#define SINGLE_CHAR_TIMEOUT (50 * 1000)
-#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
-
-static int uart8250_mem_can_tx_byte(unsigned base_port)
-{
- return read8(base_port + UART_LSR) & UART_LSR_THRE;
-}
-
-static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
-{
- unsigned long int i = SINGLE_CHAR_TIMEOUT;
- while(i-- && !uart8250_mem_can_tx_byte(base_port))
- udelay(1);
- write8(base_port + UART_TBR, data);
-}
-
-static void uart8250_mem_tx_flush(unsigned base_port)
-{
- unsigned long int i = FIFO_TIMEOUT;
- while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
- udelay(1);
-}
-
-static int uart8250_mem_can_rx_byte(unsigned base_port)
-{
- return read8(base_port + UART_LSR) & UART_LSR_DR;
-}
-
-static unsigned char uart8250_mem_rx_byte(unsigned base_port)
-{
- unsigned long int i = SINGLE_CHAR_TIMEOUT;
- while(i-- && !uart8250_mem_can_rx_byte(base_port))
- udelay(1);
- if (i)
- return read8(base_port + UART_RBR);
- else
- return 0x0;
-}
-
-static void uart8250_mem_init(unsigned base_port, unsigned divisor)
-{
- /* Disable interrupts */
- write8(base_port + UART_IER, 0x0);
- /* Enable FIFOs */
- write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
-
- /* Assert DTR and RTS so the other end is happy */
- write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
-
- /* DLAB on */
- write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
-
- /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
- write8(base_port + UART_DLL, divisor & 0xFF);
- write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
-
- /* Set to 3 for 8N1 */
- write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
-}
-
-void uart_init(void)
-{
- u32 base = uart_platform_base(0);
- if (!base)
- return;
-
- unsigned int refclk = uart_platform_refclk();
- unsigned int div = uart_baudrate_divisor(refclk);
- uart8250_mem_init(base, div);
-}
-
-void uart_tx_byte(unsigned char data)
-{
- u32 base = uart_platform_base(0);
- if (!base)
- return;
- uart8250_mem_tx_byte(base, data);
-}
-
-unsigned char uart_rx_byte(void)
-{
- u32 base = uart_platform_base(0);
- if (!base)
- return 0xff;
- return uart8250_mem_rx_byte(base);
-}
-
-int uart_can_rx_byte(void)
-{
- u32 base = uart_platform_base(0);
- if (!base)
- return 0;
- return uart8250_mem_can_rx_byte(base);
-}
-
-void uart_tx_flush(void)
-{
- u32 base = uart_platform_base(0);
- if (!base)
- return;
- uart8250_mem_tx_flush(base);
-}