coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 5bba95e CAR_GLOBAL: enforce compiler to check if _start != _end
by Edward O'Callaghan 19 Feb '14

19 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4719 -gerrit commit 5bba95edd42f289c5275b208ea97d21e990c4b0c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Feb 20 05:10:09 2014 +1100 CAR_GLOBAL: enforce compiler to check if _start != _end There are some fun rules C compilers can use to optimize their code. One of them is the assumption that two symbols point to two different addresses. In this case this wasn't true, resulting in unintended code execution (and later, a crash) with a clang build. [NOTFORMERGE]-yet: Test me! Change-Id: I1496b22e1d1869ed0610e321b6ec6a83252e9d8b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/init/romstage.ld | 2 +- src/cpu/x86/car.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index f44185f..6ab2247 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -37,7 +37,7 @@ SECTIONS . = ALIGN(16); _car_migrate_start = .; *(.car.migrate); - _car_migrate_end = .; + LONG(0); . = ALIGN(16); _erom = .; } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 481153d..a7e3842 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -26,7 +26,6 @@ typedef void (* const car_migration_func_t)(void); extern car_migration_func_t _car_migrate_start; -extern car_migration_func_t _car_migrate_end; extern char _car_data_start[]; extern char _car_data_end[]; @@ -98,7 +97,7 @@ void car_migrate_variables(void) /* Call all the migration functions. */ migrate_func = &_car_migrate_start; - while (migrate_func != &_car_migrate_end) { + while (*migrate_func != NULL) { (*migrate_func)(); migrate_func++; }

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Patch set updated for coreboot: fdac806 CAR_GLOBAL: enforce compiler to check if _start != _end
by Edward O'Callaghan 19 Feb '14

19 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4719 -gerrit commit fdac806240c2aa5da7820147bc3928920ff32e07 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Feb 20 01:51:43 2014 +1100 CAR_GLOBAL: enforce compiler to check if _start != _end There are some fun rules C compilers can use to optimize their code. One of them is the assumption that two symbols point to two different addresses. In this case this wasn't true, resulting in unintended code execution (and later, a crash) with a clang build. Change-Id: I1496b22e1d1869ed0610e321b6ec6a83252e9d8b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/init/romstage.ld | 1 + src/cpu/x86/car.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index f44185f..5458cfc 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -37,6 +37,7 @@ SECTIONS . = ALIGN(16); _car_migrate_start = .; *(.car.migrate); + LONG(0); _car_migrate_end = .; . = ALIGN(16); _erom = .; diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 481153d..8f6a855 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -98,7 +98,7 @@ void car_migrate_variables(void) /* Call all the migration functions. */ migrate_func = &_car_migrate_start; - while (migrate_func != &_car_migrate_end) { + while (*migrate_func != NULL) { (*migrate_func)(); migrate_func++; }

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Patch set updated for coreboot: adde7a1 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams.
by Edward O'Callaghan 19 Feb '14

19 Feb '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5198 -gerrit commit adde7a178f3cfe1f25a70cecd63a39dc161d9315 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Feb 12 21:53:44 2014 +1100 libpayload/endian.h: Provide alignment-agnostic enc/dec bytestreams. Alignment-agnostic encode/decode bytestream to/from little/big endian. The le16enc(), le16dec(), le32enc(), le32dec() functions encode and decode integers to/from byte strings on any alignment in big/little endian format. See BYTEORDER(9). Change-Id: I73a174b9c02c467bc60590c5cd894dac58b8683a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/libpayload/include/endian.h | 74 +++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index cb50443..c7ef32d 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -69,7 +69,7 @@ static inline uint64_t swap_bytes64(uint64_t in) #error Cant tell if the CPU is little or big endian. -#endif +#endif /* CONFIG_*_ENDIAN */ #define be16toh(in) htobe16(in) #define be32toh(in) htobe32(in) @@ -87,6 +87,76 @@ static inline uint64_t swap_bytes64(uint64_t in) #define ntohl(in) be32toh(in) #define ntohll(in) be64toh(in) +/* + * Alignment-agnostic encode/decode bytestream to/from little/big endian. + */ + +static inline uint16_t be16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[0] << 8) | p[1]); +} + +static inline uint32_t be32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]); +} + +static inline uint16_t le16dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[1] << 8) | p[0]); +} + +static inline uint32_t le32dec(const void *pp) +{ + uint8_t const *p = (uint8_t const *)pp; + + return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); +} + +static inline void bebitenc(void *pp, uint32_t u, uint8_t b) +{ + uint8_t *p = (uint8_t *)pp; + int i; + + for(i=(b-1); i >= 0; i++) + p[i] = (u >> i*8) & 0xFF; +} + +static inline void be16enc(void *pp, uint16_t u) +{ + bebitenc(pp, u, 2); +} + +static inline void be32enc(void *pp, uint32_t u) +{ + bebitenc(pp, u, 4); +} + +static inline void lebitenc(void *pp, uint32_t u, uint8_t b) +{ + uint8_t *p = (uint8_t *)pp; + int i; + + for(i=0; i < b; i++) + p[i] = (u >> i*8) & 0xFF; +} + +static inline void le16enc(void *pp, uint16_t u) +{ + lebitenc(pp, u, 2); +} + +static inline void le32enc(void *pp, uint32_t u) +{ + lebitenc(pp, u, 4); +} + /* Deprecated names (not in glibc / BSD) */ #define htobew(in) htobe16(in) #define htobel(in) htobe32(in) @@ -101,4 +171,4 @@ static inline uint64_t swap_bytes64(uint64_t in) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) -#endif +#endif /* _ENDIAN_H_ */

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Patch merged into coreboot/master: 01fddb1 lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS
by gerrit＠coreboot.org 18 Feb '14

18 Feb '14

the following patch was just integrated into master: commit 01fddb11d492d00dfc8b1f42e6969838ad6db04d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Feb 10 11:34:27 2014 -0800 lynxpoint: Finalize chipset before playload if not CONFIG_CHROMEOS The Chrome OS environment sends an SMI to finalize the chipset/board at the end of the "depthcharge" payload, but there is no facility to send this command if not using the full ChromeOS firmware stack. This commit adds a callback before booting the payload that will issue this SMI which will lock down the chipset and route USB devices to the XHCI controller. Change-Id: I2db9c44d61ebf8fa28a8a2b260a63d4aa4d75842 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/5181 for details. -gerrit

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New patch to review for coreboot: 6f47f9b drivers/spi: Sort SPI flash files
by Christopher Douglass 18 Feb '14

18 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5260 -gerrit commit 6f47f9b58c54a6499d9e0b8016e70c12946b5f96 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Tue Feb 18 11:21:02 2014 -0500 drivers/spi: Sort SPI flash files Change-Id: Id7e65065556ca7225969ca0afdb21eda24aeb967 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- src/drivers/spi/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index cfb5325..33eb385 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -4,12 +4,12 @@ ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers ramstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c +ramstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c ramstage-$(CONFIG_SPI_FLASH_SST) += sst.c ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c -ramstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c ifeq ($(CONFIG_SPI_FLASH_SMM),y) @@ -20,10 +20,10 @@ smm-$(CONFIG_SPI_FLASH) += spi_flash.c smm-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c smm-$(CONFIG_SPI_FLASH_EON) += eon.c smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c +smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c smm-$(CONFIG_SPI_FLASH_SST) += sst.c smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c -smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c endif

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Patch set updated for coreboot: ea850ce drivers/spi: Add support for adesto SPI flash parts
by Christopher Douglass 18 Feb '14

18 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5225 -gerrit commit ea850ceb328af1089a94a5a5e42d252801b07cda Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:26 2014 -0500 drivers/spi: Add support for adesto SPI flash parts Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- src/drivers/spi/Kconfig | 8 ++ src/drivers/spi/Makefile.inc | 4 +- src/drivers/spi/adesto.c | 197 +++++++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 3 + src/drivers/spi/spi_flash_internal.h | 1 + 5 files changed, 212 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index a99199a..95568f0 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -94,3 +94,11 @@ config SPI_FLASH_GIGADEVICE help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice. + +config SPI_FLASH_ADESTO + bool + default y + depends on SPI_FLASH + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Adesto Technologies. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 1a34ab5..cfb5325 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -2,6 +2,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +ramstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c ramstage-$(CONFIG_SPI_FLASH_EON) += eon.c ramstage-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c ramstage-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c @@ -16,6 +17,7 @@ ifeq ($(CONFIG_SPI_FLASH_SMM),y) smm-$(CONFIG_SPI_FLASH) += spi_flash.c # drivers +smm-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c smm-$(CONFIG_SPI_FLASH_EON) += eon.c smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c @@ -24,4 +26,4 @@ smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c -endif \ No newline at end of file +endif diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c new file mode 100644 index 0000000..83be8b8 --- /dev/null +++ b/src/drivers/spi/adesto.c @@ -0,0 +1,197 @@ +/* + * adesto.c + * Driver for Adesto Technologies SPI flash + * Copyright 2014 Orion Technologies, LLC + * Author: Chris Douglass <cdouglass <at> oriontechnologies.com> + * + * based on winbond.c + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* at25dfxx-specific commands */ +#define CMD_AT25DF_WREN 0x06 /* Write Enable */ +#define CMD_AT25DF_WRDI 0x04 /* Write Disable */ +#define CMD_AT25DF_RDSR 0x05 /* Read Status Register */ +#define CMD_AT25DF_WRSR 0x01 /* Write Status Register */ +#define CMD_AT25DF_READ 0x03 /* Read Data Bytes */ +#define CMD_AT25DF_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_AT25DF_PP 0x02 /* Page Program */ +#define CMD_AT25DF_SE 0x20 /* Sector (4K) Erase */ +#define CMD_AT25DF_BE 0xd8 /* Block (64K) Erase */ +#define CMD_AT25DF_CE 0xc7 /* Chip Erase */ +#define CMD_AT25DF_DP 0xb9 /* Deep Power-down */ +#define CMD_AT25DF_RES 0xab /* Release from DP, and Read Signature */ + +struct adesto_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct adesto_spi_flash { + struct spi_flash flash; + const struct adesto_spi_flash_params *params; +}; + +static inline struct adesto_spi_flash * +to_adesto_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct adesto_spi_flash, flash); +} + +static const struct adesto_spi_flash_params adesto_spi_flash_table[] = { + { + .id = 0x4501, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "AT25DF081", + }, + { + .id = 0x4701, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "AT25DF321", + }, + { + .id = 0x4800, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "AT25DF641", + }, +}; + +static int adesto_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct adesto_spi_flash *stm = to_adesto_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_AT25DF_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = spi_flash_cmd(flash->spi, CMD_AT25DF_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: adesto Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "SF: adesto: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int adesto_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_AT25DF_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode) +{ + const struct adesto_spi_flash_params *params; + unsigned page_size; + struct adesto_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(adesto_spi_flash_table); i++) { + params = &adesto_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(adesto_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported adesto ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct adesto_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = adesto_write; + stm->flash.erase = adesto_erase; +#if CONFIG_SPI_FLASH_NO_FAST_READ + stm->flash.read = spi_flash_cmd_read_slow; +#else + stm->flash.read = spi_flash_cmd_read_fast; +#endif + stm->flash.sector_size = (1 << stm->params->l2_page_size) * + stm->params->pages_per_sector; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &stm->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index ada4f3a..7a4904f 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -243,6 +243,9 @@ static struct { #if CONFIG_SPI_FLASH_STMICRO { 0, 0xff, spi_flash_probe_stmicro, }, #endif +#if CONFIG_SPI_FLASH_ADESTO + { 0, 0x1f, spi_flash_probe_adesto, }, +#endif }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..fe4a51f 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -80,4 +80,5 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);

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Patch set updated for coreboot: 93f0743 intel/sandybridge: add PCI IDs for 6-Series PCH
by Christopher Douglass 18 Feb '14

18 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5226 -gerrit commit 93f0743228e30d22cd3332d7850cc1b558bbce37 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:52 2014 -0500 intel/sandybridge: add PCI IDs for 6-Series PCH The PCI ids are taken from: Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update – NDA October 2013 CDI / IBP#: 440377 Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- .../intel/sandybridge/report_platform.c | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index cc74841..8230729 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -59,11 +59,36 @@ static void report_cpu_info(void) mode[aes], mode[txt], mode[vt]); } -/* The PCI id name match comes from Intel document 472178 */ static struct { u16 dev_id; const char *dev_name; } pch_table [] = { + /* 6-series PCI ids from + * Intel® 6 Series Chipset and + * Intel® C200 Series Chipset + * Specification Update – NDA + * October 2013 + * CDI / IBP#: 440377 + */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ {0x1E41, "Desktop Sample"}, {0x1E42, "Mobile Sample"}, {0x1E43, "SFF Sample"},

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Patch set updated for coreboot: d79b8c9 intel/sandybridge: add PCI IDs for 6-Series PCH
by Christopher Douglass 18 Feb '14

18 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5226 -gerrit commit d79b8c9277f6777eba20fac95481a3a1ac96e294 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:52 2014 -0500 intel/sandybridge: add PCI IDs for 6-Series PCH The PCI ids are taken from: Intel® 6 Series Chipset and Intel® C200 Series Chipset Specification Update – NDA October 2013 CDI / IBP#: 440377 Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- .../intel/sandybridge/report_platform.c | 27 +++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index cc74841..8230729 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -59,11 +59,36 @@ static void report_cpu_info(void) mode[aes], mode[txt], mode[vt]); } -/* The PCI id name match comes from Intel document 472178 */ static struct { u16 dev_id; const char *dev_name; } pch_table [] = { + /* 6-series PCI ids from + * Intel® 6 Series Chipset and + * Intel® C200 Series Chipset + * Specification Update – NDA + * October 2013 + * CDI / IBP#: 440377 + */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ {0x1E41, "Desktop Sample"}, {0x1E42, "Mobile Sample"}, {0x1E43, "SFF Sample"},

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Patch set updated for coreboot: f5a50a3 drivers/spi: Add support for adesto SPI flash parts
by Christopher Douglass 18 Feb '14

18 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5225 -gerrit commit f5a50a3d7ead21e69ce35459e855a8486fa36f11 Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:26 2014 -0500 drivers/spi: Add support for adesto SPI flash parts Adds support for the following Adesto Technologies SPI Flash parts. AT25DF081 AT25DF321 AT25DF641 It has been tested on an Orion VPX7654 board populated with an AT25DF321A part. The "08" and "64" densities have not been tested. These parts are the successors of the Atmel AT26DF line that was spun out or purchased by Adesto. In this patch, adesto.c is identical to winbond.c with part entries for the Adesto parts. The datasheet for the AT25DF parts includes a "100MHz" programming command in addition to the "85MHz" command that is currently used but this patch does not add support for that enhanced programming mode. Change-Id: If82d075fd9000030480c412c645dcae2c8bb7439 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- src/drivers/spi/Kconfig | 8 ++ src/drivers/spi/Makefile.inc | 2 + src/drivers/spi/adesto.c | 197 +++++++++++++++++++++++++++++++++++ src/drivers/spi/spi_flash.c | 3 + src/drivers/spi/spi_flash_internal.h | 1 + 5 files changed, 211 insertions(+) diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index a99199a..95568f0 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -94,3 +94,11 @@ config SPI_FLASH_GIGADEVICE help Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice. + +config SPI_FLASH_ADESTO + bool + default y + depends on SPI_FLASH + help + Select this option if your chipset driver needs to store certain + data in the SPI flash and your SPI flash is made by Adesto Technologies. diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 1a34ab5..65eb0b3 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -9,6 +9,7 @@ ramstage-$(CONFIG_SPI_FLASH_SST) += sst.c ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c ramstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c +ramstage-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c ifeq ($(CONFIG_SPI_FLASH_SMM),y) @@ -22,6 +23,7 @@ smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c smm-$(CONFIG_SPI_FLASH_SST) += sst.c smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c +smm-$(CONFIG_SPI_FLASH_ADESTO) += adesto.c smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c endif \ No newline at end of file diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c new file mode 100644 index 0000000..83be8b8 --- /dev/null +++ b/src/drivers/spi/adesto.c @@ -0,0 +1,197 @@ +/* + * adesto.c + * Driver for Adesto Technologies SPI flash + * Copyright 2014 Orion Technologies, LLC + * Author: Chris Douglass <cdouglass <at> oriontechnologies.com> + * + * based on winbond.c + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * Licensed under the GPL-2 or later. + */ + +#include <stdlib.h> +#include <spi_flash.h> +#include "spi_flash_internal.h" + +/* at25dfxx-specific commands */ +#define CMD_AT25DF_WREN 0x06 /* Write Enable */ +#define CMD_AT25DF_WRDI 0x04 /* Write Disable */ +#define CMD_AT25DF_RDSR 0x05 /* Read Status Register */ +#define CMD_AT25DF_WRSR 0x01 /* Write Status Register */ +#define CMD_AT25DF_READ 0x03 /* Read Data Bytes */ +#define CMD_AT25DF_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_AT25DF_PP 0x02 /* Page Program */ +#define CMD_AT25DF_SE 0x20 /* Sector (4K) Erase */ +#define CMD_AT25DF_BE 0xd8 /* Block (64K) Erase */ +#define CMD_AT25DF_CE 0xc7 /* Chip Erase */ +#define CMD_AT25DF_DP 0xb9 /* Deep Power-down */ +#define CMD_AT25DF_RES 0xab /* Release from DP, and Read Signature */ + +struct adesto_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint16_t nr_blocks; + const char *name; +}; + +/* spi_flash needs to be first so upper layers can free() it */ +struct adesto_spi_flash { + struct spi_flash flash; + const struct adesto_spi_flash_params *params; +}; + +static inline struct adesto_spi_flash * +to_adesto_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct adesto_spi_flash, flash); +} + +static const struct adesto_spi_flash_params adesto_spi_flash_table[] = { + { + .id = 0x4501, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 16, + .name = "AT25DF081", + }, + { + .id = 0x4701, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "AT25DF321", + }, + { + .id = 0x4800, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "AT25DF641", + }, +}; + +static int adesto_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct adesto_spi_flash *stm = to_adesto_spi_flash(flash); + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + byte_addr = offset % page_size; + + flash->spi->rw = SPI_WRITE_FLAG; + ret = spi_claim_bus(flash->spi); + if (ret) { + printk(BIOS_WARNING, "SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_AT25DF_PP; + cmd[1] = (offset >> 16) & 0xff; + cmd[2] = (offset >> 8) & 0xff; + cmd[3] = offset & 0xff; +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" + " chunk_len = %zu\n", buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); +#endif + + ret = spi_flash_cmd(flash->spi, CMD_AT25DF_WREN, NULL, 0); + if (ret < 0) { + printk(BIOS_WARNING, "SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + printk(BIOS_WARNING, "SF: adesto Page Program failed\n"); + goto out; + } + + ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret) + goto out; + + offset += chunk_len; + byte_addr = 0; + } + +#if CONFIG_DEBUG_SPI_FLASH + printk(BIOS_SPEW, "SF: adesto: Successfully programmed %zu bytes @" + " 0x%lx\n", len, (unsigned long)(offset - len)); +#endif + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +static int adesto_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + return spi_flash_cmd_erase(flash, CMD_AT25DF_SE, offset, len); +} + +struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode) +{ + const struct adesto_spi_flash_params *params; + unsigned page_size; + struct adesto_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(adesto_spi_flash_table); i++) { + params = &adesto_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(adesto_spi_flash_table)) { + printk(BIOS_WARNING, "SF: Unsupported adesto ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct adesto_spi_flash)); + if (!stm) { + printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = adesto_write; + stm->flash.erase = adesto_erase; +#if CONFIG_SPI_FLASH_NO_FAST_READ + stm->flash.read = spi_flash_cmd_read_slow; +#else + stm->flash.read = spi_flash_cmd_read_fast; +#endif + stm->flash.sector_size = (1 << stm->params->l2_page_size) * + stm->params->pages_per_sector; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + return &stm->flash; +} diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index ada4f3a..7a4904f 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -243,6 +243,9 @@ static struct { #if CONFIG_SPI_FLASH_STMICRO { 0, 0xff, spi_flash_probe_stmicro, }, #endif +#if CONFIG_SPI_FLASH_ADESTO + { 0, 0x1f, spi_flash_probe_adesto, }, +#endif }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 37ffee6..fe4a51f 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -80,4 +80,5 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_adesto(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);

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Patch set updated for coreboot: 61817ed add PCI IDs for Intel 6-Series PCH
by Christopher Douglass 18 Feb '14

18 Feb '14

Christopher Douglass (cdouglass.orion(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5226 -gerrit commit 61817ed316fb7328cf78299fee4a08d0d427d09a Author: Chris Douglass <cdouglass.orion(a)gmail.com> Date: Fri Feb 14 13:51:52 2014 -0500 add PCI IDs for Intel 6-Series PCH The PCI ids are taken from Intel document 440377 Change-Id: Ib8418173fd36fd4109b3c4ec0d5543ca8e39ffa6 Signed-off-by: Christopher Douglass <cdouglass.orion(a)gmail.com> --- src/northbridge/intel/sandybridge/report_platform.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index cc74841..856ba99 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -59,11 +59,30 @@ static void report_cpu_info(void) mode[aes], mode[txt], mode[vt]); } -/* The PCI id name match comes from Intel document 472178 */ static struct { u16 dev_id; const char *dev_name; } pch_table [] = { + /* 6-series PCI ids from Intel document 440377 */ + {0x1C41, "SFF Sample"}, + {0x1C42, "Desktop Sample"}, + {0x1C43, "Mobile Sample"}, + {0x1C44, "Z68"}, + {0x1C46, "P67"}, + {0x1C47, "UM67"}, + {0x1C49, "HM65"}, + {0x1C4A, "H67"}, + {0x1C4B, "HM67"}, + {0x1C4C, "Q65"}, + {0x1C4D, "QS67"}, + {0x1C4E, "Q67"}, + {0x1C4F, "QM67"}, + {0x1C50, "B65"}, + {0x1C52, "C202"}, + {0x1C54, "C204"}, + {0x1C56, "C206"}, + {0x1C5C, "H61"}, + /* 7-series PCI ids from Intel document 472178 */ {0x1E41, "Desktop Sample"}, {0x1E42, "Mobile Sample"}, {0x1E43, "SFF Sample"},

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coreboot-gerrit February 2014