coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

1 participants
1135 discussions

Patch set updated for coreboot: ca79b55 SMM: Only have console with DEBUG_SMI
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5142 -gerrit commit ca79b55400c14e0c41331b7bbe9210f1c4c0963f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jan 26 11:32:51 2014 +0200 SMM: Only have console with DEBUG_SMI Existing code compiled serial communication and printk() for SMM even when DEBUG_SMI was not selected. Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Makefile.inc | 3 +-- src/cpu/x86/smm/smiutil.c | 8 ++------ src/drivers/uart/Makefile.inc | 6 +++--- src/include/console/console.h | 1 + 4 files changed, 7 insertions(+), 11 deletions(-) diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 62be1d2..54d59cd 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -5,8 +5,7 @@ ramstage-y += vsprintf.c ramstage-y += post.c ramstage-y += die.c -smm-y += printk.c -smm-y += vtxprintf.c +smm-$(CONFIG_DEBUG_SMI) += vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c romstage-$(CONFIG_EARLY_CONSOLE) += vtxprintf.c diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 43731bc..3325c32 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -19,13 +19,10 @@ * MA 02110-1301 USA */ -#include <arch/io.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/smm.h> #include <console/console.h> #include <console/uart.h> -#include <console/vtxprintf.h> +#if CONFIG_DEBUG_SMI void console_tx_flush(void) { } @@ -42,6 +39,7 @@ void console_tx_byte(unsigned char byte) uart_tx_byte(byte); #endif } +#endif void console_init(void) { @@ -53,8 +51,6 @@ void console_init(void) #if CONFIG_CONSOLE_SERIAL8250MEM uart_init(); #endif -#else - console_loglevel = 1; #endif } diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 3a9ca3d..415c5bb 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -2,19 +2,19 @@ ifeq ($(CONFIG_CONSOLE_SERIAL),y) romstage-y += util.c ramstage-y += util.c bootblock-y += util.c -smm-y += util.c +smm-$(CONFIG_DEBUG_SMI) += util.c endif ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) romstage-y += uart8250io.c ramstage-y += uart8250io.c -smm-y += uart8250io.c +smm-$(CONFIG_DEBUG_SMI) += uart8250io.c endif ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) romstage-y += uart8250mem.c ramstage-y += uart8250mem.c -smm-y += uart8250mem.c +smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) diff --git a/src/include/console/console.h b/src/include/console/console.h index dfeedda..a089729 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -72,6 +72,7 @@ void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #if defined(__BOOT_BLOCK__) && !CONFIG_BOOTBLOCK_CONSOLE || \ + defined(__SMM__) && !CONFIG_DEBUG_SMI || \ (defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__)) && !CONFIG_EARLY_CONSOLE static inline void printk(int LEVEL, const char *fmt, ...);

1 0

Patch set updated for coreboot: 74f48b7 uart8250mem: Unify calls with generic UART
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5235 -gerrit commit 74f48b797658dcefc573e88872bdad2d3ad8219d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 10:19:23 2014 +0200 uart8250mem: Unify calls with generic UART NOTE: UART base for SMM continues to be broken, as it does not use the address resource allocator has assigned. Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 11 +--- src/console/uart8250mem_console.c | 30 +++-------- src/cpu/x86/smm/smiutil.c | 10 +--- src/drivers/oxford/oxpcie/Makefile.inc | 6 ++- src/drivers/oxford/oxpcie/oxpcie.c | 4 +- src/drivers/oxford/oxpcie/oxpcie_early.c | 51 ++++++++++++++----- src/include/console/uart.h | 2 + src/include/uart8250.h | 17 ------- src/lib/uart8250mem.c | 87 ++++++++++++++++---------------- 9 files changed, 102 insertions(+), 116 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 045890d..4971ba1 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,20 +26,13 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - void console_tx_byte(unsigned char byte) { if (byte == '\n') console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_byte(byte); @@ -61,7 +54,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_flush(); diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index 3833e47..7e52aed 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -18,47 +18,31 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> -static u32 uart_bar = 0; - -void uartmem_init(void) -{ - uart_bar = uart_mem_init(); -} - -u32 uartmem_getbaseaddr(void) +static void uartmem_init(void) { - return uart_bar; + uart_init(); } static void uartmem_tx_byte(unsigned char data) { - if (!uart_bar) - return; - - uart8250_mem_tx_byte(uart_bar, data); + uart_tx_byte(data); } static void uartmem_tx_flush(void) { - uart8250_mem_tx_flush(uart_bar); + uart_tx_flush(); } static unsigned char uartmem_rx_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_rx_byte(uart_bar); + return uart_rx_byte(); } static int uartmem_tst_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_can_rx_byte(uart_bar); + return uart_can_rx_byte(); } static const struct console_driver uart8250mem_console __console = { diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 3702e5c..43731bc 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -24,13 +24,8 @@ #include <cpu/x86/smm.h> #include <console/console.h> #include <console/uart.h> -#include <uart8250.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250MEM -static u32 serial8250mem_base_address = 0; -#endif - void console_tx_flush(void) { } @@ -41,8 +36,7 @@ void console_tx_byte(unsigned char byte) console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (serial8250mem_base_address) - uart8250_mem_tx_byte(serial8250mem_base_address, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_byte(byte); @@ -57,7 +51,7 @@ void console_init(void) uart_init(); #endif #if CONFIG_CONSOLE_SERIAL8250MEM - serial8250mem_base_address = uart_mem_init(); + uart_init(); #endif #else console_loglevel = 1; diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 6cc29c4..518e4c5 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,5 +1,7 @@ -ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c +ifeq ($(CONFIG_DRIVERS_OXFORD_OXPCIE),y) ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) -romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c +ramstage-y += oxpcie_early.c oxpcie.c +romstage-y += oxpcie_early.c +endif endif diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index f719fc7..f70c9fc 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> +#include <console/uart.h> #include <arch/io.h> static void oxford_oxpcie_enable(device_t dev) @@ -48,7 +49,8 @@ static void oxford_oxpcie_set_resources(struct device *dev) #if CONFIG_CONSOLE_SERIAL8250MEM /* Re-initialize OXPCIe base address after set_resources */ - uartmem_init(); + u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); #endif } diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index c711a40..3fc19c3 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -17,14 +17,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <stdint.h> +#include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> #include <console/uart.h> -#include <uart8250.h> #include <device/pci_def.h> +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; + #define PCIE_BRIDGE \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ @@ -36,13 +42,9 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) -#if defined(__PRE_RAM__) -int oxford_oxpcie_present CAR_GLOBAL; - -void oxford_init(void) +static void oxpcie_init_bridge(void) { u16 reg16; - oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -101,7 +103,6 @@ void oxford_init(void) break; default: /* No UART here. */ - oxford_oxpcie_present = 0; return; } @@ -114,17 +115,43 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); - /* Now the UART initialization */ - u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; + car_set_var(oxpcie_present, 1); +} + +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); +} + +unsigned int uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} - unsigned int refclk = uart_platform_refclk(); - unsigned int div = uart_baudrate_divisor(refclk); - uart8250_mem_init(uart0_base, div); +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; } +uint32_t uartmem_getbaseaddr(void) +{ + return uart_platform_base(0); +} #endif unsigned int uart_platform_refclk(void) { return 4000000; } + +void oxford_init(void) +{ + oxpcie_init_bridge(); + uart_init(); +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 27be2e8..cd9deb5 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -36,8 +36,10 @@ void uart_tx_flush(void); unsigned char uart_rx_byte(void); int uart_can_rx_byte(void); +unsigned int uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); void oxford_init(void); +void oxford_remap(unsigned int new_base); #endif /* CONSOLE_UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 100a216..c63153c 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -105,21 +105,4 @@ #define UART_SCR 0x07 #define UART_SPR 0x07 -#if CONFIG_CONSOLE_SERIAL8250MEM -void uartmem_init(void); - -/* and the same for memory mapped uarts */ -unsigned char uart8250_mem_rx_byte(unsigned base_port); -int uart8250_mem_can_rx_byte(unsigned base_port); -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); -void uart8250_mem_tx_flush(unsigned base_port); -void uart8250_mem_init(unsigned base_port, unsigned divisor); -u32 uart_mem_init(void); - -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; -#endif -#endif - #endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 7b4672a..fb471fb 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -33,42 +33,32 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static inline int uart8250_mem_can_tx_byte(unsigned base_port) +static int uart8250_mem_can_tx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_THRE; } -static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_tx_byte(base_port)) udelay(1); + write8(base_port + UART_TBR, data); } -static inline void uart8250_mem_wait_until_sent(unsigned base_port) +static void uart8250_mem_tx_flush(unsigned base_port) { unsigned long int i = FIFO_TIMEOUT; while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) udelay(1); } -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_mem_wait_to_tx_byte(base_port); - write8(base_port + UART_TBR, data); -} - -void uart8250_mem_tx_flush(unsigned base_port) -{ - uart8250_mem_wait_until_sent(base_port); -} - -int uart8250_mem_can_rx_byte(unsigned base_port) +static int uart8250_mem_can_rx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_mem_rx_byte(unsigned base_port) +static unsigned char uart8250_mem_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base_port)) @@ -79,7 +69,7 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port) return 0x0; } -void uart8250_mem_init(unsigned base_port, unsigned divisor) +static void uart8250_mem_init(unsigned base_port, unsigned divisor) { /* Disable interrupts */ write8(base_port + UART_IER, 0x0); @@ -100,36 +90,45 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -u32 uart_mem_init(void) +void uart_init(void) { - u32 uart_bar = 0; - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - - if (dev) { - struct resource *res = find_resource(dev, 0x10); - - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } - - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART -#endif + u32 base = uart_platform_base(0); + if (!base) + return; unsigned int refclk = uart_platform_refclk(); unsigned int div = uart_baudrate_divisor(refclk); - if (uart_bar) - uart8250_mem_init(uart_bar, div); + uart8250_mem_init(base, div); +} - return uart_bar; +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} + +int uart_can_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0; + return uart8250_mem_can_rx_byte(base); +} + +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); }

1 0

Patch set updated for coreboot: f3208e0 uart8250io: Unify calls with generic UART
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5234 -gerrit commit f3208e04af4f1ed1738f778dc822811b5d51a0c3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 07:53:18 2014 +0200 uart8250io: Unify calls with generic UART Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 8 +++--- src/arch/x86/lib/romstage_console.c | 6 ++--- src/console/uart8250_console.c | 10 ++++---- src/cpu/x86/smm/smiutil.c | 2 +- src/include/console/uart.h | 5 ++-- src/include/uart8250.h | 10 -------- src/lib/uart8250.c | 51 ++++++++++++++++++++++++------------- 7 files changed, 48 insertions(+), 44 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 52b8a87..1ed498a 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/uart.h> #include <console/ne2k.h> /* __PRE_RAM__ */ @@ -28,9 +29,6 @@ * we could use the same code on all architectures. */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 -#include <uart8250.h> -#endif #if CONFIG_CONSOLE_SERIAL8250 #include "drivers/uart/util.c" @@ -43,7 +41,7 @@ static void __console_tx_byte(unsigned char byte) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -64,7 +62,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4cd5d2d..045890d 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,7 +26,7 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -42,7 +42,7 @@ void console_tx_byte(unsigned char byte) } #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usbdebug_tx_byte(dbgp_console_output(), byte); @@ -64,7 +64,7 @@ void console_tx_flush(void) uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 196412c..52f59f6 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -18,7 +18,7 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> static void ttyS0_init(void) { @@ -27,22 +27,22 @@ static void ttyS0_init(void) static void ttyS0_tx_byte(unsigned char data) { - uart8250_tx_byte(CONFIG_TTYS0_BASE, data); + uart_tx_byte(data); } static void ttyS0_tx_flush(void) { - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); } static unsigned char ttyS0_rx_byte(void) { - return uart8250_rx_byte(CONFIG_TTYS0_BASE); + return uart_rx_byte(); } static int ttyS0_tst_byte(void) { - return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); + return uart_can_rx_byte(); } static const struct console_driver uart8250_console __console = { diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 98ef223..3702e5c 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -45,7 +45,7 @@ void console_tx_byte(unsigned char byte) uart8250_mem_tx_byte(serial8250mem_base_address, byte); #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif } diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 9071ddf..27be2e8 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -30,10 +30,11 @@ unsigned int uart_platform_refclk(void); unsigned int uart_baudrate_divisor(unsigned int refclk); -unsigned char uart_rx_byte(void); +void uart_init(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); -void uart_init(void); +unsigned char uart_rx_byte(void); +int uart_can_rx_byte(void); uint32_t uartmem_getbaseaddr(void); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index af95796..100a216 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -105,16 +105,6 @@ #define UART_SCR 0x07 #define UART_SPR 0x07 -#if CONFIG_CONSOLE_SERIAL8250 -unsigned char uart8250_rx_byte(unsigned base_port); -int uart8250_can_rx_byte(unsigned base_port); -void uart8250_tx_byte(unsigned base_port, unsigned char data); -void uart8250_tx_flush(unsigned base_port); -/* Yes it is silly to have three different uart init functions. But we used to - * have three different sets of uart code, so it's an improvement. - */ -void uart8250_init(unsigned base_port, unsigned divisor); -#endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 9f3ad9b..d5e845c 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -38,40 +38,30 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static inline int uart8250_can_tx_byte(unsigned base_port) +static int uart8250_can_tx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_THRE; } -static inline void uart8250_wait_to_tx_byte(unsigned base_port) +static void uart8250_tx_byte(unsigned base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_tx_byte(base_port)); + outb(data, base_port + UART_TBR); } -static inline void uart8250_wait_until_sent(unsigned base_port) +static void uart8250_tx_flush(unsigned base_port) { unsigned long int i = FIFO_TIMEOUT; while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); } -void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_wait_to_tx_byte(base_port); - outb(data, base_port + UART_TBR); -} - -void uart8250_tx_flush(unsigned base_port) -{ - uart8250_wait_until_sent(base_port); -} - -int uart8250_can_rx_byte(unsigned base_port) +static int uart8250_can_rx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_rx_byte(unsigned base_port) +static unsigned char uart8250_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_rx_byte(base_port)); @@ -82,7 +72,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) return 0x0; } -void uart8250_init(unsigned base_port, unsigned divisor) +static void uart8250_init(unsigned base_port, unsigned divisor) { DISABLE_TRACE; /* Disable interrupts */ @@ -105,8 +95,33 @@ void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } +/* FIXME: Needs uart index from Kconfig. + * Already use array as a work-around for ROMCC. + */ +static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; + void uart_init(void) { unsigned int div = uart_baudrate_divisor(BAUDRATE_REFCLK); - uart8250_init(CONFIG_TTYS0_BASE, div); + uart8250_init(bases[0], div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(bases[0], data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(bases[0]); +} + +int uart_can_rx_byte(void) +{ + return uart8250_can_rx_byte(bases[0]); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(bases[0]); }

1 0

Patch set updated for coreboot: 933ebda uart8250: Move under drivers/uart
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5236 -gerrit commit 933ebdab4f53d4599943d357f08b0d6ffc7da8c5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 30 15:45:16 2014 +0200 uart8250: Move under drivers/uart Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 2 +- src/cpu/allwinner/a10/uart.c | 2 +- src/drivers/uart/Makefile.inc | 12 ++++ src/drivers/uart/uart8250io.c | 127 +++++++++++++++++++++++++++++++++++++ src/drivers/uart/uart8250mem.c | 134 +++++++++++++++++++++++++++++++++++++++ src/drivers/uart/uart8250reg.h | 108 +++++++++++++++++++++++++++++++ src/include/uart8250.h | 108 ------------------------------- src/lib/Makefile.inc | 6 -- src/lib/uart8250.c | 127 ------------------------------------- src/lib/uart8250mem.c | 134 --------------------------------------- 10 files changed, 383 insertions(+), 377 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 1ed498a..66c81db 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -32,7 +32,7 @@ #if CONFIG_CONSOLE_SERIAL8250 #include "drivers/uart/util.c" -#include "lib/uart8250.c" +#include "drivers/uart/uart8250io.c" #endif #if CONFIG_CONSOLE_NE2K #include "drivers/net/ne2k.c" diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index 97ac302..7dad1ca 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -7,7 +7,7 @@ #include "uart.h" #include <arch/io.h> -#include <uart8250.h> +#include <drivers/uart/uart8250reg.h> /** * \brief Configure line control settings for UART diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 52a7024..3a9ca3d 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -5,6 +5,18 @@ bootblock-y += util.c smm-y += util.c endif +ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +romstage-y += uart8250io.c +ramstage-y += uart8250io.c +smm-y += uart8250io.c +endif + +ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +romstage-y += uart8250mem.c +ramstage-y += uart8250mem.c +smm-y += uart8250mem.c +endif + ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) ifeq ($(CONFIG_DRIVERS_UART_PL011),y) diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c new file mode 100644 index 0000000..6c08ce2 --- /dev/null +++ b/src/drivers/uart/uart8250io.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <trace.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* No reports of super-IOs that would use different clock for + * baudrate reference. */ +#define BAUDRATE_REFCLK 115200 + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static int uart8250_can_tx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_THRE; +} + +static void uart8250_tx_byte(unsigned base_port, unsigned char data) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_tx_byte(base_port)); + outb(data, base_port + UART_TBR); +} + +static void uart8250_tx_flush(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); +} + +static int uart8250_can_rx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_rx_byte(base_port)); + + if (i) + return inb(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_init(unsigned base_port, unsigned divisor) +{ + DISABLE_TRACE; + /* Disable interrupts */ + outb(0x0, base_port + UART_IER); + /* Enable FIFOs */ + outb(UART_FCR_FIFO_EN, base_port + UART_FCR); + + /* assert DTR and RTS so the other end is happy */ + outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); + + /* DLAB on */ + outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + outb(divisor & 0xFF, base_port + UART_DLL); + outb((divisor >> 8) & 0xFF, base_port + UART_DLM); + + /* Set to 3 for 8N1 */ + outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); + ENABLE_TRACE; +} + +/* FIXME: Needs uart index from Kconfig. + * Already use array as a work-around for ROMCC. + */ +static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; + +void uart_init(void) +{ + unsigned int div = uart_baudrate_divisor(BAUDRATE_REFCLK); + uart8250_init(bases[0], div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(bases[0], data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(bases[0]); +} + +int uart_can_rx_byte(void) +{ + return uart8250_can_rx_byte(bases[0]); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(bases[0]); +} diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c new file mode 100644 index 0000000..dded007 --- /dev/null +++ b/src/drivers/uart/uart8250mem.c @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <device/device.h> +#include <delay.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static int uart8250_mem_can_tx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_THRE; +} + +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_tx_byte(base_port)) + udelay(1); + write8(base_port + UART_TBR, data); +} + +static void uart8250_mem_tx_flush(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) + udelay(1); +} + +static int uart8250_mem_can_rx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_mem_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_rx_byte(base_port)) + udelay(1); + if (i) + return read8(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_mem_init(unsigned base_port, unsigned divisor) +{ + /* Disable interrupts */ + write8(base_port + UART_IER, 0x0); + /* Enable FIFOs */ + write8(base_port + UART_FCR, UART_FCR_FIFO_EN); + + /* Assert DTR and RTS so the other end is happy */ + write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); + + /* DLAB on */ + write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + write8(base_port + UART_DLL, divisor & 0xFF); + write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); + + /* Set to 3 for 8N1 */ + write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); +} + +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + + unsigned int refclk = uart_platform_refclk(); + unsigned int div = uart_baudrate_divisor(refclk); + uart8250_mem_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} + +int uart_can_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0; + return uart8250_mem_can_rx_byte(base); +} + +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); +} diff --git a/src/drivers/uart/uart8250reg.h b/src/drivers/uart/uart8250reg.h new file mode 100644 index 0000000..cdfbb1b --- /dev/null +++ b/src/drivers/uart/uart8250reg.h @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef UART8250REG_H +#define UART8250REG_H + +/* Data */ +#define UART_RBR 0x00 +#define UART_TBR 0x00 + +/* Control */ +#define UART_IER 0x01 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +#define UART_IIR 0x02 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +#define UART_FCR 0x02 +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +#define UART_LCR 0x03 +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity enable */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +#define UART_MCR 0x04 +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* Status */ +#define UART_LSR 0x05 +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR 0x06 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +#define UART_SCR 0x07 +#define UART_SPR 0x07 + +#endif /* UART8250REG_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h deleted file mode 100644 index c63153c..0000000 --- a/src/include/uart8250.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef UART8250_H -#define UART8250_H - -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ - -#define UART_IIR 0x02 -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ - -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ - -#define UART_FCR 0x02 -#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ - -#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ - -#define UART_LCR 0x03 -#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ -#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ -#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ -#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */ -#define UART_LCR_PEN 0x08 /* Parity enable */ -#define UART_LCR_EPS 0x10 /* Even Parity Select */ -#define UART_LCR_STKP 0x20 /* Stick Parity */ -#define UART_LCR_SBRK 0x40 /* Set Break */ -#define UART_LCR_BKSE 0x80 /* Bank select enable */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ - -#define UART_MCR 0x04 -#define UART_MCR_DTR 0x01 /* DTR */ -#define UART_MCR_RTS 0x02 /* RTS */ -#define UART_MCR_OUT1 0x04 /* Out 1 */ -#define UART_MCR_OUT2 0x08 /* Out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ - -#define UART_MCR_DMA_EN 0x04 -#define UART_MCR_TX_DFR 0x08 - -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_OE 0x02 /* Overrun */ -#define UART_LSR_PE 0x04 /* Parity error */ -#define UART_LSR_FE 0x08 /* Framing error */ -#define UART_LSR_BI 0x10 /* Break */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART_LSR_ERR 0x80 /* Error */ - -#define UART_MSR 0x06 -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ - -#define UART_SCR 0x07 -#define UART_SPR 0x07 - -#endif /* UART8250_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5c37329..6641318 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -46,8 +46,6 @@ romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -87,8 +85,6 @@ ramstage-y += stack.c ramstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += clog2.c romstage-y += clog2.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c @@ -125,8 +121,6 @@ ifneq ($(CONFIG_HAVE_ARCH_MEMMOVE),y) smm-y += memmove.c endif smm-y += cbfs.c memcmp.c -smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c smm-y += gcc.c $(obj)/lib/version.ramstage.o : $(obj)/build.h diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c deleted file mode 100644 index d5e845c..0000000 --- a/src/lib/uart8250.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <uart8250.h> -#include <trace.h> - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* No reports of super-IOs that would use different clock for - * baudrate reference. */ -#define BAUDRATE_REFCLK 115200 - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - * - * Estimated that inb() from UART takes 1 microsecond. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static int uart8250_can_tx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_THRE; -} - -static void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_tx_byte(base_port)); - outb(data, base_port + UART_TBR); -} - -static void uart8250_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); -} - -static int uart8250_can_rx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_rx_byte(base_port)); - - if (i) - return inb(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_init(unsigned base_port, unsigned divisor) -{ - DISABLE_TRACE; - /* Disable interrupts */ - outb(0x0, base_port + UART_IER); - /* Enable FIFOs */ - outb(UART_FCR_FIFO_EN, base_port + UART_FCR); - - /* assert DTR and RTS so the other end is happy */ - outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); - - /* DLAB on */ - outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - outb(divisor & 0xFF, base_port + UART_DLL); - outb((divisor >> 8) & 0xFF, base_port + UART_DLM); - - /* Set to 3 for 8N1 */ - outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); - ENABLE_TRACE; -} - -/* FIXME: Needs uart index from Kconfig. - * Already use array as a work-around for ROMCC. - */ -static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; - -void uart_init(void) -{ - unsigned int div = uart_baudrate_divisor(BAUDRATE_REFCLK); - uart8250_init(bases[0], div); -} - -void uart_tx_byte(unsigned char data) -{ - uart8250_tx_byte(bases[0], data); -} - -unsigned char uart_rx_byte(void) -{ - return uart8250_rx_byte(bases[0]); -} - -int uart_can_rx_byte(void) -{ - return uart8250_can_rx_byte(bases[0]); -} - -void uart_tx_flush(void) -{ - uart8250_tx_flush(bases[0]); -} diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c deleted file mode 100644 index fb471fb..0000000 --- a/src/lib/uart8250mem.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <uart8250.h> -#include <device/device.h> -#include <delay.h> - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static int uart8250_mem_can_tx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_THRE; -} - -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); - write8(base_port + UART_TBR, data); -} - -static void uart8250_mem_tx_flush(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) - udelay(1); -} - -static int uart8250_mem_can_rx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read8(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned base_port, unsigned divisor) -{ - /* Disable interrupts */ - write8(base_port + UART_IER, 0x0); - /* Enable FIFOs */ - write8(base_port + UART_FCR, UART_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); - - /* DLAB on */ - write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - write8(base_port + UART_DLL, divisor & 0xFF); - write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); -} - -void uart_init(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - - unsigned int refclk = uart_platform_refclk(); - unsigned int div = uart_baudrate_divisor(refclk); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(unsigned char data) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_byte(base, data); -} - -unsigned char uart_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0xff; - return uart8250_mem_rx_byte(base); -} - -int uart_can_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0; - return uart8250_mem_can_rx_byte(base); -} - -void uart_tx_flush(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_flush(base); -}

1 0

Patch set updated for coreboot: 3e5ad71 uart: Do not guard entire include file by config options
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4585 -gerrit commit 3e5ad71a7e612fd80fbb0cb0b4c2681d73e7ed9e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 17 11:36:29 2014 +0200 uart: Do not guard entire include file by config options Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL. Don't do indirect includes for <uart8250.h>. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 5 ----- src/include/uart.h | 14 -------------- src/include/uart8250.h | 5 ----- 3 files changed, 24 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index dc98bff..97ac302 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -7,11 +7,6 @@ #include "uart.h" #include <arch/io.h> - -/* Give me my 8250 UART definitions!!!! */ -/* TODO: Clean this up when uart8250mem works on ARM */ -#undef CONFIG_CONSOLE_SERIAL8250MEM -#define CONFIG_CONSOLE_SERIAL8250MEM 1 #include <uart8250.h> /** diff --git a/src/include/uart.h b/src/include/uart.h index e24699b..98d77e7 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -17,12 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* madness. Uarts are a mess. If you include this file, it - * includes ALL uart implementations which may be needed. - * No need to include them separately, and include this file FIRST. - * At least one (but at most one) of the files needs to define - * uart_init(). - */ #ifndef UART_H #define UART_H @@ -36,19 +30,11 @@ unsigned int uart_platform_refclk(void); unsigned int uart_baudrate_divisor(unsigned int refclk); -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - -#if CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); void uart_init(void); -#endif -#if CONFIG_HAVE_UART_MEMORY_MAPPED uint32_t uartmem_getbaseaddr(void); -#endif #endif /* UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 0c5ee77..112cd44 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,8 +20,6 @@ #ifndef UART8250_H #define UART8250_H -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -116,7 +114,6 @@ void uart8250_tx_flush(unsigned base_port); * have three different sets of uart code, so it's an improvement. */ void uart8250_init(unsigned base_port, unsigned divisor); -void uart_init(void); #endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); @@ -137,6 +134,4 @@ void oxford_init(void); #endif #endif -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - #endif /* UART8250_H */

1 0

New patch to review for coreboot: 0372b68 SMM: Fixes for DEBUG_SMI
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5258 -gerrit commit 0372b68005d2825d6736b26087f00c7777ae4fb2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 17 22:32:02 2014 +0200 SMM: Fixes for DEBUG_SMI Get the required UART includes directly. The ne2k part is old copy-paste leftover. Change-Id: Ifd9253abb5a50b515887459faf06b63f907eeda9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/smm/smiutil.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 13ee12e..a50a16a 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -23,6 +23,8 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <console/console.h> +#include <uart.h> +#include <uart8250.h> #include <console/vtxprintf.h> #if CONFIG_CONSOLE_SERIAL8250MEM @@ -45,9 +47,6 @@ void console_tx_byte(unsigned char byte) #if CONFIG_CONSOLE_SERIAL8250 uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); #endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } void console_init(void)

1 0

Patch set updated for coreboot: a7d2431 pl011 UART: Move under drivers/uart
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5162 -gerrit commit a7d24312457b1bf7834f80ce20f1c2a7bffd7eed Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 10 23:21:14 2014 +0200 pl011 UART: Move under drivers/uart Currently this is only a minimal stub to get console on qemu-armv7. Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/uart/Kconfig | 4 ++ src/drivers/uart/Makefile.inc | 10 +++++ src/drivers/uart/pl011.c | 50 +++++++++++++++++++++ src/mainboard/emulation/qemu-armv7/Kconfig | 8 +++- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 -- src/mainboard/emulation/qemu-armv7/uart.c | 60 ------------------------- 6 files changed, 70 insertions(+), 66 deletions(-) diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index c1c3090..5c9a9d1 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -12,3 +12,7 @@ config HAVE_UART_SPECIAL bool default n +config DRIVERS_UART_PL011 + bool + default n + select HAVE_UART_SPECIAL diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index c797d4b..52a7024 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -4,3 +4,13 @@ ramstage-y += util.c bootblock-y += util.c smm-y += util.c endif + +ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) + +ifeq ($(CONFIG_DRIVERS_UART_PL011),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c +romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c +ramstage-y += pl011.c +endif + +endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c new file mode 100644 index 0000000..af085ac --- /dev/null +++ b/src/drivers/uart/pl011.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <uart.h> + +static void pl011_uart_tx_byte(unsigned char data) +{ + static volatile unsigned int *uart0_address = + (unsigned int *) CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + + *uart0_address = (unsigned int)data; +} + +#if !defined(__PRE_RAM__) + +static const struct console_driver pl011_uart_console __console = { + .tx_byte = pl011_uart_tx_byte, +}; + +uint32_t uartmem_getbaseaddr(void) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} +#else +void uart_init(void) +{ +} + +void uart_tx_byte(unsigned char data) +{ + pl011_uart_tx_byte(data); +} + +void uart_tx_flush(void) +{ +} +#endif diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 9ab9767..edba627 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -25,8 +25,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 - select HAVE_UART_MEMORY_MAPPED - select HAVE_UART_SPECIAL + select DRIVERS_UART_PL011 select BOARD_ROMSIZE_KB_4096 config MAINBOARD_DIR @@ -49,6 +48,11 @@ config DRAM_SIZE_MB int default 1024 +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on CONSOLE_SERIAL_UART + default 0x10009000 + # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index 431d9ab..d15495f 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,7 +21,3 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c - -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -romstage-$(CONFIG_EARLY_CONSOLE) += uart.c -ramstage-y += uart.c diff --git a/src/mainboard/emulation/qemu-armv7/uart.c b/src/mainboard/emulation/qemu-armv7/uart.c deleted file mode 100644 index dfe5d0a..0000000 --- a/src/mainboard/emulation/qemu-armv7/uart.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <uart.h> - -#define VEXPRESS_UART0_IO_ADDRESS (0x10009000) - -static void pl011_init_dev(void) { -} - -static void pl011_uart_tx_byte(unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *)VEXPRESS_UART0_IO_ADDRESS; - - *uart0_address = (unsigned int)data; -} - -static void pl011_uart_tx_flush(void) { -} - -#if !defined(__PRE_RAM__) - -static const struct console_driver pl011_uart_console __console = { - .init = pl011_init_dev, - .tx_byte = pl011_uart_tx_byte, - .tx_flush = pl011_uart_tx_flush, -}; - -uint32_t uartmem_getbaseaddr(void) -{ - return VEXPRESS_UART0_IO_ADDRESS; -} -#else -void uart_init(void) -{ - pl011_init_dev(); -} - -void uart_tx_byte(unsigned char data) -{ - pl011_uart_tx_byte(data); -} - -void uart_tx_flush(void) { - pl011_uart_tx_flush(); -} -#endif

1 0

Patch set updated for coreboot: c0ffb4a option: Add arch-agnostic get_option()
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5157 -gerrit commit c0ffb4a9d6468a4c5b45e5bd4e65c0fe7e342ef1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 10:02:53 2014 +0200 option: Add arch-agnostic get_option() We should not have pc80/ includes in console/. Change-Id: Id7da732b1ea094be01f45f9dbb49142f4e78f095 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 13 +------------ src/drivers/uart/util.c | 2 +- src/include/option.h | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 38ac3e7..081113c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -25,18 +25,7 @@ #ifndef __PRE_RAM__ #include <string.h> #include <types.h> - -/* - * FIXME: get_option() needs to be abstracted better so that other non-volatile - * storage can be used. This will benefit machines without CMOS as well as those - * without a battery-backed CMOS (e.g. some laptops). - */ -#if CONFIG_USE_OPTION_TABLE -#include <pc80/mc146818rtc.h> -#else -static inline enum cb_err get_option(void *dest, const char *name) - { return CB_CMOS_OTABLE_DISABLED; } -#endif +#include <option.h> /* initialize the console */ void console_init(void) diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index 5e9b5e6..a3bfd3b 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -18,7 +18,7 @@ #include <console/console.h> #include <uart.h> #if CONFIG_USE_OPTION_TABLE -#include <pc80/mc146818rtc.h> +#include <option.h> #include "option_table.h" #endif diff --git a/src/include/option.h b/src/include/option.h new file mode 100644 index 0000000..83f3a84 --- /dev/null +++ b/src/include/option.h @@ -0,0 +1,19 @@ +#ifndef _OPTION_H_ +#define _OPTION_H_ + +/* + * FIXME: get_option() needs to be abstracted better so that other non-volatile + * storage can be used. This will benefit machines without CMOS as well as those + * without a battery-backed CMOS (e.g. some laptops). + */ +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#else +#include <types.h> +static inline enum cb_err get_option(void *dest, const char *name) +{ + return CB_CMOS_OTABLE_DISABLED; +} +#endif + +#endif /* _OPTION_H_ */

1 0

Patch set updated for coreboot: 5eeeafd uart: Do not guard entire include file by config options
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4585 -gerrit commit 5eeeafddb9ae5f9a338e0ae32f702fe430778c43 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 17 11:36:29 2014 +0200 uart: Do not guard entire include file by config options Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL. Don't do indirect includes for <uart8250.h>. The config-specific options are already properly guarded, and there is no need to guard the register and bit definitions. Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart.c | 5 ----- src/include/uart.h | 14 -------------- src/include/uart8250.h | 5 ----- 3 files changed, 24 deletions(-) diff --git a/src/cpu/allwinner/a10/uart.c b/src/cpu/allwinner/a10/uart.c index dc98bff..97ac302 100644 --- a/src/cpu/allwinner/a10/uart.c +++ b/src/cpu/allwinner/a10/uart.c @@ -7,11 +7,6 @@ #include "uart.h" #include <arch/io.h> - -/* Give me my 8250 UART definitions!!!! */ -/* TODO: Clean this up when uart8250mem works on ARM */ -#undef CONFIG_CONSOLE_SERIAL8250MEM -#define CONFIG_CONSOLE_SERIAL8250MEM 1 #include <uart8250.h> /** diff --git a/src/include/uart.h b/src/include/uart.h index e24699b..98d77e7 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -17,12 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* madness. Uarts are a mess. If you include this file, it - * includes ALL uart implementations which may be needed. - * No need to include them separately, and include this file FIRST. - * At least one (but at most one) of the files needs to define - * uart_init(). - */ #ifndef UART_H #define UART_H @@ -36,19 +30,11 @@ unsigned int uart_platform_refclk(void); unsigned int uart_baudrate_divisor(unsigned int refclk); -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - -#if CONFIG_CONSOLE_SERIAL_UART unsigned char uart_rx_byte(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); void uart_init(void); -#endif -#if CONFIG_HAVE_UART_MEMORY_MAPPED uint32_t uartmem_getbaseaddr(void); -#endif #endif /* UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h index 0c5ee77..112cd44 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -20,8 +20,6 @@ #ifndef UART8250_H #define UART8250_H -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - /* Data */ #define UART_RBR 0x00 #define UART_TBR 0x00 @@ -116,7 +114,6 @@ void uart8250_tx_flush(unsigned base_port); * have three different sets of uart code, so it's an improvement. */ void uart8250_init(unsigned base_port, unsigned divisor); -void uart_init(void); #endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); @@ -137,6 +134,4 @@ void oxford_init(void); #endif #endif -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - #endif /* UART8250_H */

1 0

Patch set updated for coreboot: 2fa65a6 uart: Unify baudrate divisor calculation
by Kyösti Mälkki 17 Feb '14

17 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5229 -gerrit commit 2fa65a66877cd14df5f8d7bea59b434c60cebdda Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 17 19:37:52 2014 +0200 uart: Unify baudrate divisor calculation Divisor is a function of requested baudrate and platform-specific clock used for UART reference. Combine this with the capability to read baudrate from option_table. When building without option_table or when there is no entry for baud_rate, CONFIG_TTYS0_BAUD is used. FIXME: Field for baudrate in lb_tables is still incorrect. Change-Id: I68539738469af780fadd3392263dd9b3d5964d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 1 + src/drivers/oxford/oxpcie/oxpcie_early.c | 10 +++++- src/drivers/uart/Makefile.inc | 6 ++++ src/drivers/uart/util.c | 54 ++++++++++++++++++++++++++++++++ src/include/uart.h | 10 ++++++ src/include/uart8250.h | 4 --- src/lib/uart8250.c | 32 ++++--------------- src/lib/uart8250mem.c | 26 ++------------- 8 files changed, 89 insertions(+), 54 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index db84f9e..c5e6882 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -32,6 +32,7 @@ #endif #if CONFIG_CONSOLE_SERIAL8250 +#include "drivers/uart/util.c" #include "lib/uart8250.c" #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d04e9d4..edb97d5 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> +#include <uart.h> #include <uart8250.h> #include <device/pci_def.h> @@ -116,7 +117,14 @@ void oxford_init(void) /* Now the UART initialization */ u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; - uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); + unsigned int refclk = uart_platform_refclk(); + unsigned int div = uart_baudrate_divisor(refclk); + uart8250_mem_init(uart0_base, div); } #endif + +unsigned int uart_platform_refclk(void) +{ + return 4000000; +} diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc new file mode 100644 index 0000000..c797d4b --- /dev/null +++ b/src/drivers/uart/Makefile.inc @@ -0,0 +1,6 @@ +ifeq ($(CONFIG_CONSOLE_SERIAL),y) +romstage-y += util.c +ramstage-y += util.c +bootblock-y += util.c +smm-y += util.c +endif diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c new file mode 100644 index 0000000..5e9b5e6 --- /dev/null +++ b/src/drivers/uart/util.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <uart.h> +#if CONFIG_USE_OPTION_TABLE +#include <pc80/mc146818rtc.h> +#include "option_table.h" +#endif + +#if CONFIG_CONSOLE_SERIAL +/* Treat the default base frequency 115200 as a special case + * to avoid runtime division. Might help ROMCC builds. + */ +unsigned int uart_baudrate_divisor(unsigned int basefreq) +{ + unsigned div = (basefreq / CONFIG_TTYS0_BAUD); + +#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE + static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; + static const unsigned baud[8] = + { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; + unsigned b_index = 0; +#if defined(__PRE_RAM__) + b_index = read_option(baud_rate, 0xff); +#else + if (get_option(&b_index, "baud_rate") != CB_SUCCESS) + b_index = 0xff; +#endif + if (b_index < 8) { + if (basefreq == 115200) + div = divisor[b_index]; + else + div = (basefreq / baud[b_index]); + } +#endif + return div; +} + +#endif diff --git a/src/include/uart.h b/src/include/uart.h index 9601bfa..e24699b 100644 --- a/src/include/uart.h +++ b/src/include/uart.h @@ -26,6 +26,16 @@ #ifndef UART_H #define UART_H +/* Return the clock frequency UART uses as reference clock for + * baudrate generator. */ +unsigned int uart_platform_refclk(void); + +/* Return the divisor that configures UART for baudrate detemined + * from option_table, or when that is not used, CONFIG_TTYS0_BAUD. + */ +unsigned int uart_baudrate_divisor(unsigned int refclk); + + #if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif diff --git a/src/include/uart8250.h b/src/include/uart8250.h index bec3637..0c5ee77 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -107,10 +107,6 @@ #define UART_SCR 0x07 #define UART_SPR 0x07 -#if ((115200 % CONFIG_TTYS0_BAUD) != 0) -#error Bad ttyS0 baud rate -#endif - #if CONFIG_CONSOLE_SERIAL8250 unsigned char uart8250_rx_byte(unsigned base_port); int uart8250_can_rx_byte(unsigned base_port); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index aa18d2a..9dcd388 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -19,16 +19,16 @@ */ #include <arch/io.h> +#include <uart.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> #include <trace.h> -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#endif - /* Should support 8250, 16450, 16550, 16550A type UARTs */ +/* No reports of super-IOs that would use different clock for + * baudrate reference. */ +#define BAUDRATE_REFCLK 115200 + /* Expected character delay at 1200bps is 9ms for a working UART * and no flow-control. Assume UART as stuck if shift register * or FIFO takes more than 50ms per character to appear empty. @@ -107,26 +107,6 @@ void uart8250_init(unsigned base_port, unsigned divisor) void uart_init(void) { - /* TODO the divisor calculation is hard coded to standard UARTs. Some - * UARTs won't work with these values. This should be a property of the - * UART used, worst case a Kconfig variable. For now live with hard - * codes as the only devices that might be different are the iWave - * iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped) - */ - unsigned int div = (115200 / CONFIG_TTYS0_BAUD); - -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - div = divisor[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - div = divisor[b_index]; -#endif -#endif - + unsigned int div = uart_baudrate_divisor(BAUDRATE_REFCLK); uart8250_init(CONFIG_TTYS0_BASE, div); } diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 1482142..a370e50 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -19,11 +19,8 @@ */ #include <arch/io.h> +#include <uart.h> #include <uart8250.h> -#include <pc80/mc146818rtc.h> -#if CONFIG_USE_OPTION_TABLE -#include "option_table.h" -#endif #include <device/device.h> #include <delay.h> @@ -105,27 +102,10 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) u32 uart_mem_init(void) { - unsigned uart_baud = CONFIG_TTYS0_BAUD; u32 uart_bar = 0; - unsigned div; - - /* find out the correct baud rate */ -#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE - static const unsigned baud[8] = { 115200, 57600, 38400, 19200, 9600, 4800, 2400, 1200 }; - unsigned b_index = 0; -#if defined(__PRE_RAM__) - b_index = read_option(baud_rate, 0); - b_index &= 7; - uart_baud = baud[b_index]; -#else - if (get_option(&b_index, "baud_rate") == CB_SUCCESS) - uart_baud = baud[b_index]; -#endif -#endif /* Now find the UART base address and calculate the divisor */ #if CONFIG_DRIVERS_OXFORD_OXPCIE - #if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) device_t dev = dev_find_device(0x1415, 0xc158, NULL); if (!dev) @@ -144,10 +124,10 @@ u32 uart_mem_init(void) #endif uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART - - div = 4000000 / uart_baud; #endif + unsigned int refclk = uart_platform_refclk(); + unsigned int div = uart_baudrate_divisor(refclk); if (uart_bar) uart8250_mem_init(uart_bar, div);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2014