coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 228a3a2 baytrail: SMM support
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 228a3a28a5f253780314821671a79223f9a962d5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 21 22:32:00 2013 -0500 baytrail: SMM support Initialize SMM on all CPUs by relocating the SMM region and setting SMRR on all the cores. Additionally SMI is enabled in the south cluster. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi. Tested with DEBUG_SMI and noted power button turns off board while in firmware. Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173983 See http://review.coreboot.org/4892 for details. -gerrit

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Patch merged into coreboot/master: bd75c21 haswell: backup the default SMM region on resume
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit bd75c215c7e0f2d2827a1940bfd8cbef3a62dd51 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 13 10:30:42 2014 -0600 haswell: backup the default SMM region on resume Haswell CPUs need to use the default SMM region for relocating to the desired SMM location. Back up that memory on resume instead of reserving the default region. This makes the haswell support more forgiving to software which expects PC-compatible memory layouts. Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5217 for details. -gerrit

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Patch merged into coreboot/master: dad6d79 x86: provide infrastructure to backup default SMM region
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit dad6d794d27bbecf4e46499a38543a481050d2d1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Feb 13 10:26:18 2014 -0600 x86: provide infrastructure to backup default SMM region Certain CPUs require the default SMM region to be backed up on resume after a suspend. The reason is that in order to relocate the SMM region the default SMM region has to be used. As coreboot is unaware of how that memory is used it needs to be backed up. Therefore provide a common method for doing this. Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5216 for details. -gerrit

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Patch merged into coreboot/master: 2441fcb intel/jarrell: Fix missing include
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 2441fcb37421ee001fa053dab46ecb3a7c84bd30 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 07:20:13 2014 +0200 intel/jarrell: Fix missing include To unconditionally get cmos_read(). Change-Id: I0af0e85c8a1f42113bd32b51c4e29e86b3c28112 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5228 for details. -gerrit

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Patch merged into coreboot/master: 9e2b49f baytrail: bring up APs
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 9e2b49f509a8eda54dca9145ffa7f365d12798e5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 21 12:36:17 2013 -0500 baytrail: bring up APs Bring up the APs using x86 MP infrastructure. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted rambi. Noted all cores are brought up. Change-Id: I9231eff5494444e8eb17ecdc5a0af72a2e5208b5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173704 See http://review.coreboot.org/4889 for details. -gerrit

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Patch merged into coreboot/master: 7a0de3b rambi: add BSP lapic device
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 7a0de3bc9ba4b5131e0e01b6225e14c2dffd4904 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 21 12:11:17 2013 -0500 rambi: add BSP lapic device There's some baked in assumptions internal to coreboot that the BSP's cpu device exists in the device tree. Therefore provide one in the device tree. BUG=chrome-os-partner:22862 BRANCH=None TEST=Compiled and booted with other changes. Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173702 See http://review.coreboot.org/4887 for details. -gerrit

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Patch merged into coreboot/master: 27b9b11 baytrail: Modify GPIO pull-up specification method
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 27b9b1175e1a58b2d40b2680565e01ba6cfb2b79 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Oct 18 17:13:18 2013 -0700 baytrail: Modify GPIO pull-up specification method Minor style changes to the way GPIO pull-ups are specified in board-specific GPIO maps. Intent is to allow calls to GPIO_FUNC macro from such maps. BUG=chrome-os-partner:22863 TEST=Manual. Build + boot on bayleybay. Change-Id: I80134b65d22d3ad8a049837dccc0985e321645da Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173748 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: David James <davidjames(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4886 for details. -gerrit

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Patch merged into coreboot/master: 3ac4460 rambi: disable internal pullups on ram_id[2:0]
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 3ac446036988bca020d902bd9b5c580cd367d9bb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 16 09:21:55 2013 -0700 rambi: disable internal pullups on ram_id[2:0] The ram_id[2:0] signals have stuffing options for pull up/down with values of 10K. However, the default pulldown values for these pads are 20K. Therefore, one can't read a high value because of the high voltage threshold is 0.65 * Vref. Therefore the high signals are marginal at best. Fix this issue by disabling the internal pull for the pads connected to ram_id[2:0]. BUG=chrome-os-partner:23350 BRANCH=None TEST=Built and checked that ram_id[2:0] is properly read now. Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173211 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> See http://review.coreboot.org/4885 for details. -gerrit

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Patch merged into coreboot/master: c5fe9c6 baytrail: correct MMC pci location
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit c5fe9c6780116d10adade54b8a2493ce6b6f7888 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 08:39:54 2013 -0500 baytrail: correct MMC pci location The original documentation was incorrect. Fix the pci device for the MMC port to reflect reality. MMC is at 00:17.0 with a device id of 0x0f50. BUG=None BRANCH=None TEST=Built. Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172772 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4884 for details. -gerrit

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Patch merged into coreboot/master: b0fe6af baytrail: fix tsc rate
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit b0fe6af46c12e516bc2a7088e3ca9979243dc274 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 11 00:44:06 2013 -0500 baytrail: fix tsc rate Despite some references to a fixed bclk in some of the docs the bclk is variable per sku. Therefore, perform the calculation according to the BSEL_CR_OVERCLOCK_CONTROL msr which provides the bclk for the cpu cores in Bay Trail. BUG=chrome-os-partner:23166 BRANCH=None TEST=Built and booted B3. correctly says: clocks_per_usec: 2133 Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172771 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4883 for details. -gerrit

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coreboot-gerrit February 2014