coreboot-gerrit February 2014

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Patch set updated for coreboot: f458d44 uart8250io: Unify calls with generic UART
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5234 -gerrit commit f458d446af1659e97fcaded11e5daa58b3538b1f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 07:53:18 2014 +0200 uart8250io: Unify calls with generic UART Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 8 +++--- src/arch/x86/lib/romstage_console.c | 6 ++--- src/console/uart8250_console.c | 10 +++---- src/include/console/uart.h | 1 + src/include/uart8250.h | 10 ------- src/lib/uart8250.c | 53 ++++++++++++++++++++++++------------- 6 files changed, 46 insertions(+), 42 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 0f0e017..5a88146 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/uart.h> #include <console/ne2k.h> /* __PRE_RAM__ */ @@ -28,9 +29,6 @@ * we could use the same code on all architectures. */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 -#include <uart8250.h> -#endif #include <console/util.c> @@ -44,7 +42,7 @@ static void __console_tx_byte(unsigned char byte) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -65,7 +63,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4981f39..89d7f82 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,7 +26,7 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -42,7 +42,7 @@ void console_tx_byte(unsigned char byte) } #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usb_tx_byte(0, byte); @@ -64,7 +64,7 @@ void console_tx_flush(void) uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 196412c..52f59f6 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -18,7 +18,7 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> static void ttyS0_init(void) { @@ -27,22 +27,22 @@ static void ttyS0_init(void) static void ttyS0_tx_byte(unsigned char data) { - uart8250_tx_byte(CONFIG_TTYS0_BASE, data); + uart_tx_byte(data); } static void ttyS0_tx_flush(void) { - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); } static unsigned char ttyS0_rx_byte(void) { - return uart8250_rx_byte(CONFIG_TTYS0_BASE); + return uart_rx_byte(); } static int ttyS0_tst_byte(void) { - return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); + return uart_can_rx_byte(); } static const struct console_driver uart8250_console __console = { diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 6cd3beb..ac4455a 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -24,6 +24,7 @@ void uart_init(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); unsigned char uart_rx_byte(void); +int uart_can_rx_byte(void); unsigned uart_divisor(unsigned basefreq); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index a214ce1..4d7ebcc 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -26,16 +26,6 @@ #error Bad ttyS0 baud rate #endif -#if CONFIG_CONSOLE_SERIAL8250 -unsigned char uart8250_rx_byte(unsigned base_port); -int uart8250_can_rx_byte(unsigned base_port); -void uart8250_tx_byte(unsigned base_port, unsigned char data); -void uart8250_tx_flush(unsigned base_port); -/* Yes it is silly to have three different uart init functions. But we used to - * have three different sets of uart code, so it's an improvement. - */ -void uart8250_init(unsigned base_port, unsigned divisor); -#endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 4d2cb63..38b1b7f 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -19,7 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> +#include <console/uart.h> #include <trace.h> #include "drivers/uart/uart8250reg.h" @@ -34,40 +34,30 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static inline int uart8250_can_tx_byte(unsigned base_port) +static int uart8250_can_tx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_THRE; } -static inline void uart8250_wait_to_tx_byte(unsigned base_port) +static void uart8250_tx_byte(unsigned base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_tx_byte(base_port)); + outb(data, base_port + UART_TBR); } -static inline void uart8250_wait_until_sent(unsigned base_port) +static void uart8250_tx_flush(unsigned base_port) { unsigned long int i = FIFO_TIMEOUT; while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); } -void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_wait_to_tx_byte(base_port); - outb(data, base_port + UART_TBR); -} - -void uart8250_tx_flush(unsigned base_port) -{ - uart8250_wait_until_sent(base_port); -} - -int uart8250_can_rx_byte(unsigned base_port) +static int uart8250_can_rx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_rx_byte(unsigned base_port) +static unsigned char uart8250_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_rx_byte(base_port)); @@ -78,7 +68,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) return 0x0; } -void uart8250_init(unsigned base_port, unsigned divisor) +static void uart8250_init(unsigned base_port, unsigned divisor) { DISABLE_TRACE; /* Disable interrupts */ @@ -101,8 +91,33 @@ void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } +/* FIXME: Needs uart index from Kconfig. + * Already use array as a work-around for ROMCC. + */ +static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; + void uart_init(void) { unsigned int div = uart_divisor(115200); - uart8250_init(CONFIG_TTYS0_BASE, div); + uart8250_init(bases[0], div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(bases[0], data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(bases[0]); +} + +int uart_can_rx_byte(void) +{ + return uart8250_can_rx_byte(bases[0]); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(bases[0]); }

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Patch set updated for coreboot: 69a03bc uart8250mem: Unify calls with generic UART
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5235 -gerrit commit 69a03bc7d9ac0b32ce7b30c675cb29486d395aaa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 10:19:23 2014 +0200 uart8250mem: Unify calls with generic UART Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 11 +--- src/console/uart8250mem_console.c | 30 +++-------- src/drivers/oxford/oxpcie/oxpcie.c | 3 +- src/drivers/oxford/oxpcie/oxpcie_early.c | 49 ++++++++++++++---- src/include/console/uart.h | 5 +- src/include/uart8250.h | 50 ------------------ src/lib/uart8250mem.c | 87 ++++++++++++++++---------------- 7 files changed, 96 insertions(+), 139 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 89d7f82..6566b2f 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,20 +26,13 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - void console_tx_byte(unsigned char byte) { if (byte == '\n') console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_byte(byte); @@ -61,7 +54,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_flush(); diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index 3833e47..7e52aed 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -18,47 +18,31 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> -static u32 uart_bar = 0; - -void uartmem_init(void) -{ - uart_bar = uart_mem_init(); -} - -u32 uartmem_getbaseaddr(void) +static void uartmem_init(void) { - return uart_bar; + uart_init(); } static void uartmem_tx_byte(unsigned char data) { - if (!uart_bar) - return; - - uart8250_mem_tx_byte(uart_bar, data); + uart_tx_byte(data); } static void uartmem_tx_flush(void) { - uart8250_mem_tx_flush(uart_bar); + uart_tx_flush(); } static unsigned char uartmem_rx_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_rx_byte(uart_bar); + return uart_rx_byte(); } static int uartmem_tst_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_can_rx_byte(uart_bar); + return uart_can_rx_byte(); } static const struct console_driver uart8250mem_console __console = { diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index f719fc7..0b9081f 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -48,7 +48,8 @@ static void oxford_oxpcie_set_resources(struct device *dev) #if CONFIG_CONSOLE_SERIAL8250MEM /* Re-initialize OXPCIe base address after set_resources */ - uartmem_init(); + u32 mmio_base = pci_read_config32(device, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); #endif } diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 693c1e9..b60cd6c 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -18,12 +18,17 @@ */ #include <stdint.h> +#include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> -#include <uart8250.h> +#include <console/uart.h> #include <device/pci_def.h> +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; + #define PCIE_BRIDGE \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ @@ -35,13 +40,9 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) -#if defined(__PRE_RAM__) -int oxford_oxpcie_present CAR_GLOBAL; - -void oxford_init(void) +static void oxpcie_init_bridge(void) { u16 reg16; - oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -100,7 +101,6 @@ void oxford_init(void) break; default: /* No UART here. */ - oxford_oxpcie_present = 0; return; } @@ -113,16 +113,43 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); - /* Now the UART initialization */ - u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; + car_set_var(oxpcie_present, 1); +} - unsigned div = uart_platform_divisor(); - uart8250_mem_init(uart0_base, div); +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); } +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} #endif +unsigned uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + unsigned uart_platform_divisor(void) { return uart_divisor(4000000); } + +uint32_t uartmem_getbaseaddr(void) +{ + return uart_platform_base(0); +} + +void oxford_init(void) +{ + oxpcie_init_bridge(); + uart_init(); +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index ac4455a..5ac7fda 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -30,7 +30,10 @@ int uart_can_rx_byte(void); unsigned uart_divisor(unsigned basefreq); unsigned uart_platform_divisor(void); - +unsigned uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); +void oxford_init(void); +void oxford_remap(u32 new_base); + #endif /* CONSOLE_UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h deleted file mode 100644 index 4d7ebcc..0000000 --- a/src/include/uart8250.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef UART8250_H -#define UART8250_H - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - -#if ((115200 % CONFIG_TTYS0_BAUD) != 0) -#error Bad ttyS0 baud rate -#endif - -#if CONFIG_CONSOLE_SERIAL8250MEM -void uartmem_init(void); - -/* and the same for memory mapped uarts */ -unsigned char uart8250_mem_rx_byte(unsigned base_port); -int uart8250_mem_can_rx_byte(unsigned base_port); -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); -void uart8250_mem_tx_flush(unsigned base_port); -void uart8250_mem_init(unsigned base_port, unsigned divisor); -u32 uart_mem_init(void); - -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; -#endif -#endif - -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - -#include <console/uart.h> - -#endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index cff67d7..029d055 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -19,8 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> -#include <device/device.h> +#include <console/uart.h> #include <delay.h> #include "drivers/uart/uart8250reg.h" @@ -33,42 +32,32 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static inline int uart8250_mem_can_tx_byte(unsigned base_port) +static int uart8250_mem_can_tx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_THRE; } -static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_tx_byte(base_port)) udelay(1); + write8(base_port + UART_TBR, data); } -static inline void uart8250_mem_wait_until_sent(unsigned base_port) +static void uart8250_mem_tx_flush(unsigned base_port) { unsigned long int i = FIFO_TIMEOUT; while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) udelay(1); } -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_mem_wait_to_tx_byte(base_port); - write8(base_port + UART_TBR, data); -} - -void uart8250_mem_tx_flush(unsigned base_port) -{ - uart8250_mem_wait_until_sent(base_port); -} - -int uart8250_mem_can_rx_byte(unsigned base_port) +static int uart8250_mem_can_rx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_mem_rx_byte(unsigned base_port) +static unsigned char uart8250_mem_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base_port)) @@ -79,7 +68,7 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port) return 0x0; } -void uart8250_mem_init(unsigned base_port, unsigned divisor) +static void uart8250_mem_init(unsigned base_port, unsigned divisor) { /* Disable interrupts */ write8(base_port + UART_IER, 0x0); @@ -100,35 +89,45 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -u32 uart_mem_init(void) -{ - u32 uart_bar = 0; - unsigned div = uart_platform_divisor(); - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; - if (dev) { - struct resource *res = find_resource(dev, 0x10); + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART -#endif +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} - if (uart_bar) - uart8250_mem_init(uart_bar, div); +int uart_can_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0; + return uart8250_mem_can_rx_byte(base); +} - return uart_bar; +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); }

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Patch set updated for coreboot: 60193d2 uart8250io: Unify calls with generic UART
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5234 -gerrit commit 60193d2d271557aeca8b1949753240b1dd12767b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 07:53:18 2014 +0200 uart8250io: Unify calls with generic UART Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 8 +++--- src/arch/x86/lib/romstage_console.c | 6 ++--- src/console/uart8250_console.c | 10 ++++---- src/include/console/uart.h | 1 + src/include/uart8250.h | 10 -------- src/lib/uart8250.c | 50 +++++++++++++++++++++++-------------- 6 files changed, 43 insertions(+), 42 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 0f0e017..5a88146 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/uart.h> #include <console/ne2k.h> /* __PRE_RAM__ */ @@ -28,9 +29,6 @@ * we could use the same code on all architectures. */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 -#include <uart8250.h> -#endif #include <console/util.c> @@ -44,7 +42,7 @@ static void __console_tx_byte(unsigned char byte) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -65,7 +63,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4981f39..89d7f82 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,7 +26,7 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -42,7 +42,7 @@ void console_tx_byte(unsigned char byte) } #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usb_tx_byte(0, byte); @@ -64,7 +64,7 @@ void console_tx_flush(void) uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 196412c..52f59f6 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -18,7 +18,7 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> static void ttyS0_init(void) { @@ -27,22 +27,22 @@ static void ttyS0_init(void) static void ttyS0_tx_byte(unsigned char data) { - uart8250_tx_byte(CONFIG_TTYS0_BASE, data); + uart_tx_byte(data); } static void ttyS0_tx_flush(void) { - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); } static unsigned char ttyS0_rx_byte(void) { - return uart8250_rx_byte(CONFIG_TTYS0_BASE); + return uart_rx_byte(); } static int ttyS0_tst_byte(void) { - return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); + return uart_can_rx_byte(); } static const struct console_driver uart8250_console __console = { diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 6cd3beb..ac4455a 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -24,6 +24,7 @@ void uart_init(void); void uart_tx_byte(unsigned char data); void uart_tx_flush(void); unsigned char uart_rx_byte(void); +int uart_can_rx_byte(void); unsigned uart_divisor(unsigned basefreq); diff --git a/src/include/uart8250.h b/src/include/uart8250.h index a214ce1..4d7ebcc 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -26,16 +26,6 @@ #error Bad ttyS0 baud rate #endif -#if CONFIG_CONSOLE_SERIAL8250 -unsigned char uart8250_rx_byte(unsigned base_port); -int uart8250_can_rx_byte(unsigned base_port); -void uart8250_tx_byte(unsigned base_port, unsigned char data); -void uart8250_tx_flush(unsigned base_port); -/* Yes it is silly to have three different uart init functions. But we used to - * have three different sets of uart code, so it's an improvement. - */ -void uart8250_init(unsigned base_port, unsigned divisor); -#endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 4d2cb63..bf51cc6 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -19,7 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> +#include <console/uart.h> #include <trace.h> #include "drivers/uart/uart8250reg.h" @@ -34,40 +34,30 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) -static inline int uart8250_can_tx_byte(unsigned base_port) +static int uart8250_can_tx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_THRE; } -static inline void uart8250_wait_to_tx_byte(unsigned base_port) +static void uart8250_tx_byte(unsigned base_port, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_tx_byte(base_port)); + outb(data, base_port + UART_TBR); } -static inline void uart8250_wait_until_sent(unsigned base_port) +static void uart8250_tx_flush(unsigned base_port) { unsigned long int i = FIFO_TIMEOUT; while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); } -void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_wait_to_tx_byte(base_port); - outb(data, base_port + UART_TBR); -} - -void uart8250_tx_flush(unsigned base_port) -{ - uart8250_wait_until_sent(base_port); -} - -int uart8250_can_rx_byte(unsigned base_port) +static int uart8250_can_rx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_rx_byte(unsigned base_port) +static unsigned char uart8250_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_rx_byte(base_port)); @@ -78,7 +68,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) return 0x0; } -void uart8250_init(unsigned base_port, unsigned divisor) +static void uart8250_init(unsigned base_port, unsigned divisor) { DISABLE_TRACE; /* Disable interrupts */ @@ -101,8 +91,30 @@ void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } +static const unsigned base = CONFIG_TTYS0_BASE; + void uart_init(void) { unsigned int div = uart_divisor(115200); - uart8250_init(CONFIG_TTYS0_BASE, div); + uart8250_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(base); +} + +int uart_can_rx_byte(void) +{ + return uart8250_can_rx_byte(base); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(base); }

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New patch to review for coreboot: 0e23020 vortex86ex: Drop baudrate programming for 10 UARTs
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5251 -gerrit commit 0e230203fe50e037d3a92f7bc4dd5c03834ce93c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 16 06:55:41 2014 +0200 vortex86ex: Drop baudrate programming for 10 UARTs This is responsibility of end-user application. When coreboot does it, it is only for the purpose of debug console. Change-Id: Idbbf9528c60b9b819b7bea9dfe84078a3f055bc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/dmp/vortex86ex/Kconfig | 260 --------------------------- src/southbridge/dmp/vortex86ex/southbridge.c | 4 +- 2 files changed, 1 insertion(+), 263 deletions(-) diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig index b1db0dc..4b130b8 100644 --- a/src/mainboard/dmp/vortex86ex/Kconfig +++ b/src/mainboard/dmp/vortex86ex/Kconfig @@ -518,32 +518,6 @@ config UART1_IRQ default 14 if UART1_IRQ14 default 15 if UART1_IRQ15 -choice - prompt "UART1 Baud rate" - default UART1_BAUD_115200 - depends on UART1_ENABLE - -config UART1_BAUD_115200 - bool "115200" -config UART1_BAUD_57600 - bool "57600" -config UART1_BAUD_38400 - bool "38400" -config UART1_BAUD_19200 - bool "19200" -config UART1_BAUD_9600 - bool "9600" - -endchoice - -config UART1_BAUD - int - depends on UART1_ENABLE - default 115200 if UART1_BAUD_115200 - default 57600 if UART1_BAUD_57600 - default 38400 if UART1_BAUD_38400 - default 19200 if UART1_BAUD_19200 - default 9600 if UART1_BAUD_9600 # end of UART1 # Begin of UART2 @@ -630,32 +604,6 @@ config UART2_IRQ default 14 if UART2_IRQ14 default 15 if UART2_IRQ15 -choice - prompt "UART2 Baud rate" - default UART2_BAUD_115200 - depends on UART2_ENABLE - -config UART2_BAUD_115200 - bool "115200" -config UART2_BAUD_57600 - bool "57600" -config UART2_BAUD_38400 - bool "38400" -config UART2_BAUD_19200 - bool "19200" -config UART2_BAUD_9600 - bool "9600" - -endchoice - -config UART2_BAUD - int - depends on UART2_ENABLE - default 115200 if UART2_BAUD_115200 - default 57600 if UART2_BAUD_57600 - default 38400 if UART2_BAUD_38400 - default 19200 if UART2_BAUD_19200 - default 9600 if UART2_BAUD_9600 # end of UART2 # Begin of UART3 @@ -742,32 +690,6 @@ config UART3_IRQ default 14 if UART3_IRQ14 default 15 if UART3_IRQ15 -choice - prompt "UART3 Baud rate" - default UART3_BAUD_115200 - depends on UART3_ENABLE - -config UART3_BAUD_115200 - bool "115200" -config UART3_BAUD_57600 - bool "57600" -config UART3_BAUD_38400 - bool "38400" -config UART3_BAUD_19200 - bool "19200" -config UART3_BAUD_9600 - bool "9600" - -endchoice - -config UART3_BAUD - int - depends on UART3_ENABLE - default 115200 if UART3_BAUD_115200 - default 57600 if UART3_BAUD_57600 - default 38400 if UART3_BAUD_38400 - default 19200 if UART3_BAUD_19200 - default 9600 if UART3_BAUD_9600 # end of UART3 # Begin of UART4 @@ -854,32 +776,6 @@ config UART4_IRQ default 14 if UART4_IRQ14 default 15 if UART4_IRQ15 -choice - prompt "UART4 Baud rate" - default UART4_BAUD_115200 - depends on UART4_ENABLE - -config UART4_BAUD_115200 - bool "115200" -config UART4_BAUD_57600 - bool "57600" -config UART4_BAUD_38400 - bool "38400" -config UART4_BAUD_19200 - bool "19200" -config UART4_BAUD_9600 - bool "9600" - -endchoice - -config UART4_BAUD - int - depends on UART4_ENABLE - default 115200 if UART4_BAUD_115200 - default 57600 if UART4_BAUD_57600 - default 38400 if UART4_BAUD_38400 - default 19200 if UART4_BAUD_19200 - default 9600 if UART4_BAUD_9600 # end of UART4 # Begin of UART5 @@ -966,32 +862,6 @@ config UART5_IRQ default 14 if UART5_IRQ14 default 15 if UART5_IRQ15 -choice - prompt "UART5 Baud rate" - default UART5_BAUD_115200 - depends on UART5_ENABLE - -config UART5_BAUD_115200 - bool "115200" -config UART5_BAUD_57600 - bool "57600" -config UART5_BAUD_38400 - bool "38400" -config UART5_BAUD_19200 - bool "19200" -config UART5_BAUD_9600 - bool "9600" - -endchoice - -config UART5_BAUD - int - depends on UART5_ENABLE - default 115200 if UART5_BAUD_115200 - default 57600 if UART5_BAUD_57600 - default 38400 if UART5_BAUD_38400 - default 19200 if UART5_BAUD_19200 - default 9600 if UART5_BAUD_9600 # end of UART5 # Begin of UART6 @@ -1078,32 +948,6 @@ config UART6_IRQ default 14 if UART6_IRQ14 default 15 if UART6_IRQ15 -choice - prompt "UART6 Baud rate" - default UART6_BAUD_115200 - depends on UART6_ENABLE - -config UART6_BAUD_115200 - bool "115200" -config UART6_BAUD_57600 - bool "57600" -config UART6_BAUD_38400 - bool "38400" -config UART6_BAUD_19200 - bool "19200" -config UART6_BAUD_9600 - bool "9600" - -endchoice - -config UART6_BAUD - int - depends on UART6_ENABLE - default 115200 if UART6_BAUD_115200 - default 57600 if UART6_BAUD_57600 - default 38400 if UART6_BAUD_38400 - default 19200 if UART6_BAUD_19200 - default 9600 if UART6_BAUD_9600 # end of UART6 # Begin of UART7 @@ -1190,32 +1034,6 @@ config UART7_IRQ default 14 if UART7_IRQ14 default 15 if UART7_IRQ15 -choice - prompt "UART7 Baud rate" - default UART7_BAUD_115200 - depends on UART7_ENABLE - -config UART7_BAUD_115200 - bool "115200" -config UART7_BAUD_57600 - bool "57600" -config UART7_BAUD_38400 - bool "38400" -config UART7_BAUD_19200 - bool "19200" -config UART7_BAUD_9600 - bool "9600" - -endchoice - -config UART7_BAUD - int - depends on UART7_ENABLE - default 115200 if UART7_BAUD_115200 - default 57600 if UART7_BAUD_57600 - default 38400 if UART7_BAUD_38400 - default 19200 if UART7_BAUD_19200 - default 9600 if UART7_BAUD_9600 # end of UART7 # Begin of UART8 @@ -1302,32 +1120,6 @@ config UART8_IRQ default 14 if UART8_IRQ14 default 15 if UART8_IRQ15 -choice - prompt "UART8 Baud rate" - default UART8_BAUD_115200 - depends on UART8_ENABLE - -config UART8_BAUD_115200 - bool "115200" -config UART8_BAUD_57600 - bool "57600" -config UART8_BAUD_38400 - bool "38400" -config UART8_BAUD_19200 - bool "19200" -config UART8_BAUD_9600 - bool "9600" - -endchoice - -config UART8_BAUD - int - depends on UART8_ENABLE - default 115200 if UART8_BAUD_115200 - default 57600 if UART8_BAUD_57600 - default 38400 if UART8_BAUD_38400 - default 19200 if UART8_BAUD_19200 - default 9600 if UART8_BAUD_9600 # end of UART8 # Begin of UART9 @@ -1414,32 +1206,6 @@ config UART9_IRQ default 14 if UART9_IRQ14 default 15 if UART9_IRQ15 -choice - prompt "UART9 Baud rate" - default UART9_BAUD_115200 - depends on UART9_ENABLE - -config UART9_BAUD_115200 - bool "115200" -config UART9_BAUD_57600 - bool "57600" -config UART9_BAUD_38400 - bool "38400" -config UART9_BAUD_19200 - bool "19200" -config UART9_BAUD_9600 - bool "9600" - -endchoice - -config UART9_BAUD - int - depends on UART9_ENABLE - default 115200 if UART9_BAUD_115200 - default 57600 if UART9_BAUD_57600 - default 38400 if UART9_BAUD_38400 - default 19200 if UART9_BAUD_19200 - default 9600 if UART9_BAUD_9600 # end of UART9 # Begin of UART10 @@ -1526,32 +1292,6 @@ config UART10_IRQ default 14 if UART10_IRQ14 default 15 if UART10_IRQ15 -choice - prompt "UART10 Baud rate" - default UART10_BAUD_115200 - depends on UART10_ENABLE - -config UART10_BAUD_115200 - bool "115200" -config UART10_BAUD_57600 - bool "57600" -config UART10_BAUD_38400 - bool "38400" -config UART10_BAUD_19200 - bool "19200" -config UART10_BAUD_9600 - bool "9600" - -endchoice - -config UART10_BAUD - int - depends on UART10_ENABLE - default 115200 if UART10_BAUD_115200 - default 57600 if UART10_BAUD_57600 - default 38400 if UART10_BAUD_38400 - default 19200 if UART10_BAUD_19200 - default 9600 if UART10_BAUD_9600 # end of UART10 endmenu diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 146bed7..2a68e4e 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -18,7 +18,6 @@ */ #include <console/console.h> -#include <uart8250.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> @@ -387,8 +386,7 @@ static u32 make_uart_config(u16 base, u8 irq) #define SETUP_UART(n) \ uart_cfg = make_uart_config(CONFIG_UART##n##_IO, CONFIG_UART##n##_IRQ);\ - outl(uart_cfg, base + (n - 1) * 4);\ - uart8250_init(CONFIG_UART##n##_IO, 115200 / CONFIG_UART##n##_BAUD); + outl(uart_cfg, base + (n - 1) * 4); static void ex_sb_uart_init(struct device *dev) {

1 0

Patch set updated for coreboot: 9dc067d uart8250mem: Unify calls with generic UART
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5235 -gerrit commit 9dc067dc2f5c47e1384554312d8eb0d1426702f2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 10:19:23 2014 +0200 uart8250mem: Unify calls with generic UART Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romstage_console.c | 11 +----- src/console/uart8250mem_console.c | 30 ++++---------- src/drivers/oxford/oxpcie/oxpcie.c | 3 +- src/drivers/oxford/oxpcie/oxpcie_early.c | 48 +++++++++++++++++------ src/include/console/uart.h | 5 ++- src/include/uart8250.h | 50 ------------------------ src/lib/uart8250mem.c | 67 ++++++++++++++++---------------- 7 files changed, 86 insertions(+), 128 deletions(-) diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 89d7f82..6566b2f 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,20 +26,13 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250MEM -#include <uart8250.h> -#endif - void console_tx_byte(unsigned char byte) { if (byte == '\n') console_tx_byte('\r'); #if CONFIG_CONSOLE_SERIAL8250MEM - if (oxford_oxpcie_present) { - uart8250_mem_tx_byte( - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte); - } + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_byte(byte); @@ -61,7 +54,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { #if CONFIG_CONSOLE_SERIAL8250MEM - uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_SERIAL8250 uart_tx_flush(); diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c index 3833e47..7e52aed 100644 --- a/src/console/uart8250mem_console.c +++ b/src/console/uart8250mem_console.c @@ -18,47 +18,31 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> -static u32 uart_bar = 0; - -void uartmem_init(void) -{ - uart_bar = uart_mem_init(); -} - -u32 uartmem_getbaseaddr(void) +static void uartmem_init(void) { - return uart_bar; + uart_init(); } static void uartmem_tx_byte(unsigned char data) { - if (!uart_bar) - return; - - uart8250_mem_tx_byte(uart_bar, data); + uart_tx_byte(data); } static void uartmem_tx_flush(void) { - uart8250_mem_tx_flush(uart_bar); + uart_tx_flush(); } static unsigned char uartmem_rx_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_rx_byte(uart_bar); + return uart_rx_byte(); } static int uartmem_tst_byte(void) { - if (!uart_bar) - return 0; - - return uart8250_mem_can_rx_byte(uart_bar); + return uart_can_rx_byte(); } static const struct console_driver uart8250mem_console __console = { diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c index f719fc7..0b9081f 100644 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ b/src/drivers/oxford/oxpcie/oxpcie.c @@ -48,7 +48,8 @@ static void oxford_oxpcie_set_resources(struct device *dev) #if CONFIG_CONSOLE_SERIAL8250MEM /* Re-initialize OXPCIe base address after set_resources */ - uartmem_init(); + u32 mmio_base = pci_read_config32(device, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); #endif } diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 693c1e9..b2004c4 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -21,9 +21,13 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> -#include <uart8250.h> +#include <console/uart.h> #include <device/pci_def.h> +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; + #define PCIE_BRIDGE \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ @@ -35,13 +39,9 @@ #define OXPCIE_DEVICE_3 \ PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) -#if defined(__PRE_RAM__) -int oxford_oxpcie_present CAR_GLOBAL; - -void oxford_init(void) +static void oxpcie_init_bridge(void) { u16 reg16; - oxford_oxpcie_present = 1; /* First we reset the secondary bus */ reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); @@ -100,7 +100,6 @@ void oxford_init(void) break; default: /* No UART here. */ - oxford_oxpcie_present = 0; return; } @@ -113,16 +112,43 @@ void oxford_init(void) reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); - /* Now the UART initialization */ - u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; + car_set_var(oxpcie_present, 1); +} - unsigned div = uart_platform_divisor(); - uart8250_mem_init(uart0_base, div); +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); } +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} #endif +unsigned uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + unsigned uart_platform_divisor(void) { return uart_divisor(4000000); } + +uint32_t uartmem_getbaseaddr(void) +{ + return uart_platform_base(0); +} + +void oxford_init(void) +{ + oxpcie_init_bridge(); + uart_init(); +} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 6cd3beb..6b1d70b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -29,7 +29,10 @@ unsigned char uart_rx_byte(void); unsigned uart_divisor(unsigned basefreq); unsigned uart_platform_divisor(void); - +unsigned uart_platform_base(int idx); uint32_t uartmem_getbaseaddr(void); +void oxford_init(void); +void oxford_remap(u32 new_base): + #endif /* CONSOLE_UART_H */ diff --git a/src/include/uart8250.h b/src/include/uart8250.h deleted file mode 100644 index 4d7ebcc..0000000 --- a/src/include/uart8250.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef UART8250_H -#define UART8250_H - -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM - -#if ((115200 % CONFIG_TTYS0_BAUD) != 0) -#error Bad ttyS0 baud rate -#endif - -#if CONFIG_CONSOLE_SERIAL8250MEM -void uartmem_init(void); - -/* and the same for memory mapped uarts */ -unsigned char uart8250_mem_rx_byte(unsigned base_port); -int uart8250_mem_can_rx_byte(unsigned base_port); -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data); -void uart8250_mem_tx_flush(unsigned base_port); -void uart8250_mem_init(unsigned base_port, unsigned divisor); -u32 uart_mem_init(void); - -#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE -/* and special init for OXPCIe based cards */ -extern int oxford_oxpcie_present; -#endif -#endif - -#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */ - -#include <console/uart.h> - -#endif /* UART8250_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index cff67d7..3540c4b 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -19,8 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> -#include <device/device.h> +#include <console/uart.h> #include <delay.h> #include "drivers/uart/uart8250reg.h" @@ -52,23 +51,23 @@ static inline void uart8250_mem_wait_until_sent(unsigned base_port) udelay(1); } -void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) { uart8250_mem_wait_to_tx_byte(base_port); write8(base_port + UART_TBR, data); } -void uart8250_mem_tx_flush(unsigned base_port) +static void uart8250_mem_tx_flush(unsigned base_port) { uart8250_mem_wait_until_sent(base_port); } -int uart8250_mem_can_rx_byte(unsigned base_port) +static int uart8250_mem_can_rx_byte(unsigned base_port) { return read8(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_mem_rx_byte(unsigned base_port) +static unsigned char uart8250_mem_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base_port)) @@ -79,7 +78,7 @@ unsigned char uart8250_mem_rx_byte(unsigned base_port) return 0x0; } -void uart8250_mem_init(unsigned base_port, unsigned divisor) +static void uart8250_mem_init(unsigned base_port, unsigned divisor) { /* Disable interrupts */ write8(base_port + UART_IER, 0x0); @@ -100,35 +99,37 @@ void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -u32 uart_mem_init(void) -{ - u32 uart_bar = 0; - unsigned div = uart_platform_divisor(); - - /* Now find the UART base address and calculate the divisor */ -#if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) - device_t dev = dev_find_device(0x1415, 0xc158, NULL); - if (!dev) - dev = dev_find_device(0x1415, 0xc11b, NULL); - if (dev) { - struct resource *res = find_resource(dev, 0x10); +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; - if (res) { - uart_bar = res->base + 0x1000; // for 1st UART - // uart_bar = res->base + 0x2000; // for 2nd UART - } - } + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} - if (!uart_bar) -#endif - uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; // 1st UART - // uart_bar = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; // 2nd UART -#endif +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} - if (uart_bar) - uart8250_mem_init(uart_bar, div); +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} - return uart_bar; +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); }

1 0

Patch set updated for coreboot: d5bdf42 uart8250io: Unify calls with generic UART
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5234 -gerrit commit d5bdf42b5d416ae50c39f88f0239dbc01d1057c3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 15 07:53:18 2014 +0200 uart8250io: Unify calls with generic UART Change-Id: I6d56648e56f2177e1d5332497321e718df18300c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 8 +++----- src/arch/x86/lib/romstage_console.c | 6 +++--- src/console/uart8250_console.c | 10 +++++----- src/include/uart8250.h | 10 ---------- src/lib/uart8250.c | 31 ++++++++++++++++++++++++------- 5 files changed, 35 insertions(+), 30 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 0f0e017..5a88146 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <console/loglevel.h> #include <console/post_codes.h> +#include <console/uart.h> #include <console/ne2k.h> /* __PRE_RAM__ */ @@ -28,9 +29,6 @@ * we could use the same code on all architectures. */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 -#include <uart8250.h> -#endif #include <console/util.c> @@ -44,7 +42,7 @@ static void __console_tx_byte(unsigned char byte) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); @@ -65,7 +63,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4981f39..89d7f82 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,7 +26,7 @@ #include <console/spkmodem.h> #include <console/vtxprintf.h> -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL8250MEM #include <uart8250.h> #endif @@ -42,7 +42,7 @@ void console_tx_byte(unsigned char byte) } #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_byte(CONFIG_TTYS0_BASE, byte); + uart_tx_byte(byte); #endif #if CONFIG_USBDEBUG && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) usb_tx_byte(0, byte); @@ -64,7 +64,7 @@ void console_tx_flush(void) uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000); #endif #if CONFIG_CONSOLE_SERIAL8250 - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); diff --git a/src/console/uart8250_console.c b/src/console/uart8250_console.c index 196412c..52f59f6 100644 --- a/src/console/uart8250_console.c +++ b/src/console/uart8250_console.c @@ -18,7 +18,7 @@ */ #include <console/console.h> -#include <uart8250.h> +#include <console/uart.h> static void ttyS0_init(void) { @@ -27,22 +27,22 @@ static void ttyS0_init(void) static void ttyS0_tx_byte(unsigned char data) { - uart8250_tx_byte(CONFIG_TTYS0_BASE, data); + uart_tx_byte(data); } static void ttyS0_tx_flush(void) { - uart8250_tx_flush(CONFIG_TTYS0_BASE); + uart_tx_flush(); } static unsigned char ttyS0_rx_byte(void) { - return uart8250_rx_byte(CONFIG_TTYS0_BASE); + return uart_rx_byte(); } static int ttyS0_tst_byte(void) { - return uart8250_can_rx_byte(CONFIG_TTYS0_BASE); + return uart_can_rx_byte(); } static const struct console_driver uart8250_console __console = { diff --git a/src/include/uart8250.h b/src/include/uart8250.h index a214ce1..4d7ebcc 100644 --- a/src/include/uart8250.h +++ b/src/include/uart8250.h @@ -26,16 +26,6 @@ #error Bad ttyS0 baud rate #endif -#if CONFIG_CONSOLE_SERIAL8250 -unsigned char uart8250_rx_byte(unsigned base_port); -int uart8250_can_rx_byte(unsigned base_port); -void uart8250_tx_byte(unsigned base_port, unsigned char data); -void uart8250_tx_flush(unsigned base_port); -/* Yes it is silly to have three different uart init functions. But we used to - * have three different sets of uart code, so it's an improvement. - */ -void uart8250_init(unsigned base_port, unsigned divisor); -#endif #if CONFIG_CONSOLE_SERIAL8250MEM void uartmem_init(void); diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c index 4d2cb63..75caa06 100644 --- a/src/lib/uart8250.c +++ b/src/lib/uart8250.c @@ -19,7 +19,7 @@ */ #include <arch/io.h> -#include <uart8250.h> +#include <console/uart.h> #include <trace.h> #include "drivers/uart/uart8250reg.h" @@ -51,23 +51,23 @@ static inline void uart8250_wait_until_sent(unsigned base_port) while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); } -void uart8250_tx_byte(unsigned base_port, unsigned char data) +static void uart8250_tx_byte(unsigned base_port, unsigned char data) { uart8250_wait_to_tx_byte(base_port); outb(data, base_port + UART_TBR); } -void uart8250_tx_flush(unsigned base_port) +static void uart8250_tx_flush(unsigned base_port) { uart8250_wait_until_sent(base_port); } -int uart8250_can_rx_byte(unsigned base_port) +static int uart8250_can_rx_byte(unsigned base_port) { return inb(base_port + UART_LSR) & UART_LSR_DR; } -unsigned char uart8250_rx_byte(unsigned base_port) +static unsigned char uart8250_rx_byte(unsigned base_port) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while (i-- && !uart8250_can_rx_byte(base_port)); @@ -78,7 +78,7 @@ unsigned char uart8250_rx_byte(unsigned base_port) return 0x0; } -void uart8250_init(unsigned base_port, unsigned divisor) +static void uart8250_init(unsigned base_port, unsigned divisor) { DISABLE_TRACE; /* Disable interrupts */ @@ -101,8 +101,25 @@ void uart8250_init(unsigned base_port, unsigned divisor) ENABLE_TRACE; } +static const unsigned base = CONFIG_TTYS0_BASE; + void uart_init(void) { unsigned int div = uart_divisor(115200); - uart8250_init(CONFIG_TTYS0_BASE, div); + uart8250_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(base); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(base); }

1 0

Patch set updated for coreboot: fa7a741 OxPCIe uart: Split PCI bridge control
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237 -gerrit commit fa7a74163f434c3a67f5880c3f08ff9f669fad6b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 12:45:09 2014 +0200 OxPCIe uart: Split PCI bridge control None of the bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid but originate from lumpy and/or stumpy devices. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_early.c | 45 ++++++++++++++++++ src/drivers/Kconfig | 1 + src/drivers/oxford/oxpcie/Kconfig | 64 ++----------------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 81 ++++++-------------------------- src/drivers/pci/Kconfig | 31 ++++++++++++ src/drivers/pci/pci_early.c | 58 +++++++++++++++++++++++ src/include/device/pci.h | 6 +++ src/southbridge/intel/bd82x6x/Kconfig | 20 ++++++++ 8 files changed, 179 insertions(+), 127 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index c15a4d0..d7c48de 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2011 Google Inc + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -66,3 +68,46 @@ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } + +void pci_bridge_reset_secondary(device_t p2p_bridge) +{ + u16 reg16; + /* Disable all access through bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + + /* First we reset the secondary bus. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +{ + /* Disable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + /* Enable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); +} + +void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base) +{ + /* MMIO window behind the bridge. */ + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + ((base & 0xffff0000) | ((base >> 16) & 0xff00))); + + /* Enable memory access through bridge */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); +} diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 01bed21..5d9a801 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -32,6 +32,7 @@ source src/drivers/parade/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig endif +source src/drivers/pci/Kconfig source src/drivers/realtek/Kconfig source src/drivers/sil/Kconfig source src/drivers/spi/Kconfig diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 899a153..bd5001c 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,68 +1,10 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n + depends on PCI select HAVE_UART_MEMORY_MAPPED + select EARLY_PCI_BRIDGE help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 will work. - NOTE: Right now you have to set the base address of your OXPCIe952 - card to exactly the value that the device allocator would set them - later on, or serial console functionality will stop as soon as the - resource allocator assigns a new base address to the device. - -config OXFORD_OXPCIE_BRIDGE_BUS - hex "OXPCIe's PCIe bridge bus number" - default 0x0 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_DEVICE - hex "OXPCIe's PCIe bridge device number" - default 0x1c - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_FUNCTION - hex "OXPCIe's PCIe bridge function number" - default 0x2 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_SUBORDINATE - hex "OXPCIe's PCIe bridge subordinate bus" - default 0x3 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BASE_ADDRESS - hex "Base address for rom stage console" - default 0xe0400000 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up a temporary address - for the OXPCIe952 controller. - + 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index b2004c4..122f3a4 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -25,94 +25,43 @@ #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; -#define PCIE_BRIDGE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) - -#define OXPCIE_DEVICE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) - -#define OXPCIE_DEVICE_3 \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) - -static void oxpcie_init_bridge(void) +static int oxpcie_probe(u8 bus, u8 dev, u32 mmio_base, u16 io_base) { - u16 reg16; - - /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ - - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Set up subordinate bus number */ - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); + pci_devfn_t device = PCI_DEV(bus, dev, 0); - /* Memory window for the OXPCIe952 card */ - // XXX is the calculation of base and limit correct? - pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); - - /* Enable memory access through bridge */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - - u32 timeout = 20000; // Timeout in 10s of microseconds. - u32 id = 0; - for (;;) { - id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); - if (!timeout-- || (id != 0 && id != 0xffffffff)) - break; - udelay(10); - } - - u32 device = OXPCIE_DEVICE; /* unknown default */ + u32 id = pci_read_config32(device, PCI_VENDOR_ID); switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI */ + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and * function 3 is the serial port. So let's go look for * the UART. */ - id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; - device = OXPCIE_DEVICE_3; + return -1; break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ case 0xc1581415: /* e.g. Startech MPEX2S952 */ - device = OXPCIE_DEVICE; break; default: /* No UART here. */ - return; + return -1; } /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); + return 0; } static int oxpcie_uart_active(void) @@ -149,6 +98,6 @@ uint32_t uartmem_getbaseaddr(void) void oxford_init(void) { - oxpcie_init_bridge(); + pci_bridge_early_init(&oxpcie_probe); uart_init(); } diff --git a/src/drivers/pci/Kconfig b/src/drivers/pci/Kconfig new file mode 100644 index 0000000..bb6d2bf --- /dev/null +++ b/src/drivers/pci/Kconfig @@ -0,0 +1,31 @@ +config EARLY_PCI_BRIDGE + bool "Early PCI bridge" + depends on PCI + default n + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. + + This option enables static configuration for a single pre-defined + PCI bridge function on bus 0. + +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex "bridge device" + default 0x0 + +config EARLY_PCI_BRIDGE_FUNCTION + hex "bridge function" + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex "MMIO window base" + default 0x0 + +config EARLY_PCI_BRIDGE_SECONDARY + hex "Early PCI bridge secondary bus" + default 0x0 + +endif # EARLY_PCI_BRIDGE diff --git a/src/drivers/pci/pci_early.c b/src/drivers/pci/pci_early.c new file mode 100644 index 0000000..6e1a6f7 --- /dev/null +++ b/src/drivers/pci/pci_early.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_def.h> + + +{ + /* No PCI-to-PCI bridges are enabled yet, so the one we try to + * configure must have its primary on bus 0. + */ + pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + u8 bus = CONFIG_EARLY_PCI_BRIDGE_SECONDARY; + + pci_bridge_reset_secondary(p2p_bridge); + pci_bridge_set_secondary(p2p_bridge, bus); + + u3 timeout = 20000; // Timeout in 10s of microseconds. + u32 id = 0; + for (;;) { + id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); + if (!timeout-- || (id != 0 && id != 0xffffffff)) + break; + udelay(10); + } + + ret = probe(bus, dev, mmio_base, io_base); + + /* Enable both MMIO and IO window with static allocation + * if we found any suitable device behind bridge. + */ + pci_bridge_enable_mmio(p2p_bridge, base, limit); + + /* Resource allocator will reconfigure bridges and secondary bus + * number may change. Early device must not use config transactions + * from here on. + */ + pci_bridge_set_secondary(p2p_bridge, 0); +} diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 29d988f..881c2ac 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -98,6 +98,12 @@ static inline const struct pci_operations *ops_pci(device_t dev) return pops; } +#else + +void pci_bridge_reset_secondary(device_t p2p_bridge); +void pci_bridge_enable_mmio(device_t p2p_bridge, u32 base); +void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary); + #endif /* ! __SIMPLE_DEVICE__ */ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 9cfa5d5..69c1fc9 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,6 +41,26 @@ config EHCI_BAR hex default 0xfef00000 +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + default 0xe0400000 + +config EARLY_PCI_BRIDGE_SECONDARY + hex + default 0x3 + +endif + config DRAM_RESET_GATE_GPIO int default 60

1 0

Patch set updated for coreboot: 05a06ec uart8250: Move under drivers/uart
by Kyösti Mälkki 16 Feb '14

16 Feb '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5236 -gerrit commit 05a06ec9edaa575d09ff2105576721e6cbd0fc9e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 30 15:45:16 2014 +0200 uart8250: Move under drivers/uart Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 2 +- src/drivers/uart/Makefile.inc | 12 ++++ src/drivers/uart/uart8250io.c | 125 ++++++++++++++++++++++++++++++++++++ src/drivers/uart/uart8250mem.c | 135 +++++++++++++++++++++++++++++++++++++++ src/lib/Makefile.inc | 4 -- src/lib/uart8250.c | 125 ------------------------------------ src/lib/uart8250mem.c | 135 --------------------------------------- 7 files changed, 273 insertions(+), 265 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 5a88146..5b88a98 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -33,7 +33,7 @@ #include <console/util.c> #if CONFIG_CONSOLE_SERIAL8250 -#include "lib/uart8250.c" +#include "drivers/uart/uart8250io.c" #endif #if CONFIG_CONSOLE_NE2K #include "drivers/net/ne2k.c" diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 9a8121e..aec6a58 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,3 +1,15 @@ +ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +romstage-y += uart8250io.c +ramstage-y += uart8250io.c +smm-$(CONFIG_DEBUG_SMI) += uart8250io.c +endif + +ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +romstage-y += uart8250mem.c +ramstage-y += uart8250mem.c +smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c +endif + ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) ifeq ($(CONFIG_DRIVERS_UART_PL011),y) diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c new file mode 100644 index 0000000..ecd77b7 --- /dev/null +++ b/src/drivers/uart/uart8250io.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <trace.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + * + * Estimated that inb() from UART takes 1 microsecond. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static inline int uart8250_can_tx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_THRE; +} + +static inline void uart8250_wait_to_tx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_tx_byte(base_port)); +} + +static inline void uart8250_wait_until_sent(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); +} + +static void uart8250_tx_byte(unsigned base_port, unsigned char data) +{ + uart8250_wait_to_tx_byte(base_port); + outb(data, base_port + UART_TBR); +} + +static void uart8250_tx_flush(unsigned base_port) +{ + uart8250_wait_until_sent(base_port); +} + +static int uart8250_can_rx_byte(unsigned base_port) +{ + return inb(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while (i-- && !uart8250_can_rx_byte(base_port)); + + if (i) + return inb(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_init(unsigned base_port, unsigned divisor) +{ + DISABLE_TRACE; + /* Disable interrupts */ + outb(0x0, base_port + UART_IER); + /* Enable FIFOs */ + outb(UART_FCR_FIFO_EN, base_port + UART_FCR); + + /* assert DTR and RTS so the other end is happy */ + outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); + + /* DLAB on */ + outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + outb(divisor & 0xFF, base_port + UART_DLL); + outb((divisor >> 8) & 0xFF, base_port + UART_DLM); + + /* Set to 3 for 8N1 */ + outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); + ENABLE_TRACE; +} + +static const unsigned base = CONFIG_TTYS0_BASE; + +void uart_init(void) +{ + unsigned int div = uart_divisor(115200); + uart8250_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + uart8250_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + return uart8250_rx_byte(base); +} + +void uart_tx_flush(void) +{ + uart8250_tx_flush(base); +} diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c new file mode 100644 index 0000000..210b9a8 --- /dev/null +++ b/src/drivers/uart/uart8250mem.c @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/uart.h> +#include <delay.h> +#include "uart8250reg.h" + +/* Should support 8250, 16450, 16550, 16550A type UARTs */ + +/* Expected character delay at 1200bps is 9ms for a working UART + * and no flow-control. Assume UART as stuck if shift register + * or FIFO takes more than 50ms per character to appear empty. + */ +#define SINGLE_CHAR_TIMEOUT (50 * 1000) +#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) + +static inline int uart8250_mem_can_tx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_THRE; +} + +static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_tx_byte(base_port)) + udelay(1); +} + +static inline void uart8250_mem_wait_until_sent(unsigned base_port) +{ + unsigned long int i = FIFO_TIMEOUT; + while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) + udelay(1); +} + +static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) +{ + uart8250_mem_wait_to_tx_byte(base_port); + write8(base_port + UART_TBR, data); +} + +static void uart8250_mem_tx_flush(unsigned base_port) +{ + uart8250_mem_wait_until_sent(base_port); +} + +static int uart8250_mem_can_rx_byte(unsigned base_port) +{ + return read8(base_port + UART_LSR) & UART_LSR_DR; +} + +static unsigned char uart8250_mem_rx_byte(unsigned base_port) +{ + unsigned long int i = SINGLE_CHAR_TIMEOUT; + while(i-- && !uart8250_mem_can_rx_byte(base_port)) + udelay(1); + if (i) + return read8(base_port + UART_RBR); + else + return 0x0; +} + +static void uart8250_mem_init(unsigned base_port, unsigned divisor) +{ + /* Disable interrupts */ + write8(base_port + UART_IER, 0x0); + /* Enable FIFOs */ + write8(base_port + UART_FCR, UART_FCR_FIFO_EN); + + /* Assert DTR and RTS so the other end is happy */ + write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); + + /* DLAB on */ + write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); + + /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ + write8(base_port + UART_DLL, divisor & 0xFF); + write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); + + /* Set to 3 for 8N1 */ + write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); +} + + +void uart_init(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + + unsigned div = uart_platform_divisor(); + uart8250_mem_init(base, div); +} + +void uart_tx_byte(unsigned char data) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_byte(base, data); +} + +unsigned char uart_rx_byte(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return 0xff; + return uart8250_mem_rx_byte(base); +} + +void uart_tx_flush(void) +{ + u32 base = uart_platform_base(0); + if (!base) + return; + uart8250_mem_tx_flush(base); +} diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 076bdd7..941c0ba 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -45,8 +45,6 @@ romstage-y += cbfs.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c #romstage-y += lzmadecode.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c -romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ifeq ($(CONFIG_EARLY_CBMEM_INIT),y) romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -86,8 +84,6 @@ ramstage-y += stack.c ramstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += clog2.c romstage-y += clog2.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c -ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c deleted file mode 100644 index 75caa06..0000000 --- a/src/lib/uart8250.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <trace.h> -#include "drivers/uart/uart8250reg.h" - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - * - * Estimated that inb() from UART takes 1 microsecond. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static inline int uart8250_can_tx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_THRE; -} - -static inline void uart8250_wait_to_tx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_tx_byte(base_port)); -} - -static inline void uart8250_wait_until_sent(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT)); -} - -static void uart8250_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_wait_to_tx_byte(base_port); - outb(data, base_port + UART_TBR); -} - -static void uart8250_tx_flush(unsigned base_port) -{ - uart8250_wait_until_sent(base_port); -} - -static int uart8250_can_rx_byte(unsigned base_port) -{ - return inb(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while (i-- && !uart8250_can_rx_byte(base_port)); - - if (i) - return inb(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_init(unsigned base_port, unsigned divisor) -{ - DISABLE_TRACE; - /* Disable interrupts */ - outb(0x0, base_port + UART_IER); - /* Enable FIFOs */ - outb(UART_FCR_FIFO_EN, base_port + UART_FCR); - - /* assert DTR and RTS so the other end is happy */ - outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR); - - /* DLAB on */ - outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - outb(divisor & 0xFF, base_port + UART_DLL); - outb((divisor >> 8) & 0xFF, base_port + UART_DLM); - - /* Set to 3 for 8N1 */ - outb(CONFIG_TTYS0_LCS, base_port + UART_LCR); - ENABLE_TRACE; -} - -static const unsigned base = CONFIG_TTYS0_BASE; - -void uart_init(void) -{ - unsigned int div = uart_divisor(115200); - uart8250_init(base, div); -} - -void uart_tx_byte(unsigned char data) -{ - uart8250_tx_byte(base, data); -} - -unsigned char uart_rx_byte(void) -{ - return uart8250_rx_byte(base); -} - -void uart_tx_flush(void) -{ - uart8250_tx_flush(base); -} diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c deleted file mode 100644 index 3540c4b..0000000 --- a/src/lib/uart8250mem.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2003 Eric Biederman - * Copyright (C) 2006-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <console/uart.h> -#include <delay.h> -#include "drivers/uart/uart8250reg.h" - -/* Should support 8250, 16450, 16550, 16550A type UARTs */ - -/* Expected character delay at 1200bps is 9ms for a working UART - * and no flow-control. Assume UART as stuck if shift register - * or FIFO takes more than 50ms per character to appear empty. - */ -#define SINGLE_CHAR_TIMEOUT (50 * 1000) -#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) - -static inline int uart8250_mem_can_tx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_THRE; -} - -static inline void uart8250_mem_wait_to_tx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_tx_byte(base_port)) - udelay(1); -} - -static inline void uart8250_mem_wait_until_sent(unsigned base_port) -{ - unsigned long int i = FIFO_TIMEOUT; - while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT)) - udelay(1); -} - -static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data) -{ - uart8250_mem_wait_to_tx_byte(base_port); - write8(base_port + UART_TBR, data); -} - -static void uart8250_mem_tx_flush(unsigned base_port) -{ - uart8250_mem_wait_until_sent(base_port); -} - -static int uart8250_mem_can_rx_byte(unsigned base_port) -{ - return read8(base_port + UART_LSR) & UART_LSR_DR; -} - -static unsigned char uart8250_mem_rx_byte(unsigned base_port) -{ - unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_rx_byte(base_port)) - udelay(1); - if (i) - return read8(base_port + UART_RBR); - else - return 0x0; -} - -static void uart8250_mem_init(unsigned base_port, unsigned divisor) -{ - /* Disable interrupts */ - write8(base_port + UART_IER, 0x0); - /* Enable FIFOs */ - write8(base_port + UART_FCR, UART_FCR_FIFO_EN); - - /* Assert DTR and RTS so the other end is happy */ - write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS); - - /* DLAB on */ - write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS); - - /* Set Baud Rate Divisor. 12 ==> 9600 Baud */ - write8(base_port + UART_DLL, divisor & 0xFF); - write8(base_port + UART_DLM, (divisor >> 8) & 0xFF); - - /* Set to 3 for 8N1 */ - write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); -} - - -void uart_init(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - - unsigned div = uart_platform_divisor(); - uart8250_mem_init(base, div); -} - -void uart_tx_byte(unsigned char data) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_byte(base, data); -} - -unsigned char uart_rx_byte(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return 0xff; - return uart8250_mem_rx_byte(base); -} - -void uart_tx_flush(void) -{ - u32 base = uart_platform_base(0); - if (!base) - return; - uart8250_mem_tx_flush(base); -}

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Patch merged into coreboot/master: f9158a5 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support.
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit f9158a5832e5d105003b7b6b1e829f0d74e68a7f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jan 25 21:46:10 2014 +1100 Jetway NF81-T56N-LF [2/2]: actually implement mainboard support. Step 2: change the Persimmon code to adapt it to the new board's hardware. The NF81-T56N-LF is a IPC form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) APU - 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V) - VGA and LVDS (via Analogix ANX3110) - AMD A55E (Hudson-E1) southbridge - 6x USB 2.0/1.1 ports - 5x SATA3 6Gb/s, 1x mSATA socket - 6-Channel HD Audio (via VIA VT1705) - PCI and ISA (via ITE IT8888)?? - NEC uPD78F0532 microcontroller on I2C ("SEMA")?? - 2x RJ45 GbE (via Realtek RTL8111E x2) - Fintek F71869AD Super I/O - PS/2 KB/MS port - RS232 header (via Unisonic UTC 75232 RS232 driver/receiver) - GPIO header - CIR header - 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS) Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway *lies* claiming the SPI flash is 16MB. They also use red pen over the chip so you wont see this deceit. Change-Id: I03ccc58bc782e800aeef0d19679ce060277b0c04 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/4801 for details. -gerrit

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Patch merged into coreboot/master: 5630d3f Jetway NF81-T56N-LF [1/2]: create board by forking AMD Persimmon
by gerrit＠coreboot.org 16 Feb '14

16 Feb '14

the following patch was just integrated into master: commit 5630d3f86d6cc7c682fa8f996b62e111099f8ca7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jan 25 07:40:39 2014 +1100 Jetway NF81-T56N-LF [1/2]: create board by forking AMD Persimmon Step 1: copy all files unmodified from Persimmon. This makes it much easier later to see how the two boards actually and deliberately differ when porting bugfixes from one to the other. Change-Id: I23e223049ed1c69e320e6b31efe4266bfeb97207 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/4800 for details. -gerrit

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coreboot-gerrit February 2014