coreboot-gerrit February 2014

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Patch set updated for coreboot: bbcb95e NOTFORMERGE: x60gfx: step 9
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit bbcb95e1900b3ba73022b24caa4966c70910ce70 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 9 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 20 +- src/drivers/intel/gma/i915_reg.h | 5 + src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/i915.c | 485 ++++++--- src/mainboard/lenovo/x60/i915io.c | 2020 +------------------------------------ src/northbridge/intel/i945/gma.c | 6 +- 6 files changed, 381 insertions(+), 2156 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..15affd3 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -32,7 +32,7 @@ wait_rdy(u32 mmio) unsigned try = 100; while (try--) { - if (read32(mmio + PCH_GMBUS2) & (1 << 11)) + if (read32(mmio + GMBUS2) & (1 << 11)) return; udelay(10); } @@ -45,29 +45,29 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) wait_rdy(mmio); /* 100 KHz, hold 0ns, */ - write32(mmio + PCH_GMBUS0, bus); + write32(mmio + GMBUS0, bus); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + write32(mmio + GMBUS5, 0); + write32(mmio + GMBUS1, 0x46000000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + write32(mmio + GMBUS5, 0); + write32(mmio + GMBUS1, 0x4a800001 | (slave << 1)); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); - reg32 = read32(mmio + PCH_GMBUS3); + reg32 = read32(mmio + GMBUS3); edid[4 * i] = reg32 & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff; } wait_rdy(mmio); - write32(mmio + PCH_GMBUS1, 0x4a800000 | (slave << 1)); + write32(mmio + GMBUS1, 0x4a800000 | (slave << 1)); wait_rdy(mmio); - write32(mmio + PCH_GMBUS0, 0x48000000); - write32(mmio + PCH_GMBUS2, 0x00008000); + write32(mmio + GMBUS0, 0x48000000); + write32(mmio + GMBUS2, 0x00008000); printk (BIOS_INFO, "EDID:\n"); for (i = 0; i < 128; i++) { diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8c08d9f..9f134d0 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -959,6 +959,11 @@ #define DVOC_ON (1<<31) #define LVDS 0x61180 #define LVDS_ON (1<<31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) /* Scratch pad debug 0 reg: */ diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..821f7a8 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -43,6 +43,17 @@ #include <cpu/x86/msr.h> #include <edid.h> #include "i915io.h" +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915_reg.h> + +#define LVDS_DETECTED (1 << 1) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ enum { vmsg = 1, vio = 2, vspin = 4, @@ -62,18 +73,6 @@ static unsigned int physbase; #define PGETBL_ENABLED 0x00000001 -static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; #define READ32(addr) io_i915_READ32(addr) #define WRITE32(val, addr) io_i915_WRITE32(val, addr) @@ -174,114 +173,24 @@ static unsigned long globalmicroseconds(void) return microseconds(globalstart, rdtscll()); } -extern struct iodef iodefs[]; -extern int niodefs; - -/* fill the palette. This runs when the P opcode is hit. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for (i = 0; i < 256; i++, color += 0x010101) - io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = 0; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for (i = index, id = &iodefs[i]; id->op; i++, id++) { - switch (id->op) { - case M: - if (verbose & vmsg) - printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr) { - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++) - u = READ32(id->addr); - - if (verbose & vspin) - printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL) { - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: - break; - case 7: - break; - default: - udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", - 100000); - } - } - break; - case V: - if (id->count < 8) { - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", - id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, unsigned int gfx); int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; - - int index; + struct edid edid; + u8 x60_edid_data[256]; unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + mmio = (void *)pmmio; addrport = piobase; dataport = addrport + 4; @@ -292,34 +201,340 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, (void *)graphics, mmio, addrport, physbase); globalstart = rdtscll(); - - decode_edid((unsigned char *)&x60_edid_data, + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); - htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (edid.ha + edid.hso - 1) | - ((edid.ha + edid.hso + edid.hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + +#define IS_DUAL_CHANNEL 0 +#define USE_SSC 1 + + read32(pmmio+PP_ON_DELAYS); // 0x00000000 + read32(pmmio+PP_OFF_DELAYS); // 0x00000000 + write32(pmmio+PP_ON_DELAYS,0x00000000); + write32(pmmio+PP_OFF_DELAYS,0x00000000); + write32(pmmio+INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800); + write32(pmmio+RENDER_RING_BASE,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x4,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x8,0x00000000); + write32(pmmio+RENDER_RING_BASE+0xc,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x10,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x14,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x18,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x1c,0x00000000); + write32(pmmio+FENCE_REG_965_0,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x4,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x8,0x00000000); + write32(pmmio+FENCE_REG_965_0+0xc,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x10,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x14,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x18,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x1c,0x00000000); + write32(pmmio+VGACNTRL, VGA_DISP_DISABLE | 0x80000000); + read32(pmmio+PFIT_CONTROL); // 0x00000000 + read32(pmmio+PP_CONTROL); // 0x00000000 + write32(pmmio+PP_CONTROL,0xabcd0000); + read32(pmmio+BLC_PWM_CTL); // 0x00000000 + read32(pmmio+DVOB); // 0x00300000 + read32(pmmio+DVOC); // 0x00300000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+TV_DAC); // 0x00000000 + write32(pmmio+TV_DAC,0x08000000); + read32(pmmio+TV_DAC); // 0x08000000 + write32(pmmio+TV_DAC,0x00000000); + read32(pmmio+TV_DAC); // 0x00000000 + write32(pmmio+TV_DAC,0x00000000); + write32(pmmio+HWS_PGA,0x352d2000); + write32(pmmio+PRB0_CTL,0x00000000); + write32(pmmio+PRB0_HEAD,0x00000000); + write32(pmmio+PRB0_TAIL,0x00000000); + read32(pmmio+PRB0_HEAD); // 0x00000000 + write32(pmmio+PRB0_START,0x00000000); + write32(pmmio+PRB0_CTL,0x0001f001); + read32(pmmio+PRB0_CTL); // 0x0001f001 + read32(pmmio+PRB0_START); // 0x00000000 + read32(pmmio+PRB0_HEAD); // 0x00000000 + read32(pmmio+PRB0_TAIL); // 0x00000000 + read32(pmmio+0x6104); // 0x00000000 + write32(pmmio+0x6104,0x0000000b); + write32(pmmio+ECOSKPD,0x00010000); + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+_DSPACNTR); // 0x00000000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + write32(pmmio+_PIPEBCONF,0x00000000); + read32(pmmio+_DSPBCNTR); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_EN,0x00000000); + read32(pmmio+PORT_HOTPLUG_STAT); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_STAT,0x00000000); + write32(pmmio+HWSTAM,0x0000effe); + write32(pmmio+_PIPEASTAT,0x00000000); + write32(pmmio+_PIPEBSTAT,0x00000000); + read32(pmmio+PORT_HOTPLUG_EN); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220); + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220 + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228); + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228 + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220 + read32(pmmio+PORT_HOTPLUG_STAT); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800); + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220); + write32(pmmio+_DSPBSIZE,0x03ff04ff); + write32(pmmio+_DSPBPOS,0x00000000); + write32(pmmio+_PIPEACONF,0x00000000); + write32(pmmio+_DSPBCNTR,0x40000000); + read32(pmmio+_DSPBCNTR); // 0x40000000 + write32(pmmio+_DSPBCNTR,0x58000000); + write32(pmmio+_DSPBADDR,0x00020000); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + read32(pmmio+TV_CTL); // 0x00000000 + write32(pmmio+TV_H_CTL_1,0x00400359); + write32(pmmio+TV_H_CTL_2,0x80480022); + write32(pmmio+TV_H_CTL_3,0x007c0344); + write32(pmmio+TV_V_CTL_1,0x00f01415); + write32(pmmio+TV_V_CTL_2,0x00060607); + write32(pmmio+TV_V_CTL_3,0x80120001); + write32(pmmio+TV_V_CTL_4,0x000900f0); + write32(pmmio+TV_V_CTL_5,0x000a00f0); + write32(pmmio+TV_V_CTL_6,0x000900f0); + write32(pmmio+TV_V_CTL_7,0x000a00f0); + write32(pmmio+TV_SC_CTL_1,0xc1710087); + write32(pmmio+TV_SC_CTL_2,0x6b405140); + write32(pmmio+TV_SC_CTL_3,0x00000000); + write32(pmmio+TV_CSC_Y,0x0332012d); + write32(pmmio+TV_CSC_Y2,0x07d30104); + write32(pmmio+TV_CSC_U,0x0733052d); + write32(pmmio+TV_CSC_U2,0x05c70200); + write32(pmmio+TV_CSC_V,0x0340030c); + write32(pmmio+TV_CSC_V2,0x06d00200); + write32(pmmio+TV_CLR_KNOBS,0x00606000); + write32(pmmio+TV_CLR_LEVEL,0x010b00e1); + write32(pmmio+_PFA_CTL_1,0x00000000); + write32(pmmio+_PFA_WIN_POS,0x00000000); + write32(pmmio+_PFA_WIN_SZ,0x00000000); + read32(pmmio+TV_DAC); // 0x70000000 + write32(pmmio+TV_DAC,0x00000000); + write32(pmmio+TV_CTL,0x000c0000); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC_SELF,0x0001002f); + write32(pmmio+FW_BLC,0x0101011a); + write32(pmmio+FW_BLC2,0x00000102); + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000); + read32(pmmio+PP_CONTROL); // 0xabcd0000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_DSPBCNTR); // 0x58000000 + write32(pmmio+_DSPBCNTR,0xd8000000); + read32(pmmio+_DSPBADDR); // 0x00020000 + write32(pmmio+_DSPBADDR,0x00020000); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_CTL); // 0x000c0000 + write32(pmmio+TV_CTL,0x800c0000); + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x800c0000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x800c0000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_DAC); // 0x70000000 + read32(pmmio+TV_CTL); // 0x800c0000 + write32(pmmio+TV_CTL,0x000c0007); + write32(pmmio+TV_DAC,0x0f0000aa); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_DAC); // 0x7f0000aa + write32(pmmio+TV_DAC,0x70000000); + write32(pmmio+TV_CTL,0x800c0000); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_CTL); // 0x800c0000 + write32(pmmio+TV_CTL,0x000c0000); + write32(pmmio+INSTPM,0x08000800); + read32(pmmio+_DSPBCNTR); // 0xd8000000 + write32(pmmio+_DSPBCNTR,0x58000000); + read32(pmmio+_DSPBADDR); // 0x00020000 + write32(pmmio+_DSPBADDR,0x00020000); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+_DSPACNTR); // 0x00000000 + read32(pmmio+_DSPBCNTR); // 0x58000000 + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x000c0000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x000c0000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + write32(pmmio+_DPLL_B, DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x18046000); + read32(pmmio+LVDS); // 0x40000000 + write32(pmmio+LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300); + write32(pmmio+_DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000); + read32(pmmio+_PIPEBCONF); // 0x00000000 + write32(pmmio+_HTOTAL_B,0x053f03ff); + write32(pmmio+_HBLANK_B,0x053f03ff); + write32(pmmio+_HSYNC_B,0x049f0417); + write32(pmmio+_VTOTAL_B,0x032502ff); + write32(pmmio+_VBLANK_B,0x032502ff); + write32(pmmio+_VSYNC_B,0x03080302); + write32(pmmio+_PIPEBSRC,0x03ff02ff); + write32(pmmio+_DSPASIZE,0x02ff03ff); + write32(pmmio+_DSPASTRIDE+0x4,0x00000000); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC_SELF,0x0001003f); + write32(pmmio+FW_BLC,0x011d0109); + write32(pmmio+FW_BLC2,0x00000102); + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000); + write32(pmmio+PFIT_PGM_RATIOS,0x00000000); + write32(pmmio+PFIT_CONTROL,(PFIT_PIPE_SHIFT & 0x8) | 0x00000008); + read32(pmmio+BLC_PWM_CTL); // 0x00000000 + write32(pmmio+BLC_PWM_CTL,0x00000002); + + target_frequency = IS_DUAL_CHANNEL ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } - vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } - vsync = (edid.va + edid.vso - 1) | - ((edid.va + edid.vso + edid.vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (IS_DUAL_CHANNEL ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((USE_SSC ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (IS_DUAL_CHANNEL ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((USE_SSC ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0x20000); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), (1 << 31)); + write32(pmmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (IS_DUAL_CHANNEL ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL | (1 << 30)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); - printk(BIOS_SPEW, "Table has %d elements\n", niodefs); + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff); verbose = 0; /* GTT is the Global Translation Table for the graphics pipeline. diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c index 3552867..def8b57 100644 --- a/src/mainboard/lenovo/x60/i915io.c +++ b/src/mainboard/lenovo/x60/i915io.c @@ -61,84 +61,6 @@ struct iodef iodefs[] = { {M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0}, {W, 1, "", VGACNTRL, VGA_DISP_DISABLE | 0x80000000, 0}, {R, 1, "", PFIT_CONTROL, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 1, "", 0x5108, 0x00004a00, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x468000a1, 0}, -{R, 1, "", 0x5108, 0x00008a08, 0}, -{R, 1, "", 0x510c, 0xffffff00, 0}, -{R, 1, "", 0x5108, 0x00008a0c, 0}, -{R, 1, "", 0x510c, 0x00ffffff, 0}, -{R, 1, "", 0x5108, 0x00008a10, 0}, -{R, 1, "", 0x510c, 0x4000ae30, 0}, -{R, 1, "", 0x5108, 0x00008a14, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x00008a18, 0}, -{R, 1, "", 0x510c, 0x03010f00, 0}, -{R, 1, "", 0x5108, 0x00008a1c, 0}, -{R, 1, "", 0x510c, 0x78121980, 0}, -{R, 1, "", 0x5108, 0x00008a20, 0}, -{R, 1, "", 0x510c, 0x9175edea, 0}, -{R, 1, "", 0x5108, 0x00008a24, 0}, -{R, 1, "", 0x510c, 0x268b4f57, 0}, -{R, 1, "", 0x5108, 0x00008a28, 0}, -{R, 1, "", 0x510c, 0x21545021, 0}, -{R, 1, "", 0x5108, 0x00008a2c, 0}, -{R, 1, "", 0x510c, 0x01010008, 0}, -{R, 1, "", 0x5108, 0x00008a30, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a34, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a38, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a3c, 0}, -{R, 1, "", 0x510c, 0x15280101, 0}, -{R, 1, "", 0x5108, 0x00008a40, 0}, -{R, 1, "", 0x510c, 0x00414000, 0}, -{R, 1, "", 0x5108, 0x00008a44, 0}, -{R, 1, "", 0x510c, 0x88183026, 0}, -{R, 1, "", 0x5108, 0x00008a48, 0}, -{R, 1, "", 0x510c, 0xb9f60036, 0}, -{R, 1, "", 0x5108, 0x00008a4c, 0}, -{R, 1, "", 0x510c, 0x18000000, 0}, -{R, 1, "", 0x5108, 0x00008a50, 0}, -{R, 1, "", 0x510c, 0x400010ed, 0}, -{R, 1, "", 0x5108, 0x00008a54, 0}, -{R, 1, "", 0x510c, 0x30260041, 0}, -{R, 1, "", 0x5108, 0x00008a58, 0}, -{R, 1, "", 0x510c, 0x00368818, 0}, -{R, 1, "", 0x5108, 0x00008a5c, 0}, -{R, 1, "", 0x510c, 0x0000b9f6, 0}, -{R, 1, "", 0x5108, 0x00008a60, 0}, -{R, 1, "", 0x510c, 0x00001800, 0}, -{R, 1, "", 0x5108, 0x00008a64, 0}, -{R, 1, "", 0x510c, 0x61000f00, 0}, -{R, 1, "", 0x5108, 0x00008a68, 0}, -{R, 1, "", 0x510c, 0x43613243, 0}, -{R, 1, "", 0x5108, 0x00008a6c, 0}, -{R, 1, "", 0x510c, 0x00010f28, 0}, -{R, 1, "", 0x5108, 0x00008a70, 0}, -{R, 1, "", 0x510c, 0x4a58a34c, 0}, -{R, 1, "", 0x5108, 0x00008a74, 0}, -{R, 1, "", 0x510c, 0xfe000000, 0}, -{R, 1, "", 0x5108, 0x00008a78, 0}, -{R, 1, "", 0x510c, 0x4e544c00, 0}, -{R, 1, "", 0x5108, 0x00008a7c, 0}, -{R, 1, "", 0x510c, 0x58313231, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x304c2d4a, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x00000a37, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, {R, 1, "", PP_CONTROL, 0x00000000, 0}, {W, 1, "", PP_CONTROL, 0xabcd0000, 0}, {R, 2, "", BLC_PWM_CTL, 0x00000000, 0}, @@ -168,7 +90,6 @@ struct iodef iodefs[] = { {W, 1, "", 0x6104, 0x0000000b, 0}, {W, 1, "", ECOSKPD, 0x00010000, 0}, {M, 1, "[drm] initialized overlay support", 0x0, 0x0, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, {R, 1, "", _PIPEBCONF, 0x00000000, 0}, {R, 1, "", LVDS, 0x40000000, 0}, {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, @@ -176,8 +97,6 @@ struct iodef iodefs[] = { {R, 1, "", LVDS, 0x40000000, 0}, {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, {R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, {R, 1, "", _DSPACNTR, 0x00000000, 0}, {R, 1, "", _PIPEBCONF, 0x00000000, 0}, {W, 1, "", _PIPEBCONF, 0x00000000, 0}, @@ -188,7 +107,6 @@ struct iodef iodefs[] = { {R, 1, "", LVDS, 0x40000000, 0}, {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, {R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, {R, 1, "", _PIPEBCONF, 0x00000000, 0}, {W, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, {R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, @@ -210,45 +128,15 @@ struct iodef iodefs[] = { {R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, {W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800, 0}, {W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", 0x5100, 0x00000002, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 2, "", 0x5108, 0x00009c00, 0}, -{W, 1, "", 0x5104, 0x80000000, 0}, -{W, 1, "", 0x5104, 0x00000000, 0}, -{W, 2, "", 0x5100, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _FPA0, 0x00020e08, 0}, -{W, 1, "", _FPA1, 0x00020e08, 0}, -{W, 1, "", _DPLL_A, 0x14020003, 0}, -{W, 2, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{W, 1, "", _HBLANK_A, 0x06af04ff, 0}, -{W, 1, "", _HSYNC_A, 0x05d70557, 0}, -{W, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{W, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{W, 1, "", _VSYNC_A, 0x04090402, 0}, -{W, 1, "", _PIPEASRC, 0x04ff03ff, 0}, {W, 1, "", _DSPBSIZE, 0x03ff04ff, 0}, {W, 1, "", _DSPBPOS, 0x00000000, 0}, {W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{R, 2, "", _PIPEASTAT, 0x00000000, 0}, -{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{R, 1, "", _PIPEASTAT, 0x00000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, {W, 1, "", _DSPBCNTR, 0x40000000, 0}, {R, 1, "", _DSPBCNTR, 0x40000000, 0}, {W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBSTRIDE, 0x00001400, 0}, {W, 1, "", _DSPBADDR, 0x00020000, 0}, {R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, {W, 1, "", FW_BLC, 0x011d011a, 0}, {W, 1, "", FW_BLC2, 0x00000102, 0}, {R, 1, "", TV_CTL, 0x00000000, 0}, @@ -273,242 +161,20 @@ struct iodef iodefs[] = { {W, 1, "", TV_CSC_V2, 0x06d00200, 0}, {W, 1, "", TV_CLR_KNOBS, 0x00606000, 0}, {W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEADSL, 0x0000029e, 0}, -{R, 3, "", _PIPEADSL, 0x000003ff, 0}, -{W, 1, "", _PFA_CTL_1, 0x80000000, 0}, -{W, 1, "", _PFA_WIN_POS, 0x00360024, 0}, -{W, 1, "", _PFA_WIN_SZ, 0x02640198, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", TV_H_LUMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_LUMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_LUMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_LUMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_LUMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_LUMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_LUMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_LUMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_LUMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_LUMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_LUMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_LUMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_LUMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_LUMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_LUMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_LUMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_LUMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_LUMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_LUMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_LUMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68180, 0x3ae0b160, 0}, -{W, 1, "", 0x68184, 0x2b001810, 0}, -{W, 1, "", 0x68188, 0xb0c03120, 0}, -{W, 1, "", 0x6818c, 0xb140b020, 0}, -{W, 1, "", 0x68190, 0x18283ba0, 0}, -{W, 1, "", 0x68194, 0x30c02a80, 0}, -{W, 1, "", 0x68198, 0xb020b0a0, 0}, -{W, 1, "", 0x6819c, 0x3c60b140, 0}, -{W, 1, "", 0x681a0, 0x2a201838, 0}, -{W, 1, "", 0x681a4, 0xb0a03080, 0}, -{W, 1, "", 0x681a8, 0xb120b020, 0}, -{W, 1, "", 0x681ac, 0x18383d20, 0}, -{W, 1, "", 0x681b0, 0x304029c0, 0}, -{W, 1, "", 0x681b4, 0xb040b080, 0}, -{W, 1, "", 0x681b8, 0x3de0b100, 0}, -{W, 1, "", 0x681bc, 0x29601848, 0}, -{W, 1, "", 0x681c0, 0xb0803000, 0}, -{W, 1, "", 0x681c4, 0xb100b040, 0}, -{W, 1, "", 0x681c8, 0x18483ec0, 0}, -{W, 1, "", 0x681cc, 0xb0402900, 0}, -{W, 1, "", 0x681d0, 0xb040b060, 0}, -{W, 1, "", 0x681d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x681d8, 0x28801858, 0}, -{W, 1, "", 0x681dc, 0xb060b080, 0}, -{W, 1, "", 0x681e0, 0xb0a0b060, 0}, -{W, 1, "", 0x681e4, 0x18602820, 0}, -{W, 1, "", 0x681e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_LUMA_59, 0x0000b060, 0}, -{W, 1, "", TV_H_CHROMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_CHROMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_CHROMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_CHROMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_CHROMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_CHROMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_CHROMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_CHROMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_CHROMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_CHROMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_CHROMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_CHROMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_CHROMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_CHROMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68280, 0x3ae0b160, 0}, -{W, 1, "", 0x68284, 0x2b001810, 0}, -{W, 1, "", 0x68288, 0xb0c03120, 0}, -{W, 1, "", 0x6828c, 0xb140b020, 0}, -{W, 1, "", 0x68290, 0x18283ba0, 0}, -{W, 1, "", 0x68294, 0x30c02a80, 0}, -{W, 1, "", 0x68298, 0xb020b0a0, 0}, -{W, 1, "", 0x6829c, 0x3c60b140, 0}, -{W, 1, "", 0x682a0, 0x2a201838, 0}, -{W, 1, "", 0x682a4, 0xb0a03080, 0}, -{W, 1, "", 0x682a8, 0xb120b020, 0}, -{W, 1, "", 0x682ac, 0x18383d20, 0}, -{W, 1, "", 0x682b0, 0x304029c0, 0}, -{W, 1, "", 0x682b4, 0xb040b080, 0}, -{W, 1, "", 0x682b8, 0x3de0b100, 0}, -{W, 1, "", 0x682bc, 0x29601848, 0}, -{W, 1, "", 0x682c0, 0xb0803000, 0}, -{W, 1, "", 0x682c4, 0xb100b040, 0}, -{W, 1, "", 0x682c8, 0x18483ec0, 0}, -{W, 1, "", 0x682cc, 0xb0402900, 0}, -{W, 1, "", 0x682d0, 0xb040b060, 0}, -{W, 1, "", 0x682d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x682d8, 0x28801858, 0}, -{W, 1, "", 0x682dc, 0xb060b080, 0}, -{W, 1, "", 0x682e0, 0xb0a0b060, 0}, -{W, 1, "", 0x682e4, 0x18602820, 0}, -{W, 1, "", 0x682e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_CHROMA_59, 0x0000b060, 0}, -{W, 1, "", TV_V_LUMA_0, 0x36403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x4, 0x2d002cc0, 0}, -{W, 1, "", TV_V_LUMA_0+0x8, 0x30003640, 0}, -{W, 1, "", TV_V_LUMA_0+0xc, 0x2d0036c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x10, 0x35c02cc0, 0}, -{W, 1, "", TV_V_LUMA_0+0x14, 0x37403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x18, 0x2c802d40, 0}, -{W, 1, "", TV_V_LUMA_0+0x1c, 0x30003540, 0}, -{W, 1, "", TV_V_LUMA_0+0x20, 0x2d8037c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x24, 0x34c02c40, 0}, -{W, 1, "", TV_V_LUMA_0+0x28, 0x38403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x2c, 0x2bc02e00, 0}, -{W, 1, "", TV_V_LUMA_0+0x30, 0x30003440, 0}, -{W, 1, "", TV_V_LUMA_0+0x34, 0x2e2038c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x38, 0x34002b80, 0}, -{W, 1, "", TV_V_LUMA_0+0x3c, 0x39803000, 0}, -{W, 1, "", TV_V_LUMA_0+0x40, 0x2b402e40, 0}, -{W, 1, "", TV_V_LUMA_0+0x44, 0x30003380, 0}, -{W, 1, "", TV_V_LUMA_0+0x48, 0x2e603a00, 0}, -{W, 1, "", TV_V_LUMA_0+0x4c, 0x33402b00, 0}, -{W, 1, "", TV_V_LUMA_0+0x50, 0x3a803040, 0}, -{W, 1, "", TV_V_LUMA_0+0x54, 0x2a802ea0, 0}, -{W, 1, "", TV_V_LUMA_0+0x58, 0x30403300, 0}, -{W, 1, "", TV_V_LUMA_0+0x5c, 0x2ec03b40, 0}, -{W, 1, "", TV_V_LUMA_0+0x60, 0x32802a40, 0}, -{W, 1, "", TV_V_LUMA_0+0x64, 0x3c003040, 0}, -{W, 1, "", TV_V_LUMA_0+0x68, 0x2a002ec0, 0}, -{W, 1, "", TV_V_LUMA_0+0x6c, 0x30803240, 0}, -{W, 1, "", TV_V_LUMA_0+0x70, 0x2ec03c80, 0}, -{W, 1, "", TV_V_LUMA_0+0x74, 0x320029c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x78, 0x3d403080, 0}, -{W, 1, "", TV_V_LUMA_0+0x7c, 0x29402f00, 0}, -{W, 1, "", 0x68380, 0x308031c0, 0}, -{W, 1, "", 0x68384, 0x2f203dc0, 0}, -{W, 1, "", 0x68388, 0x31802900, 0}, -{W, 1, "", 0x6838c, 0x3e8030c0, 0}, -{W, 1, "", 0x68390, 0x28802f40, 0}, -{W, 1, "", 0x68394, 0x30c03140, 0}, -{W, 1, "", 0x68398, 0x2f203f40, 0}, -{W, 1, "", 0x6839c, 0x31402840, 0}, -{W, 1, "", 0x683a0, 0x28003100, 0}, -{W, 1, "", 0x683a4, 0x28002f00, 0}, -{W, 1, "", TV_V_LUMA_42, 0x00003100, 0}, -{W, 1, "", TV_V_CHROMA_0, 0x36403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x4, 0x2d002cc0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x8, 0x30003640, 0}, -{W, 1, "", TV_V_CHROMA_0+0xc, 0x2d0036c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x10, 0x35c02cc0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x14, 0x37403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x18, 0x2c802d40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x1c, 0x30003540, 0}, -{W, 1, "", TV_V_CHROMA_0+0x20, 0x2d8037c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x24, 0x34c02c40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x28, 0x38403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x2c, 0x2bc02e00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x30, 0x30003440, 0}, -{W, 1, "", TV_V_CHROMA_0+0x34, 0x2e2038c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x38, 0x34002b80, 0}, -{W, 1, "", TV_V_CHROMA_0+0x3c, 0x39803000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x40, 0x2b402e40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x44, 0x30003380, 0}, -{W, 1, "", TV_V_CHROMA_0+0x48, 0x2e603a00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x4c, 0x33402b00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x50, 0x3a803040, 0}, -{W, 1, "", TV_V_CHROMA_0+0x54, 0x2a802ea0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x58, 0x30403300, 0}, -{W, 1, "", TV_V_CHROMA_0+0x5c, 0x2ec03b40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x60, 0x32802a40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x64, 0x3c003040, 0}, -{W, 1, "", TV_V_CHROMA_0+0x68, 0x2a002ec0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x6c, 0x30803240, 0}, -{W, 1, "", TV_V_CHROMA_0+0x70, 0x2ec03c80, 0}, -{W, 1, "", TV_V_CHROMA_0+0x74, 0x320029c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x78, 0x3d403080, 0}, -{W, 1, "", TV_V_CHROMA_0+0x7c, 0x29402f00, 0}, -{W, 1, "", 0x68480, 0x308031c0, 0}, -{W, 1, "", 0x68484, 0x2f203dc0, 0}, -{W, 1, "", 0x68488, 0x31802900, 0}, -{W, 1, "", 0x6848c, 0x3e8030c0, 0}, -{W, 1, "", 0x68490, 0x28802f40, 0}, -{W, 1, "", 0x68494, 0x30c03140, 0}, -{W, 1, "", 0x68498, 0x2f203f40, 0}, -{W, 1, "", 0x6849c, 0x31402840, 0}, -{W, 1, "", 0x684a0, 0x28003100, 0}, -{W, 1, "", 0x684a4, 0x28002f00, 0}, -{W, 1, "", TV_V_CHROMA_42, 0x00003100, 0}, +{W, 1, "", _PFA_CTL_1, 0x00000000, 0}, +{W, 1, "", _PFA_WIN_POS, 0x00000000, 0}, +{W, 1, "", _PFA_WIN_SZ, 0x00000000, 0}, {R, 1, "", TV_DAC, 0x70000000, 0}, {W, 1, "", TV_DAC, 0x00000000, 0}, {W, 1, "", TV_CTL, 0x000c0000, 0}, {R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, -{W, 1, "", INSTPM+0x20, 0x0001002f, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, +{W, 1, "", FW_BLC_SELF, 0x0001002f, 0}, {W, 1, "", FW_BLC, 0x0101011a, 0}, {W, 1, "", FW_BLC2, 0x00000102, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80008000, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000, 0}, {R, 1, "", PP_CONTROL, 0xabcd0000, 0}, {R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{W, 3, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{R, 2, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, {R, 1, "", _DSPBCNTR, 0x58000000, 0}, {W, 1, "", _DSPBCNTR, 0xd8000000, 0}, {R, 1, "", _DSPBADDR, 0x00020000, 0}, @@ -517,262 +183,6 @@ struct iodef iodefs[] = { {W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, {R, 2, "", _PIPEASTAT, 0x00000000, 0}, {R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _PALETTE_A, 0x00000000, 0}, -{W, 1, "", _PALETTE_A+0x4, 0x00010101, 0}, -{W, 1, "", _PALETTE_A+0x8, 0x00020202, 0}, -{W, 1, "", _PALETTE_A+0xc, 0x00030303, 0}, -{W, 1, "", _PALETTE_A+0x10, 0x00040404, 0}, -{W, 1, "", _PALETTE_A+0x14, 0x00050505, 0}, -{W, 1, "", _PALETTE_A+0x18, 0x00060606, 0}, -{W, 1, "", _PALETTE_A+0x1c, 0x00070707, 0}, -{W, 1, "", _PALETTE_A+0x20, 0x00080808, 0}, -{W, 1, "", _PALETTE_A+0x24, 0x00090909, 0}, -{W, 1, "", _PALETTE_A+0x28, 0x000a0a0a, 0}, -{W, 1, "", _PALETTE_A+0x2c, 0x000b0b0b, 0}, -{W, 1, "", _PALETTE_A+0x30, 0x000c0c0c, 0}, -{W, 1, "", _PALETTE_A+0x34, 0x000d0d0d, 0}, -{W, 1, "", _PALETTE_A+0x38, 0x000e0e0e, 0}, -{W, 1, "", _PALETTE_A+0x3c, 0x000f0f0f, 0}, -{W, 1, "", _PALETTE_A+0x40, 0x00101010, 0}, -{W, 1, "", _PALETTE_A+0x44, 0x00111111, 0}, -{W, 1, "", _PALETTE_A+0x48, 0x00121212, 0}, -{W, 1, "", _PALETTE_A+0x4c, 0x00131313, 0}, -{W, 1, "", _PALETTE_A+0x50, 0x00141414, 0}, -{W, 1, "", _PALETTE_A+0x54, 0x00151515, 0}, -{W, 1, "", _PALETTE_A+0x58, 0x00161616, 0}, -{W, 1, "", _PALETTE_A+0x5c, 0x00171717, 0}, -{W, 1, "", _PALETTE_A+0x60, 0x00181818, 0}, -{W, 1, "", _PALETTE_A+0x64, 0x00191919, 0}, -{W, 1, "", _PALETTE_A+0x68, 0x001a1a1a, 0}, -{W, 1, "", _PALETTE_A+0x6c, 0x001b1b1b, 0}, -{W, 1, "", _PALETTE_A+0x70, 0x001c1c1c, 0}, -{W, 1, "", _PALETTE_A+0x74, 0x001d1d1d, 0}, -{W, 1, "", _PALETTE_A+0x78, 0x001e1e1e, 0}, -{W, 1, "", _PALETTE_A+0x7c, 0x001f1f1f, 0}, -{W, 1, "", 0xa080, 0x00202020, 0}, -{W, 1, "", 0xa084, 0x00212121, 0}, -{W, 1, "", 0xa088, 0x00222222, 0}, -{W, 1, "", 0xa08c, 0x00232323, 0}, -{W, 1, "", 0xa090, 0x00242424, 0}, -{W, 1, "", 0xa094, 0x00252525, 0}, -{W, 1, "", 0xa098, 0x00262626, 0}, -{W, 1, "", 0xa09c, 0x00272727, 0}, -{W, 1, "", 0xa0a0, 0x00282828, 0}, -{W, 1, "", 0xa0a4, 0x00292929, 0}, -{W, 1, "", 0xa0a8, 0x002a2a2a, 0}, -{W, 1, "", 0xa0ac, 0x002b2b2b, 0}, -{W, 1, "", 0xa0b0, 0x002c2c2c, 0}, -{W, 1, "", 0xa0b4, 0x002d2d2d, 0}, -{W, 1, "", 0xa0b8, 0x002e2e2e, 0}, -{W, 1, "", 0xa0bc, 0x002f2f2f, 0}, -{W, 1, "", 0xa0c0, 0x00303030, 0}, -{W, 1, "", 0xa0c4, 0x00313131, 0}, -{W, 1, "", 0xa0c8, 0x00323232, 0}, -{W, 1, "", 0xa0cc, 0x00333333, 0}, -{W, 1, "", 0xa0d0, 0x00343434, 0}, -{W, 1, "", 0xa0d4, 0x00353535, 0}, -{W, 1, "", 0xa0d8, 0x00363636, 0}, -{W, 1, "", 0xa0dc, 0x00373737, 0}, -{W, 1, "", 0xa0e0, 0x00383838, 0}, -{W, 1, "", 0xa0e4, 0x00393939, 0}, -{W, 1, "", 0xa0e8, 0x003a3a3a, 0}, -{W, 1, "", 0xa0ec, 0x003b3b3b, 0}, -{W, 1, "", 0xa0f0, 0x003c3c3c, 0}, -{W, 1, "", 0xa0f4, 0x003d3d3d, 0}, -{W, 1, "", 0xa0f8, 0x003e3e3e, 0}, -{W, 1, "", 0xa0fc, 0x003f3f3f, 0}, -{W, 1, "", 0xa100, 0x00404040, 0}, -{W, 1, "", 0xa104, 0x00414141, 0}, -{W, 1, "", 0xa108, 0x00424242, 0}, -{W, 1, "", 0xa10c, 0x00434343, 0}, -{W, 1, "", 0xa110, 0x00444444, 0}, -{W, 1, "", 0xa114, 0x00454545, 0}, -{W, 1, "", 0xa118, 0x00464646, 0}, -{W, 1, "", 0xa11c, 0x00474747, 0}, -{W, 1, "", 0xa120, 0x00484848, 0}, -{W, 1, "", 0xa124, 0x00494949, 0}, -{W, 1, "", 0xa128, 0x004a4a4a, 0}, -{W, 1, "", 0xa12c, 0x004b4b4b, 0}, -{W, 1, "", 0xa130, 0x004c4c4c, 0}, -{W, 1, "", 0xa134, 0x004d4d4d, 0}, -{W, 1, "", 0xa138, 0x004e4e4e, 0}, -{W, 1, "", 0xa13c, 0x004f4f4f, 0}, -{W, 1, "", 0xa140, 0x00505050, 0}, -{W, 1, "", 0xa144, 0x00515151, 0}, -{W, 1, "", 0xa148, 0x00525252, 0}, -{W, 1, "", 0xa14c, 0x00535353, 0}, -{W, 1, "", 0xa150, 0x00545454, 0}, -{W, 1, "", 0xa154, 0x00555555, 0}, -{W, 1, "", 0xa158, 0x00565656, 0}, -{W, 1, "", 0xa15c, 0x00575757, 0}, -{W, 1, "", 0xa160, 0x00585858, 0}, -{W, 1, "", 0xa164, 0x00595959, 0}, -{W, 1, "", 0xa168, 0x005a5a5a, 0}, -{W, 1, "", 0xa16c, 0x005b5b5b, 0}, -{W, 1, "", 0xa170, 0x005c5c5c, 0}, -{W, 1, "", 0xa174, 0x005d5d5d, 0}, -{W, 1, "", 0xa178, 0x005e5e5e, 0}, -{W, 1, "", 0xa17c, 0x005f5f5f, 0}, -{W, 1, "", 0xa180, 0x00606060, 0}, -{W, 1, "", 0xa184, 0x00616161, 0}, -{W, 1, "", FORCEWAKE_MT, 0x00626262, 0}, -{W, 1, "", FORCEWAKE, 0x00636363, 0}, -{W, 1, "", 0xa190, 0x00646464, 0}, -{W, 1, "", 0xa194, 0x00656565, 0}, -{W, 1, "", 0xa198, 0x00666666, 0}, -{W, 1, "", 0xa19c, 0x00676767, 0}, -{W, 1, "", 0xa1a0, 0x00686868, 0}, -{W, 1, "", 0xa1a4, 0x00696969, 0}, -{W, 1, "", 0xa1a8, 0x006a6a6a, 0}, -{W, 1, "", 0xa1ac, 0x006b6b6b, 0}, -{W, 1, "", 0xa1b0, 0x006c6c6c, 0}, -{W, 1, "", 0xa1b4, 0x006d6d6d, 0}, -{W, 1, "", 0xa1b8, 0x006e6e6e, 0}, -{W, 1, "", 0xa1bc, 0x006f6f6f, 0}, -{W, 1, "", 0xa1c0, 0x00707070, 0}, -{W, 1, "", 0xa1c4, 0x00717171, 0}, -{W, 1, "", 0xa1c8, 0x00727272, 0}, -{W, 1, "", 0xa1cc, 0x00737373, 0}, -{W, 1, "", 0xa1d0, 0x00747474, 0}, -{W, 1, "", 0xa1d4, 0x00757575, 0}, -{W, 1, "", 0xa1d8, 0x00767676, 0}, -{W, 1, "", 0xa1dc, 0x00777777, 0}, -{W, 1, "", 0xa1e0, 0x00787878, 0}, -{W, 1, "", 0xa1e4, 0x00797979, 0}, -{W, 1, "", 0xa1e8, 0x007a7a7a, 0}, -{W, 1, "", 0xa1ec, 0x007b7b7b, 0}, -{W, 1, "", 0xa1f0, 0x007c7c7c, 0}, -{W, 1, "", 0xa1f4, 0x007d7d7d, 0}, -{W, 1, "", 0xa1f8, 0x007e7e7e, 0}, -{W, 1, "", 0xa1fc, 0x007f7f7f, 0}, -{W, 1, "", 0xa200, 0x00808080, 0}, -{W, 1, "", 0xa204, 0x00818181, 0}, -{W, 1, "", 0xa208, 0x00828282, 0}, -{W, 1, "", 0xa20c, 0x00838383, 0}, -{W, 1, "", 0xa210, 0x00848484, 0}, -{W, 1, "", 0xa214, 0x00858585, 0}, -{W, 1, "", 0xa218, 0x00868686, 0}, -{W, 1, "", 0xa21c, 0x00878787, 0}, -{W, 1, "", 0xa220, 0x00888888, 0}, -{W, 1, "", 0xa224, 0x00898989, 0}, -{W, 1, "", 0xa228, 0x008a8a8a, 0}, -{W, 1, "", 0xa22c, 0x008b8b8b, 0}, -{W, 1, "", 0xa230, 0x008c8c8c, 0}, -{W, 1, "", 0xa234, 0x008d8d8d, 0}, -{W, 1, "", 0xa238, 0x008e8e8e, 0}, -{W, 1, "", 0xa23c, 0x008f8f8f, 0}, -{W, 1, "", 0xa240, 0x00909090, 0}, -{W, 1, "", 0xa244, 0x00919191, 0}, -{W, 1, "", 0xa248, 0x00929292, 0}, -{W, 1, "", 0xa24c, 0x00939393, 0}, -{W, 1, "", 0xa250, 0x00949494, 0}, -{W, 1, "", 0xa254, 0x00959595, 0}, -{W, 1, "", 0xa258, 0x00969696, 0}, -{W, 1, "", 0xa25c, 0x00979797, 0}, -{W, 1, "", 0xa260, 0x00989898, 0}, -{W, 1, "", 0xa264, 0x00999999, 0}, -{W, 1, "", 0xa268, 0x009a9a9a, 0}, -{W, 1, "", 0xa26c, 0x009b9b9b, 0}, -{W, 1, "", 0xa270, 0x009c9c9c, 0}, -{W, 1, "", 0xa274, 0x009d9d9d, 0}, -{W, 1, "", 0xa278, 0x009e9e9e, 0}, -{W, 1, "", 0xa27c, 0x009f9f9f, 0}, -{W, 1, "", 0xa280, 0x00a0a0a0, 0}, -{W, 1, "", 0xa284, 0x00a1a1a1, 0}, -{W, 1, "", 0xa288, 0x00a2a2a2, 0}, -{W, 1, "", 0xa28c, 0x00a3a3a3, 0}, -{W, 1, "", 0xa290, 0x00a4a4a4, 0}, -{W, 1, "", 0xa294, 0x00a5a5a5, 0}, -{W, 1, "", 0xa298, 0x00a6a6a6, 0}, -{W, 1, "", 0xa29c, 0x00a7a7a7, 0}, -{W, 1, "", 0xa2a0, 0x00a8a8a8, 0}, -{W, 1, "", 0xa2a4, 0x00a9a9a9, 0}, -{W, 1, "", 0xa2a8, 0x00aaaaaa, 0}, -{W, 1, "", 0xa2ac, 0x00ababab, 0}, -{W, 1, "", 0xa2b0, 0x00acacac, 0}, -{W, 1, "", 0xa2b4, 0x00adadad, 0}, -{W, 1, "", 0xa2b8, 0x00aeaeae, 0}, -{W, 1, "", 0xa2bc, 0x00afafaf, 0}, -{W, 1, "", 0xa2c0, 0x00b0b0b0, 0}, -{W, 1, "", 0xa2c4, 0x00b1b1b1, 0}, -{W, 1, "", 0xa2c8, 0x00b2b2b2, 0}, -{W, 1, "", 0xa2cc, 0x00b3b3b3, 0}, -{W, 1, "", 0xa2d0, 0x00b4b4b4, 0}, -{W, 1, "", 0xa2d4, 0x00b5b5b5, 0}, -{W, 1, "", 0xa2d8, 0x00b6b6b6, 0}, -{W, 1, "", 0xa2dc, 0x00b7b7b7, 0}, -{W, 1, "", 0xa2e0, 0x00b8b8b8, 0}, -{W, 1, "", 0xa2e4, 0x00b9b9b9, 0}, -{W, 1, "", 0xa2e8, 0x00bababa, 0}, -{W, 1, "", 0xa2ec, 0x00bbbbbb, 0}, -{W, 1, "", 0xa2f0, 0x00bcbcbc, 0}, -{W, 1, "", 0xa2f4, 0x00bdbdbd, 0}, -{W, 1, "", 0xa2f8, 0x00bebebe, 0}, -{W, 1, "", 0xa2fc, 0x00bfbfbf, 0}, -{W, 1, "", 0xa300, 0x00c0c0c0, 0}, -{W, 1, "", 0xa304, 0x00c1c1c1, 0}, -{W, 1, "", 0xa308, 0x00c2c2c2, 0}, -{W, 1, "", 0xa30c, 0x00c3c3c3, 0}, -{W, 1, "", 0xa310, 0x00c4c4c4, 0}, -{W, 1, "", 0xa314, 0x00c5c5c5, 0}, -{W, 1, "", 0xa318, 0x00c6c6c6, 0}, -{W, 1, "", 0xa31c, 0x00c7c7c7, 0}, -{W, 1, "", 0xa320, 0x00c8c8c8, 0}, -{W, 1, "", 0xa324, 0x00c9c9c9, 0}, -{W, 1, "", 0xa328, 0x00cacaca, 0}, -{W, 1, "", 0xa32c, 0x00cbcbcb, 0}, -{W, 1, "", 0xa330, 0x00cccccc, 0}, -{W, 1, "", 0xa334, 0x00cdcdcd, 0}, -{W, 1, "", 0xa338, 0x00cecece, 0}, -{W, 1, "", 0xa33c, 0x00cfcfcf, 0}, -{W, 1, "", 0xa340, 0x00d0d0d0, 0}, -{W, 1, "", 0xa344, 0x00d1d1d1, 0}, -{W, 1, "", 0xa348, 0x00d2d2d2, 0}, -{W, 1, "", 0xa34c, 0x00d3d3d3, 0}, -{W, 1, "", 0xa350, 0x00d4d4d4, 0}, -{W, 1, "", 0xa354, 0x00d5d5d5, 0}, -{W, 1, "", 0xa358, 0x00d6d6d6, 0}, -{W, 1, "", 0xa35c, 0x00d7d7d7, 0}, -{W, 1, "", 0xa360, 0x00d8d8d8, 0}, -{W, 1, "", 0xa364, 0x00d9d9d9, 0}, -{W, 1, "", 0xa368, 0x00dadada, 0}, -{W, 1, "", 0xa36c, 0x00dbdbdb, 0}, -{W, 1, "", 0xa370, 0x00dcdcdc, 0}, -{W, 1, "", 0xa374, 0x00dddddd, 0}, -{W, 1, "", 0xa378, 0x00dedede, 0}, -{W, 1, "", 0xa37c, 0x00dfdfdf, 0}, -{W, 1, "", 0xa380, 0x00e0e0e0, 0}, -{W, 1, "", 0xa384, 0x00e1e1e1, 0}, -{W, 1, "", 0xa388, 0x00e2e2e2, 0}, -{W, 1, "", 0xa38c, 0x00e3e3e3, 0}, -{W, 1, "", 0xa390, 0x00e4e4e4, 0}, -{W, 1, "", 0xa394, 0x00e5e5e5, 0}, -{W, 1, "", 0xa398, 0x00e6e6e6, 0}, -{W, 1, "", 0xa39c, 0x00e7e7e7, 0}, -{W, 1, "", 0xa3a0, 0x00e8e8e8, 0}, -{W, 1, "", 0xa3a4, 0x00e9e9e9, 0}, -{W, 1, "", 0xa3a8, 0x00eaeaea, 0}, -{W, 1, "", 0xa3ac, 0x00ebebeb, 0}, -{W, 1, "", 0xa3b0, 0x00ececec, 0}, -{W, 1, "", 0xa3b4, 0x00ededed, 0}, -{W, 1, "", 0xa3b8, 0x00eeeeee, 0}, -{W, 1, "", 0xa3bc, 0x00efefef, 0}, -{W, 1, "", 0xa3c0, 0x00f0f0f0, 0}, -{W, 1, "", 0xa3c4, 0x00f1f1f1, 0}, -{W, 1, "", 0xa3c8, 0x00f2f2f2, 0}, -{W, 1, "", 0xa3cc, 0x00f3f3f3, 0}, -{W, 1, "", 0xa3d0, 0x00f4f4f4, 0}, -{W, 1, "", 0xa3d4, 0x00f5f5f5, 0}, -{W, 1, "", 0xa3d8, 0x00f6f6f6, 0}, -{W, 1, "", 0xa3dc, 0x00f7f7f7, 0}, -{W, 1, "", 0xa3e0, 0x00f8f8f8, 0}, -{W, 1, "", 0xa3e4, 0x00f9f9f9, 0}, -{W, 1, "", 0xa3e8, 0x00fafafa, 0}, -{W, 1, "", 0xa3ec, 0x00fbfbfb, 0}, -{W, 1, "", 0xa3f0, 0x00fcfcfc, 0}, -{W, 1, "", 0xa3f4, 0x00fdfdfd, 0}, -{W, 1, "", 0xa3f8, 0x00fefefe, 0}, -{W, 1, "", 0xa3fc, 0x00ffffff, 0}, {R, 1, "", TV_CTL, 0x000c0000, 0}, {W, 1, "", TV_CTL, 0x800c0000, 0}, {R, 1, "", LVDS, 0x40000000, 0}, @@ -781,7 +191,6 @@ struct iodef iodefs[] = { {R, 1, "", LVDS, 0x40000000, 0}, {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, {R, 1, "", TV_CTL, 0x800c0000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, {R, 1, "", _PIPEBCONF, 0x00000000, 0}, {R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, {W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, @@ -805,75 +214,6 @@ struct iodef iodefs[] = { {R, 1, "", TV_CTL, 0x800c0000, 0}, {W, 1, "", TV_CTL, 0x000c0000, 0}, {W, 1, "", INSTPM, 0x08000800, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x62029b1b, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6217572c, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x63156af7, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x64137fac, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6510b8c6, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6607c3b5, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x661c804f, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x671a949c, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6818a96d, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6915e1d1, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6a0cec77, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6b04d273, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6c02e710, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6d00fb0c, 0}, -{R, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{R, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, -{R, 1, "", _PIPEA_FLIPCOUNT_GM45, 0x6d1b0b04, 0}, -{R, 1, "", _PIPEA_FRMCOUNT_GM45, 0x00000000, 0}, {R, 1, "", _DSPBCNTR, 0xd8000000, 0}, {W, 1, "", _DSPBCNTR, 0x58000000, 0}, {R, 1, "", _DSPBADDR, 0x00020000, 0}, @@ -884,31 +224,20 @@ struct iodef iodefs[] = { {R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, {R, 1, "", _DSPACNTR, 0x00000000, 0}, {R, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 2, "", _PIPEADSL, 0x000003ff, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{W, 1, "", _DPLL_A, 0x14020003, 0}, {R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, {W, 1, "", FW_BLC, 0x011d011a, 0}, {W, 1, "", FW_BLC2, 0x00000102, 0}, -{R, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, {R, 1, "", LVDS, 0x40000000, 0}, {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, {R, 1, "", TV_CTL, 0x000c0000, 0}, {R, 1, "", LVDS, 0x40000000, 0}, {R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, {R, 1, "", TV_CTL, 0x000c0000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, {R, 1, "", _PIPEBCONF, 0x00000000, 0}, {M, 1, "fbcon:inteldrmfb (fb0) is primary device", 0x0, 0x0, 0}, {R, 1, "", _PIPEBCONF, 0x00000000, 0}, {R, 2, "", LVDS, 0x40000000, 0}, -{W, 1, "", _FPB0, 0x00020e09, 0}, -{W, 1, "", _FPB1, FP_M1_DIV_SHIFT | DPLLA_INPUT_BUFFER_ENABLE | VF_UNIT_CLOCK_GATE_DISABLE | 0x00020e09, 0}, {W, 1, "", _DPLL_B, DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x18046000, 0}, {R, 1, "", LVDS, 0x40000000, 0}, {W, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0}, @@ -923,1347 +252,22 @@ struct iodef iodefs[] = { {W, 1, "", _PIPEBSRC, 0x03ff02ff, 0}, {W, 1, "", _DSPASIZE, 0x02ff03ff, 0}, {W, 1, "", _DSPASTRIDE+0x4, 0x00000000, 0}, -{W, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", _PIPEBCONF, 0x80000000, 0}, -{R, 1, "", _PIPEBSTAT, 0x00000040, 0}, -{W, 1, "", _PIPEBSTAT, 0x00000042, 0}, -{R, 1, "", _PIPEBSTAT, 0x00000000, 0}, -{R, 2, "", _PIPEBSTAT, 0x00000202, 0}, -{W, 1, "", _PIPEBSTAT, 0x00000202, 0}, -{R, 3, "", _PIPEBSTAT, 0x00000000, 0}, -{R, 1, "", _PIPEBSTAT, 0x00000202, 0}, -{W, 1, "", _DSPACNTR, 0x41000000, 0}, -{R, 1, "", _DSPACNTR, 0x41000000, 0}, -{W, 1, "", _DSPACNTR, 0x59000000, 0}, -{W, 1, "", _DSPASTRIDE, 0x00001000, 0}, -{W, 1, "", _DSPAADDR, 0x00020000, 0}, {R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, {W, 1, "", FW_BLC, 0x011d011a, 0}, {W, 1, "", FW_BLC2, 0x00000102, 0}, {R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, -{W, 1, "", INSTPM+0x20, 0x0001003f, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, +{W, 1, "", FW_BLC_SELF, 0x0001003f, 0}, {W, 1, "", FW_BLC, 0x011d0109, 0}, {W, 1, "", FW_BLC2, 0x00000102, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80008000, 0}, -{R, 1, "", PP_CONTROL, 0xabcd0000, 0}, -{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0}, -{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0}, -{W, 3, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0}, -{R, 1, "", _DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000, 0}, -{R, 2, "", _PIPEBCONF, 0x80000000, 0}, -{R, 1, "", _DSPACNTR, 0x59000000, 0}, -{W, 1, "", _DSPACNTR, 0xd9000000, 0}, -{R, 1, "", _DSPAADDR, 0x00020000, 0}, -{W, 1, "", _DSPAADDR, 0x00020000, 0}, -{R, 1, "", _PIPEBSTAT, 0x00000202, 0}, -{W, 1, "", _PIPEBSTAT, 0x00000202, 0}, -{R, 3, "", _PIPEBSTAT, 0x00000000, 0}, -{R, 1, "", _PIPEBSTAT, 0x00000202, 0}, -{W, 1, "", _PALETTE_B, 0x00000000, 0}, -{W, 1, "", _PALETTE_B+0x4, 0x00010101, 0}, -{W, 1, "", _PALETTE_B+0x8, 0x00020202, 0}, -{W, 1, "", _PALETTE_B+0xc, 0x00030303, 0}, -{W, 1, "", _PALETTE_B+0x10, 0x00040404, 0}, -{W, 1, "", _PALETTE_B+0x14, 0x00050505, 0}, -{W, 1, "", _PALETTE_B+0x18, 0x00060606, 0}, -{W, 1, "", _PALETTE_B+0x1c, 0x00070707, 0}, -{W, 1, "", _PALETTE_B+0x20, 0x00080808, 0}, -{W, 1, "", _PALETTE_B+0x24, 0x00090909, 0}, -{W, 1, "", _PALETTE_B+0x28, 0x000a0a0a, 0}, -{W, 1, "", _PALETTE_B+0x2c, 0x000b0b0b, 0}, -{W, 1, "", _PALETTE_B+0x30, 0x000c0c0c, 0}, -{W, 1, "", _PALETTE_B+0x34, 0x000d0d0d, 0}, -{W, 1, "", _PALETTE_B+0x38, 0x000e0e0e, 0}, -{W, 1, "", _PALETTE_B+0x3c, 0x000f0f0f, 0}, -{W, 1, "", _PALETTE_B+0x40, 0x00101010, 0}, -{W, 1, "", _PALETTE_B+0x44, 0x00111111, 0}, -{W, 1, "", _PALETTE_B+0x48, 0x00121212, 0}, -{W, 1, "", _PALETTE_B+0x4c, 0x00131313, 0}, -{W, 1, "", _PALETTE_B+0x50, 0x00141414, 0}, -{W, 1, "", _PALETTE_B+0x54, 0x00151515, 0}, -{W, 1, "", _PALETTE_B+0x58, 0x00161616, 0}, -{W, 1, "", _PALETTE_B+0x5c, 0x00171717, 0}, -{W, 1, "", _PALETTE_B+0x60, 0x00181818, 0}, -{W, 1, "", _PALETTE_B+0x64, 0x00191919, 0}, -{W, 1, "", _PALETTE_B+0x68, 0x001a1a1a, 0}, -{W, 1, "", _PALETTE_B+0x6c, 0x001b1b1b, 0}, -{W, 1, "", _PALETTE_B+0x70, 0x001c1c1c, 0}, -{W, 1, "", _PALETTE_B+0x74, 0x001d1d1d, 0}, -{W, 1, "", _PALETTE_B+0x78, 0x001e1e1e, 0}, -{W, 1, "", _PALETTE_B+0x7c, 0x001f1f1f, 0}, -{W, 1, "", 0xa880, 0x00202020, 0}, -{W, 1, "", 0xa884, 0x00212121, 0}, -{W, 1, "", 0xa888, 0x00222222, 0}, -{W, 1, "", 0xa88c, 0x00232323, 0}, -{W, 1, "", 0xa890, 0x00242424, 0}, -{W, 1, "", 0xa894, 0x00252525, 0}, -{W, 1, "", 0xa898, 0x00262626, 0}, -{W, 1, "", 0xa89c, 0x00272727, 0}, -{W, 1, "", 0xa8a0, 0x00282828, 0}, -{W, 1, "", 0xa8a4, 0x00292929, 0}, -{W, 1, "", 0xa8a8, 0x002a2a2a, 0}, -{W, 1, "", 0xa8ac, 0x002b2b2b, 0}, -{W, 1, "", 0xa8b0, 0x002c2c2c, 0}, -{W, 1, "", 0xa8b4, 0x002d2d2d, 0}, -{W, 1, "", 0xa8b8, 0x002e2e2e, 0}, -{W, 1, "", 0xa8bc, 0x002f2f2f, 0}, -{W, 1, "", 0xa8c0, 0x00303030, 0}, -{W, 1, "", 0xa8c4, 0x00313131, 0}, -{W, 1, "", 0xa8c8, 0x00323232, 0}, -{W, 1, "", 0xa8cc, 0x00333333, 0}, -{W, 1, "", 0xa8d0, 0x00343434, 0}, -{W, 1, "", 0xa8d4, 0x00353535, 0}, -{W, 1, "", 0xa8d8, 0x00363636, 0}, -{W, 1, "", 0xa8dc, 0x00373737, 0}, -{W, 1, "", 0xa8e0, 0x00383838, 0}, -{W, 1, "", 0xa8e4, 0x00393939, 0}, -{W, 1, "", 0xa8e8, 0x003a3a3a, 0}, -{W, 1, "", 0xa8ec, 0x003b3b3b, 0}, -{W, 1, "", 0xa8f0, 0x003c3c3c, 0}, -{W, 1, "", 0xa8f4, 0x003d3d3d, 0}, -{W, 1, "", 0xa8f8, 0x003e3e3e, 0}, -{W, 1, "", 0xa8fc, 0x003f3f3f, 0}, -{W, 1, "", 0xa900, 0x00404040, 0}, -{W, 1, "", 0xa904, 0x00414141, 0}, -{W, 1, "", 0xa908, 0x00424242, 0}, -{W, 1, "", 0xa90c, 0x00434343, 0}, -{W, 1, "", 0xa910, 0x00444444, 0}, -{W, 1, "", 0xa914, 0x00454545, 0}, -{W, 1, "", 0xa918, 0x00464646, 0}, -{W, 1, "", 0xa91c, 0x00474747, 0}, -{W, 1, "", 0xa920, 0x00484848, 0}, -{W, 1, "", 0xa924, 0x00494949, 0}, -{W, 1, "", 0xa928, 0x004a4a4a, 0}, -{W, 1, "", 0xa92c, 0x004b4b4b, 0}, -{W, 1, "", 0xa930, 0x004c4c4c, 0}, -{W, 1, "", 0xa934, 0x004d4d4d, 0}, -{W, 1, "", 0xa938, 0x004e4e4e, 0}, -{W, 1, "", 0xa93c, 0x004f4f4f, 0}, -{W, 1, "", 0xa940, 0x00505050, 0}, -{W, 1, "", 0xa944, 0x00515151, 0}, -{W, 1, "", 0xa948, 0x00525252, 0}, -{W, 1, "", 0xa94c, 0x00535353, 0}, -{W, 1, "", 0xa950, 0x00545454, 0}, -{W, 1, "", 0xa954, 0x00555555, 0}, -{W, 1, "", 0xa958, 0x00565656, 0}, -{W, 1, "", 0xa95c, 0x00575757, 0}, -{W, 1, "", 0xa960, 0x00585858, 0}, -{W, 1, "", 0xa964, 0x00595959, 0}, -{W, 1, "", 0xa968, 0x005a5a5a, 0}, -{W, 1, "", 0xa96c, 0x005b5b5b, 0}, -{W, 1, "", 0xa970, 0x005c5c5c, 0}, -{W, 1, "", 0xa974, 0x005d5d5d, 0}, -{W, 1, "", 0xa978, 0x005e5e5e, 0}, -{W, 1, "", 0xa97c, 0x005f5f5f, 0}, -{W, 1, "", 0xa980, 0x00606060, 0}, -{W, 1, "", 0xa984, 0x00616161, 0}, -{W, 1, "", 0xa988, 0x00626262, 0}, -{W, 1, "", 0xa98c, 0x00636363, 0}, -{W, 1, "", 0xa990, 0x00646464, 0}, -{W, 1, "", 0xa994, 0x00656565, 0}, -{W, 1, "", 0xa998, 0x00666666, 0}, -{W, 1, "", 0xa99c, 0x00676767, 0}, -{W, 1, "", 0xa9a0, 0x00686868, 0}, -{W, 1, "", 0xa9a4, 0x00696969, 0}, -{W, 1, "", 0xa9a8, 0x006a6a6a, 0}, -{W, 1, "", 0xa9ac, 0x006b6b6b, 0}, -{W, 1, "", 0xa9b0, 0x006c6c6c, 0}, -{W, 1, "", 0xa9b4, 0x006d6d6d, 0}, -{W, 1, "", 0xa9b8, 0x006e6e6e, 0}, -{W, 1, "", 0xa9bc, 0x006f6f6f, 0}, -{W, 1, "", 0xa9c0, 0x00707070, 0}, -{W, 1, "", 0xa9c4, 0x00717171, 0}, -{W, 1, "", 0xa9c8, 0x00727272, 0}, -{W, 1, "", 0xa9cc, 0x00737373, 0}, -{W, 1, "", 0xa9d0, 0x00747474, 0}, -{W, 1, "", 0xa9d4, 0x00757575, 0}, -{W, 1, "", 0xa9d8, 0x00767676, 0}, -{W, 1, "", 0xa9dc, 0x00777777, 0}, -{W, 1, "", 0xa9e0, 0x00787878, 0}, -{W, 1, "", 0xa9e4, 0x00797979, 0}, -{W, 1, "", 0xa9e8, 0x007a7a7a, 0}, -{W, 1, "", 0xa9ec, 0x007b7b7b, 0}, -{W, 1, "", 0xa9f0, 0x007c7c7c, 0}, -{W, 1, "", 0xa9f4, 0x007d7d7d, 0}, -{W, 1, "", 0xa9f8, 0x007e7e7e, 0}, -{W, 1, "", 0xa9fc, 0x007f7f7f, 0}, -{W, 1, "", 0xaa00, 0x00808080, 0}, -{W, 1, "", 0xaa04, 0x00818181, 0}, -{W, 1, "", 0xaa08, 0x00828282, 0}, -{W, 1, "", 0xaa0c, 0x00838383, 0}, -{W, 1, "", 0xaa10, 0x00848484, 0}, -{W, 1, "", 0xaa14, 0x00858585, 0}, -{W, 1, "", 0xaa18, 0x00868686, 0}, -{W, 1, "", 0xaa1c, 0x00878787, 0}, -{W, 1, "", 0xaa20, 0x00888888, 0}, -{W, 1, "", 0xaa24, 0x00898989, 0}, -{W, 1, "", 0xaa28, 0x008a8a8a, 0}, -{W, 1, "", 0xaa2c, 0x008b8b8b, 0}, -{W, 1, "", 0xaa30, 0x008c8c8c, 0}, -{W, 1, "", 0xaa34, 0x008d8d8d, 0}, -{W, 1, "", 0xaa38, 0x008e8e8e, 0}, -{W, 1, "", 0xaa3c, 0x008f8f8f, 0}, -{W, 1, "", 0xaa40, 0x00909090, 0}, -{W, 1, "", 0xaa44, 0x00919191, 0}, -{W, 1, "", 0xaa48, 0x00929292, 0}, -{W, 1, "", 0xaa4c, 0x00939393, 0}, -{W, 1, "", 0xaa50, 0x00949494, 0}, -{W, 1, "", 0xaa54, 0x00959595, 0}, -{W, 1, "", 0xaa58, 0x00969696, 0}, -{W, 1, "", 0xaa5c, 0x00979797, 0}, -{W, 1, "", 0xaa60, 0x00989898, 0}, -{W, 1, "", 0xaa64, 0x00999999, 0}, -{W, 1, "", 0xaa68, 0x009a9a9a, 0}, -{W, 1, "", 0xaa6c, 0x009b9b9b, 0}, -{W, 1, "", 0xaa70, 0x009c9c9c, 0}, -{W, 1, "", 0xaa74, 0x009d9d9d, 0}, -{W, 1, "", 0xaa78, 0x009e9e9e, 0}, -{W, 1, "", 0xaa7c, 0x009f9f9f, 0}, -{W, 1, "", 0xaa80, 0x00a0a0a0, 0}, -{W, 1, "", 0xaa84, 0x00a1a1a1, 0}, -{W, 1, "", 0xaa88, 0x00a2a2a2, 0}, -{W, 1, "", 0xaa8c, 0x00a3a3a3, 0}, -{W, 1, "", 0xaa90, 0x00a4a4a4, 0}, -{W, 1, "", 0xaa94, 0x00a5a5a5, 0}, -{W, 1, "", 0xaa98, 0x00a6a6a6, 0}, -{W, 1, "", 0xaa9c, 0x00a7a7a7, 0}, -{W, 1, "", 0xaaa0, 0x00a8a8a8, 0}, -{W, 1, "", 0xaaa4, 0x00a9a9a9, 0}, -{W, 1, "", 0xaaa8, 0x00aaaaaa, 0}, -{W, 1, "", 0xaaac, 0x00ababab, 0}, -{W, 1, "", 0xaab0, 0x00acacac, 0}, -{W, 1, "", 0xaab4, 0x00adadad, 0}, -{W, 1, "", 0xaab8, 0x00aeaeae, 0}, -{W, 1, "", 0xaabc, 0x00afafaf, 0}, -{W, 1, "", 0xaac0, 0x00b0b0b0, 0}, -{W, 1, "", 0xaac4, 0x00b1b1b1, 0}, -{W, 1, "", 0xaac8, 0x00b2b2b2, 0}, -{W, 1, "", 0xaacc, 0x00b3b3b3, 0}, -{W, 1, "", 0xaad0, 0x00b4b4b4, 0}, -{W, 1, "", 0xaad4, 0x00b5b5b5, 0}, -{W, 1, "", 0xaad8, 0x00b6b6b6, 0}, -{W, 1, "", 0xaadc, 0x00b7b7b7, 0}, -{W, 1, "", 0xaae0, 0x00b8b8b8, 0}, -{W, 1, "", 0xaae4, 0x00b9b9b9, 0}, -{W, 1, "", 0xaae8, 0x00bababa, 0}, -{W, 1, "", 0xaaec, 0x00bbbbbb, 0}, -{W, 1, "", 0xaaf0, 0x00bcbcbc, 0}, -{W, 1, "", 0xaaf4, 0x00bdbdbd, 0}, -{W, 1, "", 0xaaf8, 0x00bebebe, 0}, -{W, 1, "", 0xaafc, 0x00bfbfbf, 0}, -{W, 1, "", 0xab00, 0x00c0c0c0, 0}, -{W, 1, "", 0xab04, 0x00c1c1c1, 0}, -{W, 1, "", 0xab08, 0x00c2c2c2, 0}, -{W, 1, "", 0xab0c, 0x00c3c3c3, 0}, -{W, 1, "", 0xab10, 0x00c4c4c4, 0}, -{W, 1, "", 0xab14, 0x00c5c5c5, 0}, -{W, 1, "", 0xab18, 0x00c6c6c6, 0}, -{W, 1, "", 0xab1c, 0x00c7c7c7, 0}, -{W, 1, "", 0xab20, 0x00c8c8c8, 0}, -{W, 1, "", 0xab24, 0x00c9c9c9, 0}, -{W, 1, "", 0xab28, 0x00cacaca, 0}, -{W, 1, "", 0xab2c, 0x00cbcbcb, 0}, -{W, 1, "", 0xab30, 0x00cccccc, 0}, -{W, 1, "", 0xab34, 0x00cdcdcd, 0}, -{W, 1, "", 0xab38, 0x00cecece, 0}, -{W, 1, "", 0xab3c, 0x00cfcfcf, 0}, -{W, 1, "", 0xab40, 0x00d0d0d0, 0}, -{W, 1, "", 0xab44, 0x00d1d1d1, 0}, -{W, 1, "", 0xab48, 0x00d2d2d2, 0}, -{W, 1, "", 0xab4c, 0x00d3d3d3, 0}, -{W, 1, "", 0xab50, 0x00d4d4d4, 0}, -{W, 1, "", 0xab54, 0x00d5d5d5, 0}, -{W, 1, "", 0xab58, 0x00d6d6d6, 0}, -{W, 1, "", 0xab5c, 0x00d7d7d7, 0}, -{W, 1, "", 0xab60, 0x00d8d8d8, 0}, -{W, 1, "", 0xab64, 0x00d9d9d9, 0}, -{W, 1, "", 0xab68, 0x00dadada, 0}, -{W, 1, "", 0xab6c, 0x00dbdbdb, 0}, -{W, 1, "", 0xab70, 0x00dcdcdc, 0}, -{W, 1, "", 0xab74, 0x00dddddd, 0}, -{W, 1, "", 0xab78, 0x00dedede, 0}, -{W, 1, "", 0xab7c, 0x00dfdfdf, 0}, -{W, 1, "", 0xab80, 0x00e0e0e0, 0}, -{W, 1, "", 0xab84, 0x00e1e1e1, 0}, -{W, 1, "", 0xab88, 0x00e2e2e2, 0}, -{W, 1, "", 0xab8c, 0x00e3e3e3, 0}, -{W, 1, "", 0xab90, 0x00e4e4e4, 0}, -{W, 1, "", 0xab94, 0x00e5e5e5, 0}, -{W, 1, "", 0xab98, 0x00e6e6e6, 0}, -{W, 1, "", 0xab9c, 0x00e7e7e7, 0}, -{W, 1, "", 0xaba0, 0x00e8e8e8, 0}, -{W, 1, "", 0xaba4, 0x00e9e9e9, 0}, -{W, 1, "", 0xaba8, 0x00eaeaea, 0}, -{W, 1, "", 0xabac, 0x00ebebeb, 0}, -{W, 1, "", 0xabb0, 0x00ececec, 0}, -{W, 1, "", 0xabb4, 0x00ededed, 0}, -{W, 1, "", 0xabb8, 0x00eeeeee, 0}, -{W, 1, "", 0xabbc, 0x00efefef, 0}, -{W, 1, "", 0xabc0, 0x00f0f0f0, 0}, -{W, 1, "", 0xabc4, 0x00f1f1f1, 0}, -{W, 1, "", 0xabc8, 0x00f2f2f2, 0}, -{W, 1, "", 0xabcc, 0x00f3f3f3, 0}, -{W, 1, "", 0xabd0, 0x00f4f4f4, 0}, -{W, 1, "", 0xabd4, 0x00f5f5f5, 0}, -{W, 1, "", 0xabd8, 0x00f6f6f6, 0}, -{W, 1, "", 0xabdc, 0x00f7f7f7, 0}, -{W, 1, "", 0xabe0, 0x00f8f8f8, 0}, -{W, 1, "", 0xabe4, 0x00f9f9f9, 0}, -{W, 1, "", 0xabe8, 0x00fafafa, 0}, -{W, 1, "", 0xabec, 0x00fbfbfb, 0}, -{W, 1, "", 0xabf0, 0x00fcfcfc, 0}, -{W, 1, "", 0xabf4, 0x00fdfdfd, 0}, -{W, 1, "", 0xabf8, 0x00fefefe, 0}, -{W, 1, "", 0xabfc, 0x00ffffff, 0}, -{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0}, -{W, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0}, +{W, 1, "", FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000, 0}, {W, 1, "", PFIT_PGM_RATIOS, 0x00000000, 0}, {W, 1, "", PFIT_CONTROL, (PFIT_PIPE_SHIFT & 0x8) | 0x00000008, 0}, -{R, 1, "", PP_CONTROL, 0xabcd0000, 0}, -{W, 1, "", PP_CONTROL, POWER_TARGET_ON | 0xabcd0001, 0}, -{R, 1, "", PP_STATUS, PP_READY | (PP_SEQUENCE_SHIFT & 0x8) | 0x4000000a, 0}, -{R, 1, "", PP_STATUS, PP_ON | PP_READY | PP_SEQUENCE_POWER_UP | (PP_SEQUENCE_SHIFT & 0x8) | 0xd000000a, 0}, -{R, 1, "", BLC_PWM_CTL, 0x00000000, 0}, {M, 1, "i915:fixme:max PWM is zero", 0x0, 0x0, 0}, {R, 1, "", BLC_PWM_CTL, 0x00000000, 0}, {W, 1, "", BLC_PWM_CTL, 0x00000002, 0}, -{R, 2, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x000c0000, 0}, -{R, 1, "", LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x000c0000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x80000000, 0}, -{W, 1, "", _PALETTE_B, 0x00000000, 0}, -{W, 1, "", _PALETTE_B+0x4, 0x00010101, 0}, -{W, 1, "", _PALETTE_B+0x8, 0x00020202, 0}, -{W, 1, "", _PALETTE_B+0xc, 0x00030303, 0}, -{W, 1, "", _PALETTE_B+0x10, 0x00040404, 0}, -{W, 1, "", _PALETTE_B+0x14, 0x00050505, 0}, -{W, 1, "", _PALETTE_B+0x18, 0x00060606, 0}, -{W, 1, "", _PALETTE_B+0x1c, 0x00070707, 0}, -{W, 1, "", _PALETTE_B+0x20, 0x00080808, 0}, -{W, 1, "", _PALETTE_B+0x24, 0x00090909, 0}, -{W, 1, "", _PALETTE_B+0x28, 0x000a0a0a, 0}, -{W, 1, "", _PALETTE_B+0x2c, 0x000b0b0b, 0}, -{W, 1, "", _PALETTE_B+0x30, 0x000c0c0c, 0}, -{W, 1, "", _PALETTE_B+0x34, 0x000d0d0d, 0}, -{W, 1, "", _PALETTE_B+0x38, 0x000e0e0e, 0}, -{W, 1, "", _PALETTE_B+0x3c, 0x000f0f0f, 0}, -{W, 1, "", _PALETTE_B+0x40, 0x00101010, 0}, -{W, 1, "", _PALETTE_B+0x44, 0x00111111, 0}, -{W, 1, "", _PALETTE_B+0x48, 0x00121212, 0}, -{W, 1, "", _PALETTE_B+0x4c, 0x00131313, 0}, -{W, 1, "", _PALETTE_B+0x50, 0x00141414, 0}, -{W, 1, "", _PALETTE_B+0x54, 0x00151515, 0}, -{W, 1, "", _PALETTE_B+0x58, 0x00161616, 0}, -{W, 1, "", _PALETTE_B+0x5c, 0x00171717, 0}, -{W, 1, "", _PALETTE_B+0x60, 0x00181818, 0}, -{W, 1, "", _PALETTE_B+0x64, 0x00191919, 0}, -{W, 1, "", _PALETTE_B+0x68, 0x001a1a1a, 0}, -{W, 1, "", _PALETTE_B+0x6c, 0x001b1b1b, 0}, -{W, 1, "", _PALETTE_B+0x70, 0x001c1c1c, 0}, -{W, 1, "", _PALETTE_B+0x74, 0x001d1d1d, 0}, -{W, 1, "", _PALETTE_B+0x78, 0x001e1e1e, 0}, -{W, 1, "", _PALETTE_B+0x7c, 0x001f1f1f, 0}, -{W, 1, "", 0xa880, 0x00202020, 0}, -{W, 1, "", 0xa884, 0x00212121, 0}, -{W, 1, "", 0xa888, 0x00222222, 0}, -{W, 1, "", 0xa88c, 0x00232323, 0}, -{W, 1, "", 0xa890, 0x00242424, 0}, -{W, 1, "", 0xa894, 0x00252525, 0}, -{W, 1, "", 0xa898, 0x00262626, 0}, -{W, 1, "", 0xa89c, 0x00272727, 0}, -{W, 1, "", 0xa8a0, 0x00282828, 0}, -{W, 1, "", 0xa8a4, 0x00292929, 0}, -{W, 1, "", 0xa8a8, 0x002a2a2a, 0}, -{W, 1, "", 0xa8ac, 0x002b2b2b, 0}, -{W, 1, "", 0xa8b0, 0x002c2c2c, 0}, -{W, 1, "", 0xa8b4, 0x002d2d2d, 0}, -{W, 1, "", 0xa8b8, 0x002e2e2e, 0}, -{W, 1, "", 0xa8bc, 0x002f2f2f, 0}, -{W, 1, "", 0xa8c0, 0x00303030, 0}, -{W, 1, "", 0xa8c4, 0x00313131, 0}, -{W, 1, "", 0xa8c8, 0x00323232, 0}, -{W, 1, "", 0xa8cc, 0x00333333, 0}, -{W, 1, "", 0xa8d0, 0x00343434, 0}, -{W, 1, "", 0xa8d4, 0x00353535, 0}, -{W, 1, "", 0xa8d8, 0x00363636, 0}, -{W, 1, "", 0xa8dc, 0x00373737, 0}, -{W, 1, "", 0xa8e0, 0x00383838, 0}, -{W, 1, "", 0xa8e4, 0x00393939, 0}, -{W, 1, "", 0xa8e8, 0x003a3a3a, 0}, -{W, 1, "", 0xa8ec, 0x003b3b3b, 0}, -{W, 1, "", 0xa8f0, 0x003c3c3c, 0}, -{W, 1, "", 0xa8f4, 0x003d3d3d, 0}, -{W, 1, "", 0xa8f8, 0x003e3e3e, 0}, -{W, 1, "", 0xa8fc, 0x003f3f3f, 0}, -{W, 1, "", 0xa900, 0x00404040, 0}, -{W, 1, "", 0xa904, 0x00414141, 0}, -{W, 1, "", 0xa908, 0x00424242, 0}, -{W, 1, "", 0xa90c, 0x00434343, 0}, -{W, 1, "", 0xa910, 0x00444444, 0}, -{W, 1, "", 0xa914, 0x00454545, 0}, -{W, 1, "", 0xa918, 0x00464646, 0}, -{W, 1, "", 0xa91c, 0x00474747, 0}, -{W, 1, "", 0xa920, 0x00484848, 0}, -{W, 1, "", 0xa924, 0x00494949, 0}, -{W, 1, "", 0xa928, 0x004a4a4a, 0}, -{W, 1, "", 0xa92c, 0x004b4b4b, 0}, -{W, 1, "", 0xa930, 0x004c4c4c, 0}, -{W, 1, "", 0xa934, 0x004d4d4d, 0}, -{W, 1, "", 0xa938, 0x004e4e4e, 0}, -{W, 1, "", 0xa93c, 0x004f4f4f, 0}, -{W, 1, "", 0xa940, 0x00505050, 0}, -{W, 1, "", 0xa944, 0x00515151, 0}, -{W, 1, "", 0xa948, 0x00525252, 0}, -{W, 1, "", 0xa94c, 0x00535353, 0}, -{W, 1, "", 0xa950, 0x00545454, 0}, -{W, 1, "", 0xa954, 0x00555555, 0}, -{W, 1, "", 0xa958, 0x00565656, 0}, -{W, 1, "", 0xa95c, 0x00575757, 0}, -{W, 1, "", 0xa960, 0x00585858, 0}, -{W, 1, "", 0xa964, 0x00595959, 0}, -{W, 1, "", 0xa968, 0x005a5a5a, 0}, -{W, 1, "", 0xa96c, 0x005b5b5b, 0}, -{W, 1, "", 0xa970, 0x005c5c5c, 0}, -{W, 1, "", 0xa974, 0x005d5d5d, 0}, -{W, 1, "", 0xa978, 0x005e5e5e, 0}, -{W, 1, "", 0xa97c, 0x005f5f5f, 0}, -{W, 1, "", 0xa980, 0x00606060, 0}, -{W, 1, "", 0xa984, 0x00616161, 0}, -{W, 1, "", 0xa988, 0x00626262, 0}, -{W, 1, "", 0xa98c, 0x00636363, 0}, -{W, 1, "", 0xa990, 0x00646464, 0}, -{W, 1, "", 0xa994, 0x00656565, 0}, -{W, 1, "", 0xa998, 0x00666666, 0}, -{W, 1, "", 0xa99c, 0x00676767, 0}, -{W, 1, "", 0xa9a0, 0x00686868, 0}, -{W, 1, "", 0xa9a4, 0x00696969, 0}, -{W, 1, "", 0xa9a8, 0x006a6a6a, 0}, -{W, 1, "", 0xa9ac, 0x006b6b6b, 0}, -{W, 1, "", 0xa9b0, 0x006c6c6c, 0}, -{W, 1, "", 0xa9b4, 0x006d6d6d, 0}, -{W, 1, "", 0xa9b8, 0x006e6e6e, 0}, -{W, 1, "", 0xa9bc, 0x006f6f6f, 0}, -{W, 1, "", 0xa9c0, 0x00707070, 0}, -{W, 1, "", 0xa9c4, 0x00717171, 0}, -{W, 1, "", 0xa9c8, 0x00727272, 0}, -{W, 1, "", 0xa9cc, 0x00737373, 0}, -{W, 1, "", 0xa9d0, 0x00747474, 0}, -{W, 1, "", 0xa9d4, 0x00757575, 0}, -{W, 1, "", 0xa9d8, 0x00767676, 0}, -{W, 1, "", 0xa9dc, 0x00777777, 0}, -{W, 1, "", 0xa9e0, 0x00787878, 0}, -{W, 1, "", 0xa9e4, 0x00797979, 0}, -{W, 1, "", 0xa9e8, 0x007a7a7a, 0}, -{W, 1, "", 0xa9ec, 0x007b7b7b, 0}, -{W, 1, "", 0xa9f0, 0x007c7c7c, 0}, -{W, 1, "", 0xa9f4, 0x007d7d7d, 0}, -{W, 1, "", 0xa9f8, 0x007e7e7e, 0}, -{W, 1, "", 0xa9fc, 0x007f7f7f, 0}, -{W, 1, "", 0xaa00, 0x00808080, 0}, -{W, 1, "", 0xaa04, 0x00818181, 0}, -{W, 1, "", 0xaa08, 0x00828282, 0}, -{W, 1, "", 0xaa0c, 0x00838383, 0}, -{W, 1, "", 0xaa10, 0x00848484, 0}, -{W, 1, "", 0xaa14, 0x00858585, 0}, -{W, 1, "", 0xaa18, 0x00868686, 0}, -{W, 1, "", 0xaa1c, 0x00878787, 0}, -{W, 1, "", 0xaa20, 0x00888888, 0}, -{W, 1, "", 0xaa24, 0x00898989, 0}, -{W, 1, "", 0xaa28, 0x008a8a8a, 0}, -{W, 1, "", 0xaa2c, 0x008b8b8b, 0}, -{W, 1, "", 0xaa30, 0x008c8c8c, 0}, -{W, 1, "", 0xaa34, 0x008d8d8d, 0}, -{W, 1, "", 0xaa38, 0x008e8e8e, 0}, -{W, 1, "", 0xaa3c, 0x008f8f8f, 0}, -{W, 1, "", 0xaa40, 0x00909090, 0}, -{W, 1, "", 0xaa44, 0x00919191, 0}, -{W, 1, "", 0xaa48, 0x00929292, 0}, -{W, 1, "", 0xaa4c, 0x00939393, 0}, -{W, 1, "", 0xaa50, 0x00949494, 0}, -{W, 1, "", 0xaa54, 0x00959595, 0}, -{W, 1, "", 0xaa58, 0x00969696, 0}, -{W, 1, "", 0xaa5c, 0x00979797, 0}, -{W, 1, "", 0xaa60, 0x00989898, 0}, -{W, 1, "", 0xaa64, 0x00999999, 0}, -{W, 1, "", 0xaa68, 0x009a9a9a, 0}, -{W, 1, "", 0xaa6c, 0x009b9b9b, 0}, -{W, 1, "", 0xaa70, 0x009c9c9c, 0}, -{W, 1, "", 0xaa74, 0x009d9d9d, 0}, -{W, 1, "", 0xaa78, 0x009e9e9e, 0}, -{W, 1, "", 0xaa7c, 0x009f9f9f, 0}, -{W, 1, "", 0xaa80, 0x00a0a0a0, 0}, -{W, 1, "", 0xaa84, 0x00a1a1a1, 0}, -{W, 1, "", 0xaa88, 0x00a2a2a2, 0}, -{W, 1, "", 0xaa8c, 0x00a3a3a3, 0}, -{W, 1, "", 0xaa90, 0x00a4a4a4, 0}, -{W, 1, "", 0xaa94, 0x00a5a5a5, 0}, -{W, 1, "", 0xaa98, 0x00a6a6a6, 0}, -{W, 1, "", 0xaa9c, 0x00a7a7a7, 0}, -{W, 1, "", 0xaaa0, 0x00a8a8a8, 0}, -{W, 1, "", 0xaaa4, 0x00a9a9a9, 0}, -{W, 1, "", 0xaaa8, 0x00aaaaaa, 0}, -{W, 1, "", 0xaaac, 0x00ababab, 0}, -{W, 1, "", 0xaab0, 0x00acacac, 0}, -{W, 1, "", 0xaab4, 0x00adadad, 0}, -{W, 1, "", 0xaab8, 0x00aeaeae, 0}, -{W, 1, "", 0xaabc, 0x00afafaf, 0}, -{W, 1, "", 0xaac0, 0x00b0b0b0, 0}, -{W, 1, "", 0xaac4, 0x00b1b1b1, 0}, -{W, 1, "", 0xaac8, 0x00b2b2b2, 0}, -{W, 1, "", 0xaacc, 0x00b3b3b3, 0}, -{W, 1, "", 0xaad0, 0x00b4b4b4, 0}, -{W, 1, "", 0xaad4, 0x00b5b5b5, 0}, -{W, 1, "", 0xaad8, 0x00b6b6b6, 0}, -{W, 1, "", 0xaadc, 0x00b7b7b7, 0}, -{W, 1, "", 0xaae0, 0x00b8b8b8, 0}, -{W, 1, "", 0xaae4, 0x00b9b9b9, 0}, -{W, 1, "", 0xaae8, 0x00bababa, 0}, -{W, 1, "", 0xaaec, 0x00bbbbbb, 0}, -{W, 1, "", 0xaaf0, 0x00bcbcbc, 0}, -{W, 1, "", 0xaaf4, 0x00bdbdbd, 0}, -{W, 1, "", 0xaaf8, 0x00bebebe, 0}, -{W, 1, "", 0xaafc, 0x00bfbfbf, 0}, -{W, 1, "", 0xab00, 0x00c0c0c0, 0}, -{W, 1, "", 0xab04, 0x00c1c1c1, 0}, -{W, 1, "", 0xab08, 0x00c2c2c2, 0}, -{W, 1, "", 0xab0c, 0x00c3c3c3, 0}, -{W, 1, "", 0xab10, 0x00c4c4c4, 0}, -{W, 1, "", 0xab14, 0x00c5c5c5, 0}, -{W, 1, "", 0xab18, 0x00c6c6c6, 0}, -{W, 1, "", 0xab1c, 0x00c7c7c7, 0}, -{W, 1, "", 0xab20, 0x00c8c8c8, 0}, -{W, 1, "", 0xab24, 0x00c9c9c9, 0}, -{W, 1, "", 0xab28, 0x00cacaca, 0}, -{W, 1, "", 0xab2c, 0x00cbcbcb, 0}, -{W, 1, "", 0xab30, 0x00cccccc, 0}, -{W, 1, "", 0xab34, 0x00cdcdcd, 0}, -{W, 1, "", 0xab38, 0x00cecece, 0}, -{W, 1, "", 0xab3c, 0x00cfcfcf, 0}, -{W, 1, "", 0xab40, 0x00d0d0d0, 0}, -{W, 1, "", 0xab44, 0x00d1d1d1, 0}, -{W, 1, "", 0xab48, 0x00d2d2d2, 0}, -{W, 1, "", 0xab4c, 0x00d3d3d3, 0}, -{W, 1, "", 0xab50, 0x00d4d4d4, 0}, -{W, 1, "", 0xab54, 0x00d5d5d5, 0}, -{W, 1, "", 0xab58, 0x00d6d6d6, 0}, -{W, 1, "", 0xab5c, 0x00d7d7d7, 0}, -{W, 1, "", 0xab60, 0x00d8d8d8, 0}, -{W, 1, "", 0xab64, 0x00d9d9d9, 0}, -{W, 1, "", 0xab68, 0x00dadada, 0}, -{W, 1, "", 0xab6c, 0x00dbdbdb, 0}, -{W, 1, "", 0xab70, 0x00dcdcdc, 0}, -{W, 1, "", 0xab74, 0x00dddddd, 0}, -{W, 1, "", 0xab78, 0x00dedede, 0}, -{W, 1, "", 0xab7c, 0x00dfdfdf, 0}, -{W, 1, "", 0xab80, 0x00e0e0e0, 0}, -{W, 1, "", 0xab84, 0x00e1e1e1, 0}, -{W, 1, "", 0xab88, 0x00e2e2e2, 0}, -{W, 1, "", 0xab8c, 0x00e3e3e3, 0}, -{W, 1, "", 0xab90, 0x00e4e4e4, 0}, -{W, 1, "", 0xab94, 0x00e5e5e5, 0}, -{W, 1, "", 0xab98, 0x00e6e6e6, 0}, -{W, 1, "", 0xab9c, 0x00e7e7e7, 0}, -{W, 1, "", 0xaba0, 0x00e8e8e8, 0}, -{W, 1, "", 0xaba4, 0x00e9e9e9, 0}, -{W, 1, "", 0xaba8, 0x00eaeaea, 0}, -{W, 1, "", 0xabac, 0x00ebebeb, 0}, -{W, 1, "", 0xabb0, 0x00ececec, 0}, -{W, 1, "", 0xabb4, 0x00ededed, 0}, -{W, 1, "", 0xabb8, 0x00eeeeee, 0}, -{W, 1, "", 0xabbc, 0x00efefef, 0}, -{W, 1, "", 0xabc0, 0x00f0f0f0, 0}, -{W, 1, "", 0xabc4, 0x00f1f1f1, 0}, -{W, 1, "", 0xabc8, 0x00f2f2f2, 0}, -{W, 1, "", 0xabcc, 0x00f3f3f3, 0}, -{W, 1, "", 0xabd0, 0x00f4f4f4, 0}, -{W, 1, "", 0xabd4, 0x00f5f5f5, 0}, -{W, 1, "", 0xabd8, 0x00f6f6f6, 0}, -{W, 1, "", 0xabdc, 0x00f7f7f7, 0}, -{W, 1, "", 0xabe0, 0x00f8f8f8, 0}, -{W, 1, "", 0xabe4, 0x00f9f9f9, 0}, -{W, 1, "", 0xabe8, 0x00fafafa, 0}, -{W, 1, "", 0xabec, 0x00fbfbfb, 0}, -{W, 1, "", 0xabf0, 0x00fcfcfc, 0}, -{W, 1, "", 0xabf4, 0x00fdfdfd, 0}, -{W, 1, "", 0xabf8, 0x00fefefe, 0}, -{W, 1, "", 0xabfc, 0x00ffffff, 0}, -{W, 1, "", _PALETTE_B, 0x00000000, 0}, -{W, 1, "", _PALETTE_B+0x4, 0x00010101, 0}, -{W, 1, "", _PALETTE_B+0x8, 0x00020202, 0}, -{W, 1, "", _PALETTE_B+0xc, 0x00030303, 0}, -{W, 1, "", _PALETTE_B+0x10, 0x00040404, 0}, -{W, 1, "", _PALETTE_B+0x14, 0x00050505, 0}, -{W, 1, "", _PALETTE_B+0x18, 0x00060606, 0}, -{W, 1, "", _PALETTE_B+0x1c, 0x00070707, 0}, -{W, 1, "", _PALETTE_B+0x20, 0x00080808, 0}, -{W, 1, "", _PALETTE_B+0x24, 0x00090909, 0}, -{W, 1, "", _PALETTE_B+0x28, 0x000a0a0a, 0}, -{W, 1, "", _PALETTE_B+0x2c, 0x000b0b0b, 0}, -{W, 1, "", _PALETTE_B+0x30, 0x000c0c0c, 0}, -{W, 1, "", _PALETTE_B+0x34, 0x000d0d0d, 0}, -{W, 1, "", _PALETTE_B+0x38, 0x000e0e0e, 0}, -{W, 1, "", _PALETTE_B+0x3c, 0x000f0f0f, 0}, -{W, 1, "", _PALETTE_B+0x40, 0x00101010, 0}, -{W, 1, "", _PALETTE_B+0x44, 0x00111111, 0}, -{W, 1, "", _PALETTE_B+0x48, 0x00121212, 0}, -{W, 1, "", _PALETTE_B+0x4c, 0x00131313, 0}, -{W, 1, "", _PALETTE_B+0x50, 0x00141414, 0}, -{W, 1, "", _PALETTE_B+0x54, 0x00151515, 0}, -{W, 1, "", _PALETTE_B+0x58, 0x00161616, 0}, -{W, 1, "", _PALETTE_B+0x5c, 0x00171717, 0}, -{W, 1, "", _PALETTE_B+0x60, 0x00181818, 0}, -{W, 1, "", _PALETTE_B+0x64, 0x00191919, 0}, -{W, 1, "", _PALETTE_B+0x68, 0x001a1a1a, 0}, -{W, 1, "", _PALETTE_B+0x6c, 0x001b1b1b, 0}, -{W, 1, "", _PALETTE_B+0x70, 0x001c1c1c, 0}, -{W, 1, "", _PALETTE_B+0x74, 0x001d1d1d, 0}, -{W, 1, "", _PALETTE_B+0x78, 0x001e1e1e, 0}, -{W, 1, "", _PALETTE_B+0x7c, 0x001f1f1f, 0}, -{W, 1, "", 0xa880, 0x00202020, 0}, -{W, 1, "", 0xa884, 0x00212121, 0}, -{W, 1, "", 0xa888, 0x00222222, 0}, -{W, 1, "", 0xa88c, 0x00232323, 0}, -{W, 1, "", 0xa890, 0x00242424, 0}, -{W, 1, "", 0xa894, 0x00252525, 0}, -{W, 1, "", 0xa898, 0x00262626, 0}, -{W, 1, "", 0xa89c, 0x00272727, 0}, -{W, 1, "", 0xa8a0, 0x00282828, 0}, -{W, 1, "", 0xa8a4, 0x00292929, 0}, -{W, 1, "", 0xa8a8, 0x002a2a2a, 0}, -{W, 1, "", 0xa8ac, 0x002b2b2b, 0}, -{W, 1, "", 0xa8b0, 0x002c2c2c, 0}, -{W, 1, "", 0xa8b4, 0x002d2d2d, 0}, -{W, 1, "", 0xa8b8, 0x002e2e2e, 0}, -{W, 1, "", 0xa8bc, 0x002f2f2f, 0}, -{W, 1, "", 0xa8c0, 0x00303030, 0}, -{W, 1, "", 0xa8c4, 0x00313131, 0}, -{W, 1, "", 0xa8c8, 0x00323232, 0}, -{W, 1, "", 0xa8cc, 0x00333333, 0}, -{W, 1, "", 0xa8d0, 0x00343434, 0}, -{W, 1, "", 0xa8d4, 0x00353535, 0}, -{W, 1, "", 0xa8d8, 0x00363636, 0}, -{W, 1, "", 0xa8dc, 0x00373737, 0}, -{W, 1, "", 0xa8e0, 0x00383838, 0}, -{W, 1, "", 0xa8e4, 0x00393939, 0}, -{W, 1, "", 0xa8e8, 0x003a3a3a, 0}, -{W, 1, "", 0xa8ec, 0x003b3b3b, 0}, -{W, 1, "", 0xa8f0, 0x003c3c3c, 0}, -{W, 1, "", 0xa8f4, 0x003d3d3d, 0}, -{W, 1, "", 0xa8f8, 0x003e3e3e, 0}, -{W, 1, "", 0xa8fc, 0x003f3f3f, 0}, -{W, 1, "", 0xa900, 0x00404040, 0}, -{W, 1, "", 0xa904, 0x00414141, 0}, -{W, 1, "", 0xa908, 0x00424242, 0}, -{W, 1, "", 0xa90c, 0x00434343, 0}, -{W, 1, "", 0xa910, 0x00444444, 0}, -{W, 1, "", 0xa914, 0x00454545, 0}, -{W, 1, "", 0xa918, 0x00464646, 0}, -{W, 1, "", 0xa91c, 0x00474747, 0}, -{W, 1, "", 0xa920, 0x00484848, 0}, -{W, 1, "", 0xa924, 0x00494949, 0}, -{W, 1, "", 0xa928, 0x004a4a4a, 0}, -{W, 1, "", 0xa92c, 0x004b4b4b, 0}, -{W, 1, "", 0xa930, 0x004c4c4c, 0}, -{W, 1, "", 0xa934, 0x004d4d4d, 0}, -{W, 1, "", 0xa938, 0x004e4e4e, 0}, -{W, 1, "", 0xa93c, 0x004f4f4f, 0}, -{W, 1, "", 0xa940, 0x00505050, 0}, -{W, 1, "", 0xa944, 0x00515151, 0}, -{W, 1, "", 0xa948, 0x00525252, 0}, -{W, 1, "", 0xa94c, 0x00535353, 0}, -{W, 1, "", 0xa950, 0x00545454, 0}, -{W, 1, "", 0xa954, 0x00555555, 0}, -{W, 1, "", 0xa958, 0x00565656, 0}, -{W, 1, "", 0xa95c, 0x00575757, 0}, -{W, 1, "", 0xa960, 0x00585858, 0}, -{W, 1, "", 0xa964, 0x00595959, 0}, -{W, 1, "", 0xa968, 0x005a5a5a, 0}, -{W, 1, "", 0xa96c, 0x005b5b5b, 0}, -{W, 1, "", 0xa970, 0x005c5c5c, 0}, -{W, 1, "", 0xa974, 0x005d5d5d, 0}, -{W, 1, "", 0xa978, 0x005e5e5e, 0}, -{W, 1, "", 0xa97c, 0x005f5f5f, 0}, -{W, 1, "", 0xa980, 0x00606060, 0}, -{W, 1, "", 0xa984, 0x00616161, 0}, -{W, 1, "", 0xa988, 0x00626262, 0}, -{W, 1, "", 0xa98c, 0x00636363, 0}, -{W, 1, "", 0xa990, 0x00646464, 0}, -{W, 1, "", 0xa994, 0x00656565, 0}, -{W, 1, "", 0xa998, 0x00666666, 0}, -{W, 1, "", 0xa99c, 0x00676767, 0}, -{W, 1, "", 0xa9a0, 0x00686868, 0}, -{W, 1, "", 0xa9a4, 0x00696969, 0}, -{W, 1, "", 0xa9a8, 0x006a6a6a, 0}, -{W, 1, "", 0xa9ac, 0x006b6b6b, 0}, -{W, 1, "", 0xa9b0, 0x006c6c6c, 0}, -{W, 1, "", 0xa9b4, 0x006d6d6d, 0}, -{W, 1, "", 0xa9b8, 0x006e6e6e, 0}, -{W, 1, "", 0xa9bc, 0x006f6f6f, 0}, -{W, 1, "", 0xa9c0, 0x00707070, 0}, -{W, 1, "", 0xa9c4, 0x00717171, 0}, -{W, 1, "", 0xa9c8, 0x00727272, 0}, -{W, 1, "", 0xa9cc, 0x00737373, 0}, -{W, 1, "", 0xa9d0, 0x00747474, 0}, -{W, 1, "", 0xa9d4, 0x00757575, 0}, -{W, 1, "", 0xa9d8, 0x00767676, 0}, -{W, 1, "", 0xa9dc, 0x00777777, 0}, -{W, 1, "", 0xa9e0, 0x00787878, 0}, -{W, 1, "", 0xa9e4, 0x00797979, 0}, -{W, 1, "", 0xa9e8, 0x007a7a7a, 0}, -{W, 1, "", 0xa9ec, 0x007b7b7b, 0}, -{W, 1, "", 0xa9f0, 0x007c7c7c, 0}, -{W, 1, "", 0xa9f4, 0x007d7d7d, 0}, -{W, 1, "", 0xa9f8, 0x007e7e7e, 0}, -{W, 1, "", 0xa9fc, 0x007f7f7f, 0}, -{W, 1, "", 0xaa00, 0x00808080, 0}, -{W, 1, "", 0xaa04, 0x00818181, 0}, -{W, 1, "", 0xaa08, 0x00828282, 0}, -{W, 1, "", 0xaa0c, 0x00838383, 0}, -{W, 1, "", 0xaa10, 0x00848484, 0}, -{W, 1, "", 0xaa14, 0x00858585, 0}, -{W, 1, "", 0xaa18, 0x00868686, 0}, -{W, 1, "", 0xaa1c, 0x00878787, 0}, -{W, 1, "", 0xaa20, 0x00888888, 0}, -{W, 1, "", 0xaa24, 0x00898989, 0}, -{W, 1, "", 0xaa28, 0x008a8a8a, 0}, -{W, 1, "", 0xaa2c, 0x008b8b8b, 0}, -{W, 1, "", 0xaa30, 0x008c8c8c, 0}, -{W, 1, "", 0xaa34, 0x008d8d8d, 0}, -{W, 1, "", 0xaa38, 0x008e8e8e, 0}, -{W, 1, "", 0xaa3c, 0x008f8f8f, 0}, -{W, 1, "", 0xaa40, 0x00909090, 0}, -{W, 1, "", 0xaa44, 0x00919191, 0}, -{W, 1, "", 0xaa48, 0x00929292, 0}, -{W, 1, "", 0xaa4c, 0x00939393, 0}, -{W, 1, "", 0xaa50, 0x00949494, 0}, -{W, 1, "", 0xaa54, 0x00959595, 0}, -{W, 1, "", 0xaa58, 0x00969696, 0}, -{W, 1, "", 0xaa5c, 0x00979797, 0}, -{W, 1, "", 0xaa60, 0x00989898, 0}, -{W, 1, "", 0xaa64, 0x00999999, 0}, -{W, 1, "", 0xaa68, 0x009a9a9a, 0}, -{W, 1, "", 0xaa6c, 0x009b9b9b, 0}, -{W, 1, "", 0xaa70, 0x009c9c9c, 0}, -{W, 1, "", 0xaa74, 0x009d9d9d, 0}, -{W, 1, "", 0xaa78, 0x009e9e9e, 0}, -{W, 1, "", 0xaa7c, 0x009f9f9f, 0}, -{W, 1, "", 0xaa80, 0x00a0a0a0, 0}, -{W, 1, "", 0xaa84, 0x00a1a1a1, 0}, -{W, 1, "", 0xaa88, 0x00a2a2a2, 0}, -{W, 1, "", 0xaa8c, 0x00a3a3a3, 0}, -{W, 1, "", 0xaa90, 0x00a4a4a4, 0}, -{W, 1, "", 0xaa94, 0x00a5a5a5, 0}, -{W, 1, "", 0xaa98, 0x00a6a6a6, 0}, -{W, 1, "", 0xaa9c, 0x00a7a7a7, 0}, -{W, 1, "", 0xaaa0, 0x00a8a8a8, 0}, -{W, 1, "", 0xaaa4, 0x00a9a9a9, 0}, -{W, 1, "", 0xaaa8, 0x00aaaaaa, 0}, -{W, 1, "", 0xaaac, 0x00ababab, 0}, -{W, 1, "", 0xaab0, 0x00acacac, 0}, -{W, 1, "", 0xaab4, 0x00adadad, 0}, -{W, 1, "", 0xaab8, 0x00aeaeae, 0}, -{W, 1, "", 0xaabc, 0x00afafaf, 0}, -{W, 1, "", 0xaac0, 0x00b0b0b0, 0}, -{W, 1, "", 0xaac4, 0x00b1b1b1, 0}, -{W, 1, "", 0xaac8, 0x00b2b2b2, 0}, -{W, 1, "", 0xaacc, 0x00b3b3b3, 0}, -{W, 1, "", 0xaad0, 0x00b4b4b4, 0}, -{W, 1, "", 0xaad4, 0x00b5b5b5, 0}, -{W, 1, "", 0xaad8, 0x00b6b6b6, 0}, -{W, 1, "", 0xaadc, 0x00b7b7b7, 0}, -{W, 1, "", 0xaae0, 0x00b8b8b8, 0}, -{W, 1, "", 0xaae4, 0x00b9b9b9, 0}, -{W, 1, "", 0xaae8, 0x00bababa, 0}, -{W, 1, "", 0xaaec, 0x00bbbbbb, 0}, -{W, 1, "", 0xaaf0, 0x00bcbcbc, 0}, -{W, 1, "", 0xaaf4, 0x00bdbdbd, 0}, -{W, 1, "", 0xaaf8, 0x00bebebe, 0}, -{W, 1, "", 0xaafc, 0x00bfbfbf, 0}, -{W, 1, "", 0xab00, 0x00c0c0c0, 0}, -{W, 1, "", 0xab04, 0x00c1c1c1, 0}, -{W, 1, "", 0xab08, 0x00c2c2c2, 0}, -{W, 1, "", 0xab0c, 0x00c3c3c3, 0}, -{W, 1, "", 0xab10, 0x00c4c4c4, 0}, -{W, 1, "", 0xab14, 0x00c5c5c5, 0}, -{W, 1, "", 0xab18, 0x00c6c6c6, 0}, -{W, 1, "", 0xab1c, 0x00c7c7c7, 0}, -{W, 1, "", 0xab20, 0x00c8c8c8, 0}, -{W, 1, "", 0xab24, 0x00c9c9c9, 0}, -{W, 1, "", 0xab28, 0x00cacaca, 0}, -{W, 1, "", 0xab2c, 0x00cbcbcb, 0}, -{W, 1, "", 0xab30, 0x00cccccc, 0}, -{W, 1, "", 0xab34, 0x00cdcdcd, 0}, -{W, 1, "", 0xab38, 0x00cecece, 0}, -{W, 1, "", 0xab3c, 0x00cfcfcf, 0}, -{W, 1, "", 0xab40, 0x00d0d0d0, 0}, -{W, 1, "", 0xab44, 0x00d1d1d1, 0}, -{W, 1, "", 0xab48, 0x00d2d2d2, 0}, -{W, 1, "", 0xab4c, 0x00d3d3d3, 0}, -{W, 1, "", 0xab50, 0x00d4d4d4, 0}, -{W, 1, "", 0xab54, 0x00d5d5d5, 0}, -{W, 1, "", 0xab58, 0x00d6d6d6, 0}, -{W, 1, "", 0xab5c, 0x00d7d7d7, 0}, -{W, 1, "", 0xab60, 0x00d8d8d8, 0}, -{W, 1, "", 0xab64, 0x00d9d9d9, 0}, -{W, 1, "", 0xab68, 0x00dadada, 0}, -{W, 1, "", 0xab6c, 0x00dbdbdb, 0}, -{W, 1, "", 0xab70, 0x00dcdcdc, 0}, -{W, 1, "", 0xab74, 0x00dddddd, 0}, -{W, 1, "", 0xab78, 0x00dedede, 0}, -{W, 1, "", 0xab7c, 0x00dfdfdf, 0}, -{W, 1, "", 0xab80, 0x00e0e0e0, 0}, -{W, 1, "", 0xab84, 0x00e1e1e1, 0}, -{W, 1, "", 0xab88, 0x00e2e2e2, 0}, -{W, 1, "", 0xab8c, 0x00e3e3e3, 0}, -{W, 1, "", 0xab90, 0x00e4e4e4, 0}, -{W, 1, "", 0xab94, 0x00e5e5e5, 0}, -{W, 1, "", 0xab98, 0x00e6e6e6, 0}, -{W, 1, "", 0xab9c, 0x00e7e7e7, 0}, -{W, 1, "", 0xaba0, 0x00e8e8e8, 0}, -{W, 1, "", 0xaba4, 0x00e9e9e9, 0}, -{W, 1, "", 0xaba8, 0x00eaeaea, 0}, -{W, 1, "", 0xabac, 0x00ebebeb, 0}, -{W, 1, "", 0xabb0, 0x00ececec, 0}, -{W, 1, "", 0xabb4, 0x00ededed, 0}, -{W, 1, "", 0xabb8, 0x00eeeeee, 0}, -{W, 1, "", 0xabbc, 0x00efefef, 0}, -{W, 1, "", 0xabc0, 0x00f0f0f0, 0}, -{W, 1, "", 0xabc4, 0x00f1f1f1, 0}, -{W, 1, "", 0xabc8, 0x00f2f2f2, 0}, -{W, 1, "", 0xabcc, 0x00f3f3f3, 0}, -{W, 1, "", 0xabd0, 0x00f4f4f4, 0}, -{W, 1, "", 0xabd4, 0x00f5f5f5, 0}, -{W, 1, "", 0xabd8, 0x00f6f6f6, 0}, -{W, 1, "", 0xabdc, 0x00f7f7f7, 0}, -{W, 1, "", 0xabe0, 0x00f8f8f8, 0}, -{W, 1, "", 0xabe4, 0x00f9f9f9, 0}, -{W, 1, "", 0xabe8, 0x00fafafa, 0}, -{W, 1, "", 0xabec, 0x00fbfbfb, 0}, -{W, 1, "", 0xabf0, 0x00fcfcfc, 0}, -{W, 1, "", 0xabf4, 0x00fdfdfd, 0}, -{W, 1, "", 0xabf8, 0x00fefefe, 0}, -{W, 1, "", 0xabfc, 0x00ffffff, 0}, {M, 1, "Console:switching to colour frame buffer device 128x48", 0x0, 0x0, 0}, -{W, 1, "", _PALETTE_B, 0x00000000, 0}, -{W, 1, "", _PALETTE_B+0x4, 0x00010101, 0}, -{W, 1, "", _PALETTE_B+0x8, 0x00020202, 0}, -{W, 1, "", _PALETTE_B+0xc, 0x00030303, 0}, -{W, 1, "", _PALETTE_B+0x10, 0x00040404, 0}, -{W, 1, "", _PALETTE_B+0x14, 0x00050505, 0}, -{W, 1, "", _PALETTE_B+0x18, 0x00060606, 0}, -{W, 1, "", _PALETTE_B+0x1c, 0x00070707, 0}, -{W, 1, "", _PALETTE_B+0x20, 0x00080808, 0}, -{W, 1, "", _PALETTE_B+0x24, 0x00090909, 0}, -{W, 1, "", _PALETTE_B+0x28, 0x000a0a0a, 0}, -{W, 1, "", _PALETTE_B+0x2c, 0x000b0b0b, 0}, -{W, 1, "", _PALETTE_B+0x30, 0x000c0c0c, 0}, -{W, 1, "", _PALETTE_B+0x34, 0x000d0d0d, 0}, -{W, 1, "", _PALETTE_B+0x38, 0x000e0e0e, 0}, -{W, 1, "", _PALETTE_B+0x3c, 0x000f0f0f, 0}, -{W, 1, "", _PALETTE_B+0x40, 0x00101010, 0}, -{W, 1, "", _PALETTE_B+0x44, 0x00111111, 0}, -{W, 1, "", _PALETTE_B+0x48, 0x00121212, 0}, -{W, 1, "", _PALETTE_B+0x4c, 0x00131313, 0}, -{W, 1, "", _PALETTE_B+0x50, 0x00141414, 0}, -{W, 1, "", _PALETTE_B+0x54, 0x00151515, 0}, -{W, 1, "", _PALETTE_B+0x58, 0x00161616, 0}, -{W, 1, "", _PALETTE_B+0x5c, 0x00171717, 0}, -{W, 1, "", _PALETTE_B+0x60, 0x00181818, 0}, -{W, 1, "", _PALETTE_B+0x64, 0x00191919, 0}, -{W, 1, "", _PALETTE_B+0x68, 0x001a1a1a, 0}, -{W, 1, "", _PALETTE_B+0x6c, 0x001b1b1b, 0}, -{W, 1, "", _PALETTE_B+0x70, 0x001c1c1c, 0}, -{W, 1, "", _PALETTE_B+0x74, 0x001d1d1d, 0}, -{W, 1, "", _PALETTE_B+0x78, 0x001e1e1e, 0}, -{W, 1, "", _PALETTE_B+0x7c, 0x001f1f1f, 0}, -{W, 1, "", 0xa880, 0x00202020, 0}, -{W, 1, "", 0xa884, 0x00212121, 0}, -{W, 1, "", 0xa888, 0x00222222, 0}, -{W, 1, "", 0xa88c, 0x00232323, 0}, -{W, 1, "", 0xa890, 0x00242424, 0}, -{W, 1, "", 0xa894, 0x00252525, 0}, -{W, 1, "", 0xa898, 0x00262626, 0}, -{W, 1, "", 0xa89c, 0x00272727, 0}, -{W, 1, "", 0xa8a0, 0x00282828, 0}, -{W, 1, "", 0xa8a4, 0x00292929, 0}, -{W, 1, "", 0xa8a8, 0x002a2a2a, 0}, -{W, 1, "", 0xa8ac, 0x002b2b2b, 0}, -{W, 1, "", 0xa8b0, 0x002c2c2c, 0}, -{W, 1, "", 0xa8b4, 0x002d2d2d, 0}, -{W, 1, "", 0xa8b8, 0x002e2e2e, 0}, -{W, 1, "", 0xa8bc, 0x002f2f2f, 0}, -{W, 1, "", 0xa8c0, 0x00303030, 0}, -{W, 1, "", 0xa8c4, 0x00313131, 0}, -{W, 1, "", 0xa8c8, 0x00323232, 0}, -{W, 1, "", 0xa8cc, 0x00333333, 0}, -{W, 1, "", 0xa8d0, 0x00343434, 0}, -{W, 1, "", 0xa8d4, 0x00353535, 0}, -{W, 1, "", 0xa8d8, 0x00363636, 0}, -{W, 1, "", 0xa8dc, 0x00373737, 0}, -{W, 1, "", 0xa8e0, 0x00383838, 0}, -{W, 1, "", 0xa8e4, 0x00393939, 0}, -{W, 1, "", 0xa8e8, 0x003a3a3a, 0}, -{W, 1, "", 0xa8ec, 0x003b3b3b, 0}, -{W, 1, "", 0xa8f0, 0x003c3c3c, 0}, -{W, 1, "", 0xa8f4, 0x003d3d3d, 0}, -{W, 1, "", 0xa8f8, 0x003e3e3e, 0}, -{W, 1, "", 0xa8fc, 0x003f3f3f, 0}, -{W, 1, "", 0xa900, 0x00404040, 0}, -{W, 1, "", 0xa904, 0x00414141, 0}, -{W, 1, "", 0xa908, 0x00424242, 0}, -{W, 1, "", 0xa90c, 0x00434343, 0}, -{W, 1, "", 0xa910, 0x00444444, 0}, -{W, 1, "", 0xa914, 0x00454545, 0}, -{W, 1, "", 0xa918, 0x00464646, 0}, -{W, 1, "", 0xa91c, 0x00474747, 0}, -{W, 1, "", 0xa920, 0x00484848, 0}, -{W, 1, "", 0xa924, 0x00494949, 0}, -{W, 1, "", 0xa928, 0x004a4a4a, 0}, -{W, 1, "", 0xa92c, 0x004b4b4b, 0}, -{W, 1, "", 0xa930, 0x004c4c4c, 0}, -{W, 1, "", 0xa934, 0x004d4d4d, 0}, -{W, 1, "", 0xa938, 0x004e4e4e, 0}, -{W, 1, "", 0xa93c, 0x004f4f4f, 0}, -{W, 1, "", 0xa940, 0x00505050, 0}, -{W, 1, "", 0xa944, 0x00515151, 0}, -{W, 1, "", 0xa948, 0x00525252, 0}, -{W, 1, "", 0xa94c, 0x00535353, 0}, -{W, 1, "", 0xa950, 0x00545454, 0}, -{W, 1, "", 0xa954, 0x00555555, 0}, -{W, 1, "", 0xa958, 0x00565656, 0}, -{W, 1, "", 0xa95c, 0x00575757, 0}, -{W, 1, "", 0xa960, 0x00585858, 0}, -{W, 1, "", 0xa964, 0x00595959, 0}, -{W, 1, "", 0xa968, 0x005a5a5a, 0}, -{W, 1, "", 0xa96c, 0x005b5b5b, 0}, -{W, 1, "", 0xa970, 0x005c5c5c, 0}, -{W, 1, "", 0xa974, 0x005d5d5d, 0}, -{W, 1, "", 0xa978, 0x005e5e5e, 0}, -{W, 1, "", 0xa97c, 0x005f5f5f, 0}, -{W, 1, "", 0xa980, 0x00606060, 0}, -{W, 1, "", 0xa984, 0x00616161, 0}, -{W, 1, "", 0xa988, 0x00626262, 0}, -{W, 1, "", 0xa98c, 0x00636363, 0}, -{W, 1, "", 0xa990, 0x00646464, 0}, -{W, 1, "", 0xa994, 0x00656565, 0}, -{W, 1, "", 0xa998, 0x00666666, 0}, -{W, 1, "", 0xa99c, 0x00676767, 0}, -{W, 1, "", 0xa9a0, 0x00686868, 0}, -{W, 1, "", 0xa9a4, 0x00696969, 0}, -{W, 1, "", 0xa9a8, 0x006a6a6a, 0}, -{W, 1, "", 0xa9ac, 0x006b6b6b, 0}, -{W, 1, "", 0xa9b0, 0x006c6c6c, 0}, -{W, 1, "", 0xa9b4, 0x006d6d6d, 0}, -{W, 1, "", 0xa9b8, 0x006e6e6e, 0}, -{W, 1, "", 0xa9bc, 0x006f6f6f, 0}, -{W, 1, "", 0xa9c0, 0x00707070, 0}, -{W, 1, "", 0xa9c4, 0x00717171, 0}, -{W, 1, "", 0xa9c8, 0x00727272, 0}, -{W, 1, "", 0xa9cc, 0x00737373, 0}, -{W, 1, "", 0xa9d0, 0x00747474, 0}, -{W, 1, "", 0xa9d4, 0x00757575, 0}, -{W, 1, "", 0xa9d8, 0x00767676, 0}, -{W, 1, "", 0xa9dc, 0x00777777, 0}, -{W, 1, "", 0xa9e0, 0x00787878, 0}, -{W, 1, "", 0xa9e4, 0x00797979, 0}, -{W, 1, "", 0xa9e8, 0x007a7a7a, 0}, -{W, 1, "", 0xa9ec, 0x007b7b7b, 0}, -{W, 1, "", 0xa9f0, 0x007c7c7c, 0}, -{W, 1, "", 0xa9f4, 0x007d7d7d, 0}, -{W, 1, "", 0xa9f8, 0x007e7e7e, 0}, -{W, 1, "", 0xa9fc, 0x007f7f7f, 0}, -{W, 1, "", 0xaa00, 0x00808080, 0}, -{W, 1, "", 0xaa04, 0x00818181, 0}, -{W, 1, "", 0xaa08, 0x00828282, 0}, -{W, 1, "", 0xaa0c, 0x00838383, 0}, -{W, 1, "", 0xaa10, 0x00848484, 0}, -{W, 1, "", 0xaa14, 0x00858585, 0}, -{W, 1, "", 0xaa18, 0x00868686, 0}, -{W, 1, "", 0xaa1c, 0x00878787, 0}, -{W, 1, "", 0xaa20, 0x00888888, 0}, -{W, 1, "", 0xaa24, 0x00898989, 0}, -{W, 1, "", 0xaa28, 0x008a8a8a, 0}, -{W, 1, "", 0xaa2c, 0x008b8b8b, 0}, -{W, 1, "", 0xaa30, 0x008c8c8c, 0}, -{W, 1, "", 0xaa34, 0x008d8d8d, 0}, -{W, 1, "", 0xaa38, 0x008e8e8e, 0}, -{W, 1, "", 0xaa3c, 0x008f8f8f, 0}, -{W, 1, "", 0xaa40, 0x00909090, 0}, -{W, 1, "", 0xaa44, 0x00919191, 0}, -{W, 1, "", 0xaa48, 0x00929292, 0}, -{W, 1, "", 0xaa4c, 0x00939393, 0}, -{W, 1, "", 0xaa50, 0x00949494, 0}, -{W, 1, "", 0xaa54, 0x00959595, 0}, -{W, 1, "", 0xaa58, 0x00969696, 0}, -{W, 1, "", 0xaa5c, 0x00979797, 0}, -{W, 1, "", 0xaa60, 0x00989898, 0}, -{W, 1, "", 0xaa64, 0x00999999, 0}, -{W, 1, "", 0xaa68, 0x009a9a9a, 0}, -{W, 1, "", 0xaa6c, 0x009b9b9b, 0}, -{W, 1, "", 0xaa70, 0x009c9c9c, 0}, -{W, 1, "", 0xaa74, 0x009d9d9d, 0}, -{W, 1, "", 0xaa78, 0x009e9e9e, 0}, -{W, 1, "", 0xaa7c, 0x009f9f9f, 0}, -{W, 1, "", 0xaa80, 0x00a0a0a0, 0}, -{W, 1, "", 0xaa84, 0x00a1a1a1, 0}, -{W, 1, "", 0xaa88, 0x00a2a2a2, 0}, -{W, 1, "", 0xaa8c, 0x00a3a3a3, 0}, -{W, 1, "", 0xaa90, 0x00a4a4a4, 0}, -{W, 1, "", 0xaa94, 0x00a5a5a5, 0}, -{W, 1, "", 0xaa98, 0x00a6a6a6, 0}, -{W, 1, "", 0xaa9c, 0x00a7a7a7, 0}, -{W, 1, "", 0xaaa0, 0x00a8a8a8, 0}, -{W, 1, "", 0xaaa4, 0x00a9a9a9, 0}, -{W, 1, "", 0xaaa8, 0x00aaaaaa, 0}, -{W, 1, "", 0xaaac, 0x00ababab, 0}, -{W, 1, "", 0xaab0, 0x00acacac, 0}, -{W, 1, "", 0xaab4, 0x00adadad, 0}, -{W, 1, "", 0xaab8, 0x00aeaeae, 0}, -{W, 1, "", 0xaabc, 0x00afafaf, 0}, -{W, 1, "", 0xaac0, 0x00b0b0b0, 0}, -{W, 1, "", 0xaac4, 0x00b1b1b1, 0}, -{W, 1, "", 0xaac8, 0x00b2b2b2, 0}, -{W, 1, "", 0xaacc, 0x00b3b3b3, 0}, -{W, 1, "", 0xaad0, 0x00b4b4b4, 0}, -{W, 1, "", 0xaad4, 0x00b5b5b5, 0}, -{W, 1, "", 0xaad8, 0x00b6b6b6, 0}, -{W, 1, "", 0xaadc, 0x00b7b7b7, 0}, -{W, 1, "", 0xaae0, 0x00b8b8b8, 0}, -{W, 1, "", 0xaae4, 0x00b9b9b9, 0}, -{W, 1, "", 0xaae8, 0x00bababa, 0}, -{W, 1, "", 0xaaec, 0x00bbbbbb, 0}, -{W, 1, "", 0xaaf0, 0x00bcbcbc, 0}, -{W, 1, "", 0xaaf4, 0x00bdbdbd, 0}, -{W, 1, "", 0xaaf8, 0x00bebebe, 0}, -{W, 1, "", 0xaafc, 0x00bfbfbf, 0}, -{W, 1, "", 0xab00, 0x00c0c0c0, 0}, -{W, 1, "", 0xab04, 0x00c1c1c1, 0}, -{W, 1, "", 0xab08, 0x00c2c2c2, 0}, -{W, 1, "", 0xab0c, 0x00c3c3c3, 0}, -{W, 1, "", 0xab10, 0x00c4c4c4, 0}, -{W, 1, "", 0xab14, 0x00c5c5c5, 0}, -{W, 1, "", 0xab18, 0x00c6c6c6, 0}, -{W, 1, "", 0xab1c, 0x00c7c7c7, 0}, -{W, 1, "", 0xab20, 0x00c8c8c8, 0}, -{W, 1, "", 0xab24, 0x00c9c9c9, 0}, -{W, 1, "", 0xab28, 0x00cacaca, 0}, -{W, 1, "", 0xab2c, 0x00cbcbcb, 0}, -{W, 1, "", 0xab30, 0x00cccccc, 0}, -{W, 1, "", 0xab34, 0x00cdcdcd, 0}, -{W, 1, "", 0xab38, 0x00cecece, 0}, -{W, 1, "", 0xab3c, 0x00cfcfcf, 0}, -{W, 1, "", 0xab40, 0x00d0d0d0, 0}, -{W, 1, "", 0xab44, 0x00d1d1d1, 0}, -{W, 1, "", 0xab48, 0x00d2d2d2, 0}, -{W, 1, "", 0xab4c, 0x00d3d3d3, 0}, -{W, 1, "", 0xab50, 0x00d4d4d4, 0}, -{W, 1, "", 0xab54, 0x00d5d5d5, 0}, -{W, 1, "", 0xab58, 0x00d6d6d6, 0}, -{W, 1, "", 0xab5c, 0x00d7d7d7, 0}, -{W, 1, "", 0xab60, 0x00d8d8d8, 0}, -{W, 1, "", 0xab64, 0x00d9d9d9, 0}, -{W, 1, "", 0xab68, 0x00dadada, 0}, -{W, 1, "", 0xab6c, 0x00dbdbdb, 0}, -{W, 1, "", 0xab70, 0x00dcdcdc, 0}, -{W, 1, "", 0xab74, 0x00dddddd, 0}, -{W, 1, "", 0xab78, 0x00dedede, 0}, -{W, 1, "", 0xab7c, 0x00dfdfdf, 0}, -{W, 1, "", 0xab80, 0x00e0e0e0, 0}, -{W, 1, "", 0xab84, 0x00e1e1e1, 0}, -{W, 1, "", 0xab88, 0x00e2e2e2, 0}, -{W, 1, "", 0xab8c, 0x00e3e3e3, 0}, -{W, 1, "", 0xab90, 0x00e4e4e4, 0}, -{W, 1, "", 0xab94, 0x00e5e5e5, 0}, -{W, 1, "", 0xab98, 0x00e6e6e6, 0}, -{W, 1, "", 0xab9c, 0x00e7e7e7, 0}, -{W, 1, "", 0xaba0, 0x00e8e8e8, 0}, -{W, 1, "", 0xaba4, 0x00e9e9e9, 0}, -{W, 1, "", 0xaba8, 0x00eaeaea, 0}, -{W, 1, "", 0xabac, 0x00ebebeb, 0}, -{W, 1, "", 0xabb0, 0x00ececec, 0}, -{W, 1, "", 0xabb4, 0x00ededed, 0}, -{W, 1, "", 0xabb8, 0x00eeeeee, 0}, -{W, 1, "", 0xabbc, 0x00efefef, 0}, -{W, 1, "", 0xabc0, 0x00f0f0f0, 0}, -{W, 1, "", 0xabc4, 0x00f1f1f1, 0}, -{W, 1, "", 0xabc8, 0x00f2f2f2, 0}, -{W, 1, "", 0xabcc, 0x00f3f3f3, 0}, -{W, 1, "", 0xabd0, 0x00f4f4f4, 0}, -{W, 1, "", 0xabd4, 0x00f5f5f5, 0}, -{W, 1, "", 0xabd8, 0x00f6f6f6, 0}, -{W, 1, "", 0xabdc, 0x00f7f7f7, 0}, -{W, 1, "", 0xabe0, 0x00f8f8f8, 0}, -{W, 1, "", 0xabe4, 0x00f9f9f9, 0}, -{W, 1, "", 0xabe8, 0x00fafafa, 0}, -{W, 1, "", 0xabec, 0x00fbfbfb, 0}, -{W, 1, "", 0xabf0, 0x00fcfcfc, 0}, -{W, 1, "", 0xabf4, 0x00fdfdfd, 0}, -{W, 1, "", 0xabf8, 0x00fefefe, 0}, -{W, 1, "", 0xabfc, 0x00ffffff, 0}, -{W, 1, "", _PALETTE_B, 0x00000000, 0}, -{W, 1, "", _PALETTE_B+0x4, 0x00010101, 0}, -{W, 1, "", _PALETTE_B+0x8, 0x00020202, 0}, -{W, 1, "", _PALETTE_B+0xc, 0x00030303, 0}, -{W, 1, "", _PALETTE_B+0x10, 0x00040404, 0}, -{W, 1, "", _PALETTE_B+0x14, 0x00050505, 0}, -{W, 1, "", _PALETTE_B+0x18, 0x00060606, 0}, -{W, 1, "", _PALETTE_B+0x1c, 0x00070707, 0}, -{W, 1, "", _PALETTE_B+0x20, 0x00080808, 0}, -{W, 1, "", _PALETTE_B+0x24, 0x00090909, 0}, -{W, 1, "", _PALETTE_B+0x28, 0x000a0a0a, 0}, -{W, 1, "", _PALETTE_B+0x2c, 0x000b0b0b, 0}, -{W, 1, "", _PALETTE_B+0x30, 0x000c0c0c, 0}, -{W, 1, "", _PALETTE_B+0x34, 0x000d0d0d, 0}, -{W, 1, "", _PALETTE_B+0x38, 0x000e0e0e, 0}, -{W, 1, "", _PALETTE_B+0x3c, 0x000f0f0f, 0}, -{W, 1, "", _PALETTE_B+0x40, 0x00101010, 0}, -{W, 1, "", _PALETTE_B+0x44, 0x00111111, 0}, -{W, 1, "", _PALETTE_B+0x48, 0x00121212, 0}, -{W, 1, "", _PALETTE_B+0x4c, 0x00131313, 0}, -{W, 1, "", _PALETTE_B+0x50, 0x00141414, 0}, -{W, 1, "", _PALETTE_B+0x54, 0x00151515, 0}, -{W, 1, "", _PALETTE_B+0x58, 0x00161616, 0}, -{W, 1, "", _PALETTE_B+0x5c, 0x00171717, 0}, -{W, 1, "", _PALETTE_B+0x60, 0x00181818, 0}, -{W, 1, "", _PALETTE_B+0x64, 0x00191919, 0}, -{W, 1, "", _PALETTE_B+0x68, 0x001a1a1a, 0}, -{W, 1, "", _PALETTE_B+0x6c, 0x001b1b1b, 0}, -{W, 1, "", _PALETTE_B+0x70, 0x001c1c1c, 0}, -{W, 1, "", _PALETTE_B+0x74, 0x001d1d1d, 0}, -{W, 1, "", _PALETTE_B+0x78, 0x001e1e1e, 0}, -{W, 1, "", _PALETTE_B+0x7c, 0x001f1f1f, 0}, -{W, 1, "", 0xa880, 0x00202020, 0}, -{W, 1, "", 0xa884, 0x00212121, 0}, -{W, 1, "", 0xa888, 0x00222222, 0}, -{W, 1, "", 0xa88c, 0x00232323, 0}, -{W, 1, "", 0xa890, 0x00242424, 0}, -{W, 1, "", 0xa894, 0x00252525, 0}, -{W, 1, "", 0xa898, 0x00262626, 0}, -{W, 1, "", 0xa89c, 0x00272727, 0}, -{W, 1, "", 0xa8a0, 0x00282828, 0}, -{W, 1, "", 0xa8a4, 0x00292929, 0}, -{W, 1, "", 0xa8a8, 0x002a2a2a, 0}, -{W, 1, "", 0xa8ac, 0x002b2b2b, 0}, -{W, 1, "", 0xa8b0, 0x002c2c2c, 0}, -{W, 1, "", 0xa8b4, 0x002d2d2d, 0}, -{W, 1, "", 0xa8b8, 0x002e2e2e, 0}, -{W, 1, "", 0xa8bc, 0x002f2f2f, 0}, -{W, 1, "", 0xa8c0, 0x00303030, 0}, -{W, 1, "", 0xa8c4, 0x00313131, 0}, -{W, 1, "", 0xa8c8, 0x00323232, 0}, -{W, 1, "", 0xa8cc, 0x00333333, 0}, -{W, 1, "", 0xa8d0, 0x00343434, 0}, -{W, 1, "", 0xa8d4, 0x00353535, 0}, -{W, 1, "", 0xa8d8, 0x00363636, 0}, -{W, 1, "", 0xa8dc, 0x00373737, 0}, -{W, 1, "", 0xa8e0, 0x00383838, 0}, -{W, 1, "", 0xa8e4, 0x00393939, 0}, -{W, 1, "", 0xa8e8, 0x003a3a3a, 0}, -{W, 1, "", 0xa8ec, 0x003b3b3b, 0}, -{W, 1, "", 0xa8f0, 0x003c3c3c, 0}, -{W, 1, "", 0xa8f4, 0x003d3d3d, 0}, -{W, 1, "", 0xa8f8, 0x003e3e3e, 0}, -{W, 1, "", 0xa8fc, 0x003f3f3f, 0}, -{W, 1, "", 0xa900, 0x00404040, 0}, -{W, 1, "", 0xa904, 0x00414141, 0}, -{W, 1, "", 0xa908, 0x00424242, 0}, -{W, 1, "", 0xa90c, 0x00434343, 0}, -{W, 1, "", 0xa910, 0x00444444, 0}, -{W, 1, "", 0xa914, 0x00454545, 0}, -{W, 1, "", 0xa918, 0x00464646, 0}, -{W, 1, "", 0xa91c, 0x00474747, 0}, -{W, 1, "", 0xa920, 0x00484848, 0}, -{W, 1, "", 0xa924, 0x00494949, 0}, -{W, 1, "", 0xa928, 0x004a4a4a, 0}, -{W, 1, "", 0xa92c, 0x004b4b4b, 0}, -{W, 1, "", 0xa930, 0x004c4c4c, 0}, -{W, 1, "", 0xa934, 0x004d4d4d, 0}, -{W, 1, "", 0xa938, 0x004e4e4e, 0}, -{W, 1, "", 0xa93c, 0x004f4f4f, 0}, -{W, 1, "", 0xa940, 0x00505050, 0}, -{W, 1, "", 0xa944, 0x00515151, 0}, -{W, 1, "", 0xa948, 0x00525252, 0}, -{W, 1, "", 0xa94c, 0x00535353, 0}, -{W, 1, "", 0xa950, 0x00545454, 0}, -{W, 1, "", 0xa954, 0x00555555, 0}, -{W, 1, "", 0xa958, 0x00565656, 0}, -{W, 1, "", 0xa95c, 0x00575757, 0}, -{W, 1, "", 0xa960, 0x00585858, 0}, -{W, 1, "", 0xa964, 0x00595959, 0}, -{W, 1, "", 0xa968, 0x005a5a5a, 0}, -{W, 1, "", 0xa96c, 0x005b5b5b, 0}, -{W, 1, "", 0xa970, 0x005c5c5c, 0}, -{W, 1, "", 0xa974, 0x005d5d5d, 0}, -{W, 1, "", 0xa978, 0x005e5e5e, 0}, -{W, 1, "", 0xa97c, 0x005f5f5f, 0}, -{W, 1, "", 0xa980, 0x00606060, 0}, -{W, 1, "", 0xa984, 0x00616161, 0}, -{W, 1, "", 0xa988, 0x00626262, 0}, -{W, 1, "", 0xa98c, 0x00636363, 0}, -{W, 1, "", 0xa990, 0x00646464, 0}, -{W, 1, "", 0xa994, 0x00656565, 0}, -{W, 1, "", 0xa998, 0x00666666, 0}, -{W, 1, "", 0xa99c, 0x00676767, 0}, -{W, 1, "", 0xa9a0, 0x00686868, 0}, -{W, 1, "", 0xa9a4, 0x00696969, 0}, -{W, 1, "", 0xa9a8, 0x006a6a6a, 0}, -{W, 1, "", 0xa9ac, 0x006b6b6b, 0}, -{W, 1, "", 0xa9b0, 0x006c6c6c, 0}, -{W, 1, "", 0xa9b4, 0x006d6d6d, 0}, -{W, 1, "", 0xa9b8, 0x006e6e6e, 0}, -{W, 1, "", 0xa9bc, 0x006f6f6f, 0}, -{W, 1, "", 0xa9c0, 0x00707070, 0}, -{W, 1, "", 0xa9c4, 0x00717171, 0}, -{W, 1, "", 0xa9c8, 0x00727272, 0}, -{W, 1, "", 0xa9cc, 0x00737373, 0}, -{W, 1, "", 0xa9d0, 0x00747474, 0}, -{W, 1, "", 0xa9d4, 0x00757575, 0}, -{W, 1, "", 0xa9d8, 0x00767676, 0}, -{W, 1, "", 0xa9dc, 0x00777777, 0}, -{W, 1, "", 0xa9e0, 0x00787878, 0}, -{W, 1, "", 0xa9e4, 0x00797979, 0}, -{W, 1, "", 0xa9e8, 0x007a7a7a, 0}, -{W, 1, "", 0xa9ec, 0x007b7b7b, 0}, -{W, 1, "", 0xa9f0, 0x007c7c7c, 0}, -{W, 1, "", 0xa9f4, 0x007d7d7d, 0}, -{W, 1, "", 0xa9f8, 0x007e7e7e, 0}, -{W, 1, "", 0xa9fc, 0x007f7f7f, 0}, -{W, 1, "", 0xaa00, 0x00808080, 0}, -{W, 1, "", 0xaa04, 0x00818181, 0}, -{W, 1, "", 0xaa08, 0x00828282, 0}, -{W, 1, "", 0xaa0c, 0x00838383, 0}, -{W, 1, "", 0xaa10, 0x00848484, 0}, -{W, 1, "", 0xaa14, 0x00858585, 0}, -{W, 1, "", 0xaa18, 0x00868686, 0}, -{W, 1, "", 0xaa1c, 0x00878787, 0}, -{W, 1, "", 0xaa20, 0x00888888, 0}, -{W, 1, "", 0xaa24, 0x00898989, 0}, -{W, 1, "", 0xaa28, 0x008a8a8a, 0}, -{W, 1, "", 0xaa2c, 0x008b8b8b, 0}, -{W, 1, "", 0xaa30, 0x008c8c8c, 0}, -{W, 1, "", 0xaa34, 0x008d8d8d, 0}, -{W, 1, "", 0xaa38, 0x008e8e8e, 0}, -{W, 1, "", 0xaa3c, 0x008f8f8f, 0}, -{W, 1, "", 0xaa40, 0x00909090, 0}, -{W, 1, "", 0xaa44, 0x00919191, 0}, -{W, 1, "", 0xaa48, 0x00929292, 0}, -{W, 1, "", 0xaa4c, 0x00939393, 0}, -{W, 1, "", 0xaa50, 0x00949494, 0}, -{W, 1, "", 0xaa54, 0x00959595, 0}, -{W, 1, "", 0xaa58, 0x00969696, 0}, -{W, 1, "", 0xaa5c, 0x00979797, 0}, -{W, 1, "", 0xaa60, 0x00989898, 0}, -{W, 1, "", 0xaa64, 0x00999999, 0}, -{W, 1, "", 0xaa68, 0x009a9a9a, 0}, -{W, 1, "", 0xaa6c, 0x009b9b9b, 0}, -{W, 1, "", 0xaa70, 0x009c9c9c, 0}, -{W, 1, "", 0xaa74, 0x009d9d9d, 0}, -{W, 1, "", 0xaa78, 0x009e9e9e, 0}, -{W, 1, "", 0xaa7c, 0x009f9f9f, 0}, -{W, 1, "", 0xaa80, 0x00a0a0a0, 0}, -{W, 1, "", 0xaa84, 0x00a1a1a1, 0}, -{W, 1, "", 0xaa88, 0x00a2a2a2, 0}, -{W, 1, "", 0xaa8c, 0x00a3a3a3, 0}, -{W, 1, "", 0xaa90, 0x00a4a4a4, 0}, -{W, 1, "", 0xaa94, 0x00a5a5a5, 0}, -{W, 1, "", 0xaa98, 0x00a6a6a6, 0}, -{W, 1, "", 0xaa9c, 0x00a7a7a7, 0}, -{W, 1, "", 0xaaa0, 0x00a8a8a8, 0}, -{W, 1, "", 0xaaa4, 0x00a9a9a9, 0}, -{W, 1, "", 0xaaa8, 0x00aaaaaa, 0}, -{W, 1, "", 0xaaac, 0x00ababab, 0}, -{W, 1, "", 0xaab0, 0x00acacac, 0}, -{W, 1, "", 0xaab4, 0x00adadad, 0}, -{W, 1, "", 0xaab8, 0x00aeaeae, 0}, -{W, 1, "", 0xaabc, 0x00afafaf, 0}, -{W, 1, "", 0xaac0, 0x00b0b0b0, 0}, -{W, 1, "", 0xaac4, 0x00b1b1b1, 0}, -{W, 1, "", 0xaac8, 0x00b2b2b2, 0}, -{W, 1, "", 0xaacc, 0x00b3b3b3, 0}, -{W, 1, "", 0xaad0, 0x00b4b4b4, 0}, -{W, 1, "", 0xaad4, 0x00b5b5b5, 0}, -{W, 1, "", 0xaad8, 0x00b6b6b6, 0}, -{W, 1, "", 0xaadc, 0x00b7b7b7, 0}, -{W, 1, "", 0xaae0, 0x00b8b8b8, 0}, -{W, 1, "", 0xaae4, 0x00b9b9b9, 0}, -{W, 1, "", 0xaae8, 0x00bababa, 0}, -{W, 1, "", 0xaaec, 0x00bbbbbb, 0}, -{W, 1, "", 0xaaf0, 0x00bcbcbc, 0}, -{W, 1, "", 0xaaf4, 0x00bdbdbd, 0}, -{W, 1, "", 0xaaf8, 0x00bebebe, 0}, -{W, 1, "", 0xaafc, 0x00bfbfbf, 0}, -{W, 1, "", 0xab00, 0x00c0c0c0, 0}, -{W, 1, "", 0xab04, 0x00c1c1c1, 0}, -{W, 1, "", 0xab08, 0x00c2c2c2, 0}, -{W, 1, "", 0xab0c, 0x00c3c3c3, 0}, -{W, 1, "", 0xab10, 0x00c4c4c4, 0}, -{W, 1, "", 0xab14, 0x00c5c5c5, 0}, -{W, 1, "", 0xab18, 0x00c6c6c6, 0}, -{W, 1, "", 0xab1c, 0x00c7c7c7, 0}, -{W, 1, "", 0xab20, 0x00c8c8c8, 0}, -{W, 1, "", 0xab24, 0x00c9c9c9, 0}, -{W, 1, "", 0xab28, 0x00cacaca, 0}, -{W, 1, "", 0xab2c, 0x00cbcbcb, 0}, -{W, 1, "", 0xab30, 0x00cccccc, 0}, -{W, 1, "", 0xab34, 0x00cdcdcd, 0}, -{W, 1, "", 0xab38, 0x00cecece, 0}, -{W, 1, "", 0xab3c, 0x00cfcfcf, 0}, -{W, 1, "", 0xab40, 0x00d0d0d0, 0}, -{W, 1, "", 0xab44, 0x00d1d1d1, 0}, -{W, 1, "", 0xab48, 0x00d2d2d2, 0}, -{W, 1, "", 0xab4c, 0x00d3d3d3, 0}, -{W, 1, "", 0xab50, 0x00d4d4d4, 0}, -{W, 1, "", 0xab54, 0x00d5d5d5, 0}, -{W, 1, "", 0xab58, 0x00d6d6d6, 0}, -{W, 1, "", 0xab5c, 0x00d7d7d7, 0}, -{W, 1, "", 0xab60, 0x00d8d8d8, 0}, -{W, 1, "", 0xab64, 0x00d9d9d9, 0}, -{W, 1, "", 0xab68, 0x00dadada, 0}, -{W, 1, "", 0xab6c, 0x00dbdbdb, 0}, -{W, 1, "", 0xab70, 0x00dcdcdc, 0}, -{W, 1, "", 0xab74, 0x00dddddd, 0}, -{W, 1, "", 0xab78, 0x00dedede, 0}, -{W, 1, "", 0xab7c, 0x00dfdfdf, 0}, -{W, 1, "", 0xab80, 0x00e0e0e0, 0}, -{W, 1, "", 0xab84, 0x00e1e1e1, 0}, -{W, 1, "", 0xab88, 0x00e2e2e2, 0}, -{W, 1, "", 0xab8c, 0x00e3e3e3, 0}, -{W, 1, "", 0xab90, 0x00e4e4e4, 0}, -{W, 1, "", 0xab94, 0x00e5e5e5, 0}, -{W, 1, "", 0xab98, 0x00e6e6e6, 0}, -{W, 1, "", 0xab9c, 0x00e7e7e7, 0}, -{W, 1, "", 0xaba0, 0x00e8e8e8, 0}, -{W, 1, "", 0xaba4, 0x00e9e9e9, 0}, -{W, 1, "", 0xaba8, 0x00eaeaea, 0}, -{W, 1, "", 0xabac, 0x00ebebeb, 0}, -{W, 1, "", 0xabb0, 0x00ececec, 0}, -{W, 1, "", 0xabb4, 0x00ededed, 0}, -{W, 1, "", 0xabb8, 0x00eeeeee, 0}, -{W, 1, "", 0xabbc, 0x00efefef, 0}, -{W, 1, "", 0xabc0, 0x00f0f0f0, 0}, -{W, 1, "", 0xabc4, 0x00f1f1f1, 0}, -{W, 1, "", 0xabc8, 0x00f2f2f2, 0}, -{W, 1, "", 0xabcc, 0x00f3f3f3, 0}, -{W, 1, "", 0xabd0, 0x00f4f4f4, 0}, -{W, 1, "", 0xabd4, 0x00f5f5f5, 0}, -{W, 1, "", 0xabd8, 0x00f6f6f6, 0}, -{W, 1, "", 0xabdc, 0x00f7f7f7, 0}, -{W, 1, "", 0xabe0, 0x00f8f8f8, 0}, -{W, 1, "", 0xabe4, 0x00f9f9f9, 0}, -{W, 1, "", 0xabe8, 0x00fafafa, 0}, -{W, 1, "", 0xabec, 0x00fbfbfb, 0}, -{W, 1, "", 0xabf0, 0x00fcfcfc, 0}, -{W, 1, "", 0xabf4, 0x00fdfdfd, 0}, -{W, 1, "", 0xabf8, 0x00fefefe, 0}, -{W, 1, "", 0xabfc, 0x00ffffff, 0}, {M, 1, "i915 0000:00:02.0:fb0:inteldrmfb frame buffer device", 0x0, 0x0, 0}, {M, 1, "i915 0000:00:02.0:registered panic notifier", 0x0, 0x0, 0}, {M, 1, "[drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0", 0x0, 0x0, 0}, diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..ad63c97 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -40,8 +40,8 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ @@ -92,7 +92,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);

1 0

Patch merged into coreboot/master: 7176ac7 Remove CACHE_ROM.
by gerrit＠coreboot.org 25 Feb '14

25 Feb '14

the following patch was just integrated into master: commit 7176ac78e3d7ad16891b4925ce440bf2a90d0131 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5146 for details. -gerrit

1 0

Patch merged into coreboot/master: 32cb934 intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit 32cb934fba946ce23416d7e78e59e87541be51c3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Feb 11 10:38:27 2014 +0100 intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB Linux kernel 2.6.31 reports the warning below on Intel Ivy Bridge (with FSP). resource map sanity check conflict: 0xfed10000 0xfed17fff 0xfed10000 0xfed13fff pnp 00:01 Since Sandy Bridge the length of the MCHBAR is 32 kB and it is already used that way in other places. $ more src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl […] OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) […] So instead of 16 kB specify that 32 kB are decoded in that memory range for Intel Sandy Bridge, Ivy Bridge and Haswell. (Linux kernel 3.10 does not warn about that.) Change-Id: Ie7a9356d9051c807833df85e4a806e5a9498473f Reported-by: Norwich in #coreboot on <irc.freenode.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5192 for details. -gerrit

1 0

Patch set updated for coreboot: 7176ac7 Remove CACHE_ROM.
by Vladimir Serbinenko 24 Feb '14

24 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 7176ac78e3d7ad16891b4925ce440bf2a90d0131 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 23 -------- src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 163 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index dc6012b..b7bea20 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -789,9 +789,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* Restore the default SMM region. */ restore_default_smm_area(smm_save_area); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 98238d8..19fa246 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d85a869..86e31d0 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -199,16 +199,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB, filter_vga_wrcomb); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -380,61 +370,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -482,17 +417,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..2a44072 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,25 +67,6 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that - * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the - * rom caching will be disabled if all threads run the MTRR code. Therefore, - * one needs to call x86_mtrr_enable_rom_caching() after all threads of the - * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ - #endif #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index d00acaa..2360b36 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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Patch set updated for coreboot: b7b0f8f Remove CACHE_ROM.
by Vladimir Serbinenko 24 Feb '14

24 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit b7b0f8f4be4002841e13be8cee4ca0ad7dbab9ef Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherencyin worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 23 -------- src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 163 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index dc6012b..b7bea20 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -789,9 +789,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* Restore the default SMM region. */ restore_default_smm_area(smm_save_area); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 98238d8..19fa246 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d85a869..86e31d0 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -199,16 +199,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB, filter_vga_wrcomb); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -380,61 +370,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -482,17 +417,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..2a44072 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,25 +67,6 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that - * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the - * rom caching will be disabled if all threads run the MTRR code. Therefore, - * one needs to call x86_mtrr_enable_rom_caching() after all threads of the - * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ - #endif #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index d00acaa..2360b36 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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Patch set updated for coreboot: 47bc952 Remove CACHE_ROM.
by Vladimir Serbinenko 24 Feb '14

24 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 47bc952d4c7c5fe396494801263482fb76b720d1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 23 -------- src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 163 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index dc6012b..b7bea20 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -789,9 +789,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* Restore the default SMM region. */ restore_default_smm_area(smm_save_area); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 98238d8..19fa246 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d85a869..86e31d0 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -199,16 +199,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB, filter_vga_wrcomb); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -380,61 +370,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -482,17 +417,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..2a44072 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,25 +67,6 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that - * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the - * rom caching will be disabled if all threads run the MTRR code. Therefore, - * one needs to call x86_mtrr_enable_rom_caching() after all threads of the - * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ - #endif #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index d00acaa..2360b36 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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Patch set updated for coreboot: 5d9223b Remove CACHE_ROM.
by Vladimir Serbinenko 24 Feb '14

24 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5146 -gerrit commit 5d9223b58a92ed9d973a00c6f5b7a44bbab52bc2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 19:46:45 2014 +0100 Remove CACHE_ROM. With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs on all systems I tried it on, hence screwing up I/O access and cache coherency in worst cases. Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/intel/haswell/haswell_init.c | 3 - src/cpu/intel/haswell/mp_init.c | 15 ----- src/cpu/x86/Kconfig | 7 --- src/cpu/x86/mtrr/mtrr.c | 76 ------------------------- src/include/cpu/x86/mtrr.h | 23 -------- src/lib/coreboot_table.c | 20 ------- src/mainboard/google/Kconfig | 5 -- src/mainboard/google/bolt/Kconfig | 1 - src/mainboard/google/falco/Kconfig | 1 - src/mainboard/google/peppy/Kconfig | 1 - src/mainboard/google/slippy/Kconfig | 1 - src/mainboard/intel/wtm2/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 4 -- src/northbridge/intel/nehalem/northbridge.c | 2 - src/northbridge/intel/sandybridge/northbridge.c | 2 - src/soc/intel/baytrail/Kconfig | 1 - 16 files changed, 163 deletions(-) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index dc6012b..b7bea20 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -789,9 +789,6 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) /* Restore the default SMM region. */ restore_default_smm_area(smm_save_area); - - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/haswell/mp_init.c b/src/cpu/intel/haswell/mp_init.c index 51130a5..0398360 100644 --- a/src/cpu/intel/haswell/mp_init.c +++ b/src/cpu/intel/haswell/mp_init.c @@ -143,14 +143,6 @@ void release_aps_for_smm_relocation(int do_parallel) printk(BIOS_DEBUG, "Timed out waiting for AP SMM relocation\n"); } -/* The mtrr code sets up ROM caching on the BSP, but not the others. However, - * the boot loader payload disables this. In order for Linux not to complain - * ensure the caching is disabled for the APs before going to sleep. */ -static void cleanup_rom_caching(void) -{ - x86_mtrr_disable_rom_caching(); -} - /* By the time APs call ap_init() caching has been setup, and microcode has * been loaded. */ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) @@ -184,13 +176,6 @@ static void asmlinkage ap_init(unsigned int cpu, void *microcode_ptr) /* After SMM relocation a 2nd microcode load is required. */ intel_microcode_load_unlocked(microcode_ptr); - /* The MTRR resources are core scoped. Therefore, there is no need - * to do the same work twice. Additionally, this check keeps the - * ROM cache enabled on the BSP since its hyperthread sibling won't - * call cleanup_rom_caching(). */ - if ((lapicid() & 1) == 0) - cleanup_rom_caching(); - /* FIXME(adurbin): park CPUs properly -- preferably somewhere in a * reserved part of memory that the OS cannot get to. */ stop_this_cpu(); diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 98238d8..19fa246 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -76,13 +76,6 @@ config LOGICAL_CPUS bool default y -config CACHE_ROM - bool "Allow for caching system ROM." - default n - help - When selected a variable range MTRR is allocated for coreboot and - the bootloader enables caching of the system ROM for faster access. - config SMM_TSEG bool default n diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index d85a869..86e31d0 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -199,16 +199,6 @@ static struct memranges *get_physical_address_space(void) memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB, filter_vga_wrcomb); -#if CONFIG_CACHE_ROM - /* Add a write-protect region covering the ROM size - * when CONFIG_CACHE_ROM is enabled. The ROM is assumed - * to be located at 4GiB - rom size. */ - resource_t rom_base = RANGE_TO_PHYS_ADDR( - RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE)); - memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); -#endif - /* The address space below 4GiB is special. It needs to be * covered entirly by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. @@ -380,61 +370,6 @@ void x86_setup_fixed_mtrrs(void) enable_fixed_mtrr(); } -/* Keep track of the MTRR that covers the ROM for caching purposes. */ -#if CONFIG_CACHE_ROM -static long rom_cache_mtrr = -1; - -long x86_mtrr_rom_cache_var_index(void) -{ - return rom_cache_mtrr; -} - -void x86_mtrr_enable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - msr_val.lo |= MTRR_TYPE_WRPROT; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -void x86_mtrr_disable_rom_caching(void) -{ - msr_t msr_val; - unsigned long index; - - if (rom_cache_mtrr < 0) - return; - - index = rom_cache_mtrr; - disable_cache(); - msr_val = rdmsr(MTRRphysBase_MSR(index)); - msr_val.lo &= ~0xff; - wrmsr(MTRRphysBase_MSR(index), msr_val); - enable_cache(); -} - -static void disable_cache_rom(void *unused) -{ - x86_mtrr_disable_rom_caching(); -} - -BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, - disable_cache_rom, NULL), - BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, - disable_cache_rom, NULL), -}; -#endif - struct var_mtrr_state { struct memranges *addr_space; int above4gb; @@ -482,17 +417,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state, mask = (1ULL << var_state->address_bits) - 1; rsize = rsize & mask; -#if CONFIG_CACHE_ROM - /* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing - * one to turn on caching for faster ROM access. However, it is - * left to the MTRR callers to enable it. */ - if (mtrr_type == MTRR_TYPE_WRPROT) { - mtrr_type = MTRR_TYPE_UNCACHEABLE; - if (rom_cache_mtrr < 0) - rom_cache_mtrr = var_state->mtrr_index; - } -#endif - printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", var_state->mtrr_index, rbase, rsize, mtrr_type); diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 9414687..2a44072 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -52,10 +52,6 @@ * of the nature of the global MTRR enable flag. Therefore, all direct * or indirect callers of enable_fixed_mtrr() should ensure that the * variable MTRR MSRs do not contain bad ranges. - * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling - * the caching of the ROM. However, it is set to uncacheable (UC). It - * is the responsibility of the caller to enable it by calling - * x86_mtrr_enable_rom_caching(). */ void x86_setup_mtrrs(void); /* @@ -71,25 +67,6 @@ void x86_setup_fixed_mtrrs(void); /* Set up fixed MTRRs but do not enable them. */ void x86_setup_fixed_mtrrs_no_enable(void); int x86_mtrr_check(void); -/* ROM caching can be used after variable MTRRs are set up. Beware that - * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on - * one's IO hole size and WRCOMB resources. Be sure to check the console - * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that - * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the - * rom caching will be disabled if all threads run the MTRR code. Therefore, - * one needs to call x86_mtrr_enable_rom_caching() after all threads of the - * same core have run the MTRR code. */ -#if CONFIG_CACHE_ROM -void x86_mtrr_enable_rom_caching(void); -void x86_mtrr_disable_rom_caching(void); -/* Return the variable range MTRR index of the ROM cache. */ -long x86_mtrr_rom_cache_var_index(void); -#else -static inline void x86_mtrr_enable_rom_caching(void) {} -static inline void x86_mtrr_disable_rom_caching(void) {} -static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } -#endif /* CONFIG_CACHE_ROM */ - #endif #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d5dc14c..904185a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -235,24 +235,6 @@ static inline void lb_vboot_handoff(struct lb_header *header) {} #endif /* CONFIG_VBOOT_VERIFY_FIRMWARE */ #endif /* CONFIG_CHROMEOS */ -static void lb_x86_rom_cache(struct lb_header *header) -{ -#if CONFIG_ARCH_X86 - long mtrr_index; - struct lb_x86_rom_mtrr *lb_x86_rom_mtrr; - - mtrr_index = x86_mtrr_rom_cache_var_index(); - - if (mtrr_index < 0) - return; - - lb_x86_rom_mtrr = (struct lb_x86_rom_mtrr *)lb_new_record(header); - lb_x86_rom_mtrr->tag = LB_TAG_X86_ROM_MTRR; - lb_x86_rom_mtrr->size = sizeof(struct lb_x86_rom_mtrr); - lb_x86_rom_mtrr->index = mtrr_index; -#endif -} - static void add_cbmem_pointers(struct lb_header *header) { /* @@ -529,8 +511,6 @@ unsigned long write_coreboot_table( lb_strings(head); /* Record our framebuffer */ lb_framebuffer(head); - /* Communicate x86 variable MTRR ROM cache information. */ - lb_x86_rom_cache(head); #if CONFIG_CHROMEOS /* Record our GPIO settings (ChromeOS specific) */ diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index b86b0ad..85c8592 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -18,11 +18,6 @@ ## if VENDOR_GOOGLE -# Auto select common options -config VENDOR_SPECIFIC_OPTIONS - def_bool y - select CACHE_ROM - choice prompt "Mainboard model" diff --git a/src/mainboard/google/bolt/Kconfig b/src/mainboard/google/bolt/Kconfig index 5247070..47d41ed 100644 --- a/src/mainboard/google/bolt/Kconfig +++ b/src/mainboard/google/bolt/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index d800206..5d19ffc 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select DRIVERS_I2C_RTD2132 diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 6cac476..f401feb 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 6980234..ba6a6fe 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select EXTERNAL_MRC_BLOB - select CACHE_ROM select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 8e13108..00ea604 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS - select CACHE_ROM select MAINBOARD_HAS_NATIVE_VGA_INIT select MONOTONIC_TIMER_MSR diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5..ce366ef 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386de..d94bc09 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301..5440140 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index d00acaa..2360b36 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,7 +9,6 @@ if SOC_INTEL_BAYTRAIL config CPU_SPECIFIC_OPTIONS def_bool y select CACHE_MRC_SETTINGS - select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS select CPU_MICROCODE_IN_CBFS

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Patch set updated for coreboot: 488ef52 baytrail: add support for disabling southcluster pci devices
by Aaron Durbin 24 Feb '14

24 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4911 -gerrit commit 488ef529aa13fa84d366b08797fcf5fe37ce8758 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 16:37:10 2013 -0500 baytrail: add support for disabling southcluster pci devices When the southcluster pci devices are listed in the devicetree add the ability to perform the proper disabling seqence for turning off devices. This only turns off the pci device interface as well as put the device into D3Hot. It is not yet know how to put the TXE device into D3Hot so it's currently not possible to disable that device. Also, expose the southcluster_enable_dev() function so that other devices can call this if they require doing specific things before disabling the device. The southcluster_enable_dev() is only called on devices found in the devicetree and if they currently have no ops associated with them. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Interrogated output to ensure devices were being properly disabled. Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174644 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 4 + src/soc/intel/baytrail/baytrail/pmc.h | 33 +++++ src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.c | 8 +- src/soc/intel/baytrail/southcluster.c | 204 ++++++++++++++++++++++++++++- 5 files changed, 247 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 8b0335e..f20102a 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -102,12 +102,16 @@ /* PCIe Ports */ #define PCIE_DEV 28 +# define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 # define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 # define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 # define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index e0e5cff..51f8887 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -33,6 +33,39 @@ # define IGNORE_HPET (1 << 21) # define CF9GR (1 << 20) # define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index eaa8f6b..4fa6ddd 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -27,6 +27,7 @@ void baytrail_init_pre_device(void); void baytrail_init_cpus(device_t dev); void set_max_freq(void); +void southcluster_enable_dev(device_t dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 0f686fa..eedae39 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -53,13 +53,17 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(device_t dev) { - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } } } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 32b8799..b16a9cf 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <arch/io.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -29,6 +30,7 @@ #include <baytrail/lpc.h> #include <baytrail/nvs.h> #include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> #include <baytrail/ramstage.h> static inline void @@ -113,12 +115,212 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +/* + * Common code for the south cluster devices. + */ + +/* Set bit in function disble register to hide this device. */ +static void sc_disable_devfn(device_t dev) +{ + const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; + const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t mask = 0; + uint32_t mask2 = 0; + +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask2 |= name_ ## _DIS + + switch (dev->path.pci.devfn) { + SET_DIS_MASK(SDIO); + break; + SET_DIS_MASK(SD); + break; + SET_DIS_MASK(SATA); + break; + SET_DIS_MASK(XHCI); + /* Disable super speed PHY when XHCI is not available. */ + mask2 |= USH_SS_PHY_DIS; + break; + SET_DIS_MASK(LPE); + break; + SET_DIS_MASK(MMC); + break; + SET_DIS_MASK(SIO_DMA1); + break; + SET_DIS_MASK(I2C1); + break; + SET_DIS_MASK(I2C2); + break; + SET_DIS_MASK(I2C3); + break; + SET_DIS_MASK(I2C4); + break; + SET_DIS_MASK(I2C5); + break; + SET_DIS_MASK(I2C6); + break; + SET_DIS_MASK(I2C7); + break; + SET_DIS_MASK(TXE); + break; + SET_DIS_MASK(HDA); + break; + SET_DIS_MASK(PCIE_PORT1); + break; + SET_DIS_MASK(PCIE_PORT2); + break; + SET_DIS_MASK(PCIE_PORT3); + break; + SET_DIS_MASK(PCIE_PORT4); + break; + SET_DIS_MASK(EHCI); + break; + SET_DIS_MASK(SIO_DMA2); + break; + SET_DIS_MASK(PWM1); + break; + SET_DIS_MASK(PWM2); + break; + SET_DIS_MASK(HSUART1); + break; + SET_DIS_MASK(HSUART2); + break; + SET_DIS_MASK(SPI); + break; + SET_DIS_MASK2(SMBUS); + break; + } + + if (mask != 0) { + write32(func_dis, read32(func_dis) | mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (mask2 != 0) { + write32(func_dis2, read32(func_dis2) | mask2); + /* Ensure posted write hits. */ + read32(func_dis2); + } +} + +static inline void set_d3hot_bits(device_t dev, int offset) +{ + uint32_t reg8; + printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); + reg8 = pci_read_config8(dev, offset + 4); + reg8 |= 0x3; + pci_write_config8(dev, offset + 4, reg8); +} + +static int place_device_in_d3hot(device_t dev) +{ + unsigned offset; + + offset = pci_find_capability(dev, PCI_CAP_ID_PM); + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + /* For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. */ +#define DEV_CASE(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + DEV_CASE(SDIO): + DEV_CASE(SD): + DEV_CASE(MMC): + DEV_CASE(LPE): + DEV_CASE(SIO_DMA1): + DEV_CASE(I2C1): + DEV_CASE(I2C2): + DEV_CASE(I2C3): + DEV_CASE(I2C4): + DEV_CASE(I2C5): + DEV_CASE(I2C6): + DEV_CASE(I2C7): + DEV_CASE(SIO_DMA2): + DEV_CASE(PWM1): + DEV_CASE(PWM2): + DEV_CASE(HSUART1): + DEV_CASE(HSUART2): + DEV_CASE(SPI): + offset = 0x80; + break; + DEV_CASE(SATA): + DEV_CASE(XHCI): + DEV_CASE(EHCI): + offset = 0x70; + break; + DEV_CASE(HDA): + DEV_CASE(SMBUS): + offset = 0x50; + break; + DEV_CASE(TXE): + break; + DEV_CASE(PCIE_PORT1): + DEV_CASE(PCIE_PORT2): + DEV_CASE(PCIE_PORT3): + DEV_CASE(PCIE_PORT4): + offset = 0xa0; + break; + } + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + return -1; +} + +/* Common PCI device function disable. */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Place device in D3Hot */ + if (place_device_in_d3hot(dev) < 0) { + printk(BIOS_WARNING, + "Could not place %02x.%01x into D3Hot. " + "Keeping device visible.\n", slot, func); + return; + } + /* Disable this device if possible */ + sc_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, .init = NULL, - .enable = NULL, + .enable = southcluster_enable_dev, .scan_bus = NULL, .ops_pci = &soc_pci_ops, };

1 0

Patch set updated for coreboot: de34fb7 baytrail: use MCRX in iosf access functions
by Aaron Durbin 24 Feb '14

24 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4909 -gerrit commit de34fb79f122b4bfc37febb74a834d518ee1a8e8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 10:57:31 2013 -0500 baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initlaized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 1 + src/soc/intel/baytrail/iosf.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 920061f..7f0c7f5 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -45,6 +45,7 @@ #define IOSF_OPCODE(x) ((x) << 24) #define IOSF_PORT(x) ((0xff & (x)) << 16) #define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) (((~0xff) & (x))) #define IOSF_BYTE_EN_0 0x10 #define IOSF_BYTE_EN_1 0x20 #define IOSF_BYTE_EN_2 0x40 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index b9f1531..b050eba 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -47,6 +47,7 @@ uint32_t iosf_bunit_read(int reg) uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -57,6 +58,7 @@ void iosf_bunit_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } @@ -66,6 +68,7 @@ uint32_t iosf_dunit_read(int reg) IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -81,6 +84,7 @@ uint32_t iosf_dunit_ch1_read(int reg) IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -92,6 +96,7 @@ void iosf_dunit_write(int reg, uint32_t val) IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } @@ -101,6 +106,7 @@ uint32_t iosf_punit_read(int reg) IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -112,5 +118,6 @@ void iosf_punit_write(int reg, uint32_t val) IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); }

1 0

Patch set updated for coreboot: 40bf4bd baytrail: use common code for iosf accessors
by Aaron Durbin 24 Feb '14

24 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4922 -gerrit commit 40bf4bdfd188be7588a8a2e1f76ab22c665580de Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 31 11:58:32 2013 -0500 baytrail: use common code for iosf accessors The same sequence is used regardless of the port being read or written. Therefore, use the same implementation for reading or writing to a port. BUG=None BRANCH=None TEST=Built and booted through depthcharge. Dev and recovery screens still work. Nothing bizarre in console output. Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175441 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/iosf.c | 115 +++++++++++++++--------------------------- 1 file changed, 41 insertions(+), 74 deletions(-) diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 8016446..a7f7a90 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -42,35 +42,42 @@ static inline uint32_t read_iosf_reg(int reg) } #endif -uint32_t iosf_bunit_read(int reg) +/* Common sequences for all the port accesses. */ +static uint32_t iosf_read_port(uint32_t cr, int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; - + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } -void iosf_bunit_write(int reg, uint32_t val) +static void iosf_write_port(uint32_t cr, int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; - + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } +uint32_t iosf_bunit_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | + IOSF_PORT(IOSF_PORT_BUNIT); + return iosf_read_port(cr, reg); +} + +void iosf_bunit_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | + IOSF_PORT(IOSF_PORT_BUNIT); + iosf_write_port(cr, reg, val); +} + uint32_t iosf_dunit_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_SYSMEMC); + return iosf_read_port(cr, reg); } uint32_t iosf_dunit_ch0_read(int reg) @@ -81,109 +88,69 @@ uint32_t iosf_dunit_ch0_read(int reg) uint32_t iosf_dunit_ch1_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_DUNIT_CH1); + return iosf_read_port(cr, reg); } void iosf_dunit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_SYSMEMC); + iosf_write_port(cr, reg, val); } uint32_t iosf_punit_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) | - IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_PMC); + return iosf_read_port(cr, reg); } void iosf_punit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | - IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_PMC); + iosf_write_port(cr, reg, val); } uint32_t iosf_usbphy_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_USBPHY); + return iosf_read_port(cr, reg); } void iosf_usbphy_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_USBPHY); + return iosf_write_port(cr, reg, val); } uint32_t iosf_ushphy_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_USHPHY); + return iosf_read_port(cr, reg); } void iosf_ushphy_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_USHPHY); + return iosf_write_port(cr, reg, val); } uint32_t iosf_lpss_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_LPSS); + return iosf_read_port(cr, reg); } void iosf_lpss_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_LPSS); + return iosf_write_port(cr, reg, val); }

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coreboot-gerrit February 2014