coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 1b322a8 rambi: Enable internal keyboard
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4915 -gerrit commit 1b322a8e40842275ef04d453541707b4009e2534 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 31 10:10:20 2013 -0700 rambi: Enable internal keyboard The EC LPC init function needs to run to enable the internal keyboard. I needed this to confirm that it is just USB keyboards that are causing all sorts of issues. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=boot to recovery screen and hit tab Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175207 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 10 +++++++++- src/soc/intel/baytrail/southcluster.c | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index e7f86ce..66d98ed 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -38,7 +38,15 @@ chip soc/intel/baytrail device pci 1e.3 off end # HSUART1 device pci 1e.4 on end # HSUART2 device pci 1e.5 on end # SPI - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on + chip ec/google/chromeec + # We only have one init function that + # we need to call to initialize the + # keyboard part of the EC. + device pnp ff.1 on # dummy address + end + end + end # LPC Bridge device pci 1f.3 off end # SMBus end end diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index b16a9cf..a3a1a22 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -321,7 +321,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = NULL, .enable = southcluster_enable_dev, - .scan_bus = NULL, + .scan_bus = scan_static_bus, .ops_pci = &soc_pci_ops, };

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Patch set updated for coreboot: 3a55040 rambi: Enable SATA port
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4914 -gerrit commit 3a55040acbb5621d17073ad04f70bbe4568bde55 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Oct 28 16:43:17 2013 -0700 rambi: Enable SATA port Enable first SATA port in Rambi device tree. BUG=chrome-os-partner:23643 TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174916 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 3086ebf..e7f86ce 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -1,4 +1,10 @@ chip soc/intel/baytrail + + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + device cpu_cluster 0 on device lapic 0 on end end

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Patch set updated for coreboot: 877ea49 baytrail: Add SATA driver
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4913 -gerrit commit 877ea49763af80446354cb6de203c169c35b599c Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Mon Oct 28 16:15:02 2013 -0700 baytrail: Add SATA driver Add SATA driver for baytrail platform. BUG=chrome-os-partner:23643 TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: I5c13e03203c8f26d233c7d10af8ff6812c460578 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174914 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/pci_devs.h | 6 +- src/soc/intel/baytrail/baytrail/sata.h | 26 ++++ src/soc/intel/baytrail/chip.h | 10 +- src/soc/intel/baytrail/sata.c | 240 +++++++++++++++++++++++++++++ 5 files changed, 279 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 3e62ccf..ad3f94f 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -33,6 +33,7 @@ smm-y += smihandler.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c +ramstage-y += sata.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index f20102a..6b38a71 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -45,8 +45,10 @@ /* SATA */ #define SATA_DEV 19 #define SATA_FUNC 0 -# define ACHI1_DEVID 0x0f22 -# define ACHI2_DEVID 0x0f23 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 /* xHCI */ #define XHCI_DEV 20 diff --git a/src/soc/intel/baytrail/baytrail/sata.h b/src/soc/intel/baytrail/baytrail/sata.h new file mode 100644 index 0000000..7704c18 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/sata.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_SATA_H +#define BAYTRAIL_SATA_H + +#define SATA_SIRI 0xa0 +#define SATA_SIRD 0xa4 + +#endif diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index b6d3f84..d17474f 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -17,12 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_CHIP_H_ -#define _BAYTRAIL_CHIP_H_ /* The devicetree parser expects chip.h to reside directly in the path * specified by the devicetree. */ +#ifndef _BAYTRAIL_CHIP_H_ +#define _BAYTRAIL_CHIP_H_ + +#include <stdint.h> + struct soc_intel_baytrail_config { + uint8_t sata_port_map; + uint8_t sata_ahci; + uint8_t ide_legacy_combined; }; extern struct chip_operations soc_intel_baytrail_ops; diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c new file mode 100644 index 0000000..28a2f8c --- /dev/null +++ b/src/soc/intel/baytrail/sata.c @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include <baytrail/sata.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include "chip.h" + +typedef struct soc_intel_baytrail_config config_t; + +static inline void sir_write(struct device *dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + +static void sata_init(struct device *dev) +{ + config_t *config = dev->chip_info; + u32 reg32; + u16 reg16; + u8 reg8; + + printk(BIOS_DEBUG, "SATA: Initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); + return; + } + + if (!config->sata_ahci) { + /* Set legacy or native decoding mode */ + if (config->ide_legacy_combined) { + reg8 = pci_read_config8(dev, 0x09); + reg8 &= ~0x5; + pci_write_config8(dev, 0x09, reg8); + } else { + reg8 = pci_read_config8(dev, 0x09); + reg8 |= 0x5; + pci_write_config8(dev, 0x09, reg8); + } + + /* Set capabilities pointer */ + pci_write_config8(dev, 0x34, 0x70); + reg16 = pci_read_config16(dev, 0x70); + reg16 &= ~0xFF00; + pci_write_config16(dev, 0x70, reg16); + } + + /* Primary timing - decode enable */ + reg16 = pci_read_config16(dev, 0x40); + reg16 |= 1 << 15; + pci_write_config16(dev, 0x40, reg16); + + /* Secondary timing - decode enable */ + reg16 = pci_read_config16(dev, 0x42); + reg16 |= 1 << 15; + pci_write_config16(dev, 0x42, reg16); + + /* Port mapping enables */ + reg16 = pci_read_config16(dev, 0x90); + reg16 |= (config->sata_port_map ^ 0x3) << 8; + pci_write_config16(dev, 0x90, reg16); + + /* Port control enables */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x003f; + reg16 |= config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + + if (config->sata_ahci) { + u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + /* Enable CR memory space decoding */ + reg16 = pci_read_config16(dev, 0x04); + reg16 |= 0x2; + pci_write_config16(dev, 0x04, reg16); + + /* Set capability register */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM + reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits + reg32 |= (0x3 << 20); // Gen3 SATA + write32(abar + 0x00, reg32); + + /* Ports enabled */ + reg32 = read32(abar + 0x0c); + reg32 &= (u32)(~0x3f); + reg32 |= config->sata_port_map; + write32(abar + 0xc, reg32); + /* Two extra reads to latch */ + read32(abar + 0x0c); + read32(abar + 0x0c); + + /* Set cap2 - Support devslp */ + reg32 = (1 << 5) | (1 << 4) | (1 << 3); + write32(abar + 0x24, reg32); + + /* Set PxCMD registers */ + reg32 = read32(abar + 0x118); + reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | + (1 << 19) | (1 << 18) | (1 << 1)); + reg32 |= 2; + write32(abar + 0x118, reg32); + + reg32 = read32(abar + 0x198); + reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | + (1 << 19) | (1 << 18) | (1 << 1)); + reg32 |= 2; + write32(abar + 0x198, reg32); + + /* Clear reset features */ + write32(abar + 0xc8, 0); + + /* Enable interrupts */ + reg8 = read8(abar + 0x04); + reg8 |= 0x02; + write8(abar + 0x04, reg8); + + } else { + /* TODO(shawnn): Configure IDE SATA speed regs */ + } + + /* 1.4 us delay after configuring port / enable bits */ + udelay(2); + + /* Enable clock for ports */ + reg32 = pci_read_config32(dev, 0x94); + reg32 |= 0x3f << 24; + pci_write_config32(dev, 0x94, reg32); + reg32 &= (config->sata_port_map ^ 0x3) << 24; + pci_write_config32(dev, 0x94, reg32); + + /* Lock SataGc register */ + reg32 = (0x1 << 31) | (0x7 << 12); + pci_write_config32(dev, 0x98, reg32); +} + +static void sata_enable(device_t dev) +{ + config_t *config = dev->chip_info; + u8 reg8; + u16 reg16; + u32 reg32; + + southcluster_enable_dev(dev); + if (!config) + return; + + /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ + reg16 = pci_read_config16(dev, 0x90); + reg16 &= ~0x03e0; + reg16 |= (config->sata_port_map ^ 0x3) << 8; + if(config->sata_ahci) + reg16 |= 0x60; + pci_write_config16(dev, 0x90, reg16); + + /* Set reg 0x94 before starting configuration */ + reg32 = pci_read_config32(dev, 0x94); + reg32 &= (u32)(~0x1ff); + reg32 |= 0x183; + pci_write_config32(dev, 0x94, reg32); + + /* Set ORM bit */ + reg16 = pci_read_config16(dev, 0x92); + reg16 |= (1 << 15); + pci_write_config16(dev, 0x92, reg16); + + /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ + reg32 = pci_read_config32(dev, 0x98); + reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); + reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | + (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); + pci_write_config32(dev, 0x98, reg32); + + /* CMD reg - set bus master enable (BME) */ + reg8 = pci_read_config8(dev, 0x04); + reg8 |= (1 << 2); + pci_write_config8(dev, 0x04, reg8); + + /* "Test mode registers" */ + sir_write(dev, 0x70, 0x00288301); + sir_write(dev, 0x54, 0x00000300); + sir_write(dev, 0x58, 0x50000000); + /* "OOB Detection Margin */ + sir_write(dev, 0x6c, 0x130C0603); + /* "Gasket Control" */ + sir_write(dev, 0xf4, 0); + + /* PCS - Enable requested SATA ports */ + reg8 = pci_read_config8(dev, 0x92); + reg8 &= ~0x03; + reg8 |= config->sata_port_map; + pci_write_config8(dev, 0x92, reg8); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = sata_enable, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + IDE1_DEVID, IDE2_DEVID, /* IDE */ + AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ + 0, +}; + +static const struct pci_driver baytrail_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: d4746f5 rambi: add all on-board devices
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4912 -gerrit commit d4746f5f3aa536e1b9f2f36e7bd1ce27b67a9fe9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 17:00:07 2013 -0500 rambi: add all on-board devices Add the on-board devices in the SoC to the device tree. Also, disable the unused devices aside from TXE and HDA. Those particular devices cause the system to shut down when they are disabled. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Noted the calls to the southcluster disable function. Change-Id: I482c1c9609833054aeb2948144af54b57d3df086 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174645 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 34 +++++++++++++++++++++++++++++--- 1 file changed, 31 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index c6ea97c..3086ebf 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -3,8 +3,36 @@ chip soc/intel/baytrail device lapic 0 on end end device domain 0 on - device pci 00.0 on end # SoC router - device pci 02.0 on end # GFX - device pci 1f.0 on end # LPC Bridge + device pci 00.0 on end # SoC router + device pci 02.0 on end # GFX + device pci 11.0 off end # SDIO + device pci 12.0 on end # SD + device pci 13.0 on end # SATA + device pci 14.0 on end # XHCI + device pci 15.0 on end # LPE + device pci 17.0 on end # MMC + device pci 18.0 on end # SIO_DMA1 + device pci 18.1 on end # I2C1 + device pci 18.2 on end # I2C2 + device pci 18.3 off end # I2C3 + device pci 18.4 off end # I2C4 + device pci 18.5 on end # I2C5 + device pci 18.6 on end # I2C6 + device pci 18.7 off end # I2C7 + device pci 1a.0 on end # TXE + device pci 1b.0 on end # HDA + device pci 1c.0 on end # PCIE_PORT1 + device pci 1c.1 on end # PCIE_PORT2 + device pci 1c.2 off end # PCIE_PORT3 + device pci 1c.3 off end # PCIE_PORT4 + device pci 1d.0 on end # EHCI + device pci 1e.0 on end # SIO_DMA2 + device pci 1e.1 off end # PWM1 + device pci 1e.2 off end # PWM2 + device pci 1e.3 off end # HSUART1 + device pci 1e.4 on end # HSUART2 + device pci 1e.5 on end # SPI + device pci 1f.0 on end # LPC Bridge + device pci 1f.3 off end # SMBus end end

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Patch set updated for coreboot: 72a62e6 baytrail: increment boot count for elog
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4919 -gerrit commit 72a62e62ce4f370da8a5339bb10cfab885ecbc06 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 15:46:07 2013 -0500 baytrail: increment boot count for elog The elog boot counter in cmos was not being initialized nor incremented. Start doing that in romstage. Since S3 resume is not detected yet the increment is unconditional. BUG=None BRANCH=None TEST=Built and booted through depthcharge multiple times. Noted output such as 'Boot Count incremented to 4'. Change-Id: Ic585d4ad4b3af086e0067e28fe0f35c02979bbd2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174717 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/romstage/romstage.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 9752363..5af9bf4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -28,6 +28,7 @@ #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> #endif +#include <elog.h> #include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> @@ -145,6 +146,10 @@ void romstage_common(struct romstage_params *params) mark_ts(params, timestamp_get()); +#if CONFIG_ELOG_BOOT_COUNT + boot_count_increment(); +#endif + /* Initialize RAM */ raminit(params->mrc_params, 5);

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Patch set updated for coreboot: 8f5d69c baytrail: add GNVS to cbmem and set acpi_slp_type
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4918 -gerrit commit 8f5d69cdf574fb49114764c2e2ca56ee1f623e21 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 15:25:42 2013 -0500 baytrail: add GNVS to cbmem and set acpi_slp_type The ACPI code was previously complaining about not being able to find the GNVS area: 'ACPI: Could not find CBMEM GNVS'. Fix this by adding GNVS area early in start up. This is also the appropriate place to set the acpi_slp_type variable to indicate an S3 resume or not. BUG=chrome-os-partner:22867 BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge. Noted cbmem has 'ACPI GNVS' entry. Change-Id: Ifbca3dd390ebe573730ee204ca4c2f19626dd6b1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174647 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/ramstage.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 896ecfe..ab29190 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -18,6 +18,8 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -25,14 +27,16 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <romstage_handoff.h> #include <stdlib.h> -#include <baytrail/pattrs.h> +#include <baytrail/gpio.h> #include <baytrail/lpc.h> #include <baytrail/msr.h> +#include <baytrail/nvs.h> +#include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> -#include <baytrail/gpio.h> /* Global PATTRS */ DEFINE_PATTRS; @@ -103,6 +107,31 @@ static void fill_in_pattrs(void) fill_in_msr(&attrs->iacore_vids, MSR_IACORE_VIDS); } +static inline void set_acpi_sleep_type(int val) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = val; +#endif +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) { + memset(gnvs, 0, sizeof(global_nvs_t)); + } + set_acpi_sleep_type(0); + return; + } + + set_acpi_sleep_type(3); +} void baytrail_init_pre_device(void) { @@ -119,4 +148,7 @@ void baytrail_init_pre_device(void) /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); + + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); }

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Patch set updated for coreboot: 160d02b baytrail: fix uninitialized acpi structures
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4917 -gerrit commit 160d02b606a45ac51b466b99ef96cf8f8fc883b7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 14:36:11 2013 -0500 baytrail: fix uninitialized acpi structures The callers of the following functions assume the storage area provided by the pointers is initialized. That's not the case as these were just place holders. - void acpi_create_intel_hpet(acpi_hpet_t * hpet); - void acpi_create_serialio_ssdt(acpi_header_t *ssdt); To fix this properly initialize the hpet entry, and just remove the serialio_ssdt function entirely. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge on rambi. Noted no more ACPI errors relating to invalid length. Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174716 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/acpi_tables.c | 7 ---- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/acpi.c | 58 ++++++++++++++++++++++++++++++++ src/soc/intel/baytrail/baytrail/acpi.h | 1 - src/soc/intel/baytrail/baytrail/iomap.h | 1 + src/soc/intel/baytrail/placeholders.c | 4 --- 6 files changed, 60 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 3723021..0b96228 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -274,13 +274,6 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); ALIGN_CURRENT; - printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); - ssdt = (acpi_header_t *)current; - acpi_create_serialio_ssdt(ssdt); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - ALIGN_CURRENT; - printk(BIOS_DEBUG, "current = %lx\n", current); printk(BIOS_INFO, "ACPI: done.\n"); return current; diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index ad3f94f..d414057 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -34,6 +34,7 @@ ramstage-y += smm.c ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c +ramstage-y += acpi.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c new file mode 100644 index 0000000..84d125a --- /dev/null +++ b/src/soc/intel/baytrail/acpi.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <types.h> +#include <string.h> + +#include <baytrail/acpi.h> +#include <baytrail/iomap.h> + +void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; + addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h index 917eb26..b269e44 100644 --- a/src/soc/intel/baytrail/baytrail/acpi.h +++ b/src/soc/intel/baytrail/baytrail/acpi.h @@ -23,7 +23,6 @@ #include <arch/acpi.h> void acpi_create_intel_hpet(acpi_hpet_t * hpet); -void acpi_create_serialio_ssdt(acpi_header_t *ssdt); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h index 9fc8da7..fa34105 100644 --- a/src/soc/intel/baytrail/baytrail/iomap.h +++ b/src/soc/intel/baytrail/baytrail/iomap.h @@ -30,6 +30,7 @@ #define MPHY_BASE_ADDRESS 0xfef00000 #define PUNIT_BASE_ADDRESS 0xfed05000 #define RCBA_BASE_ADDRESS 0xfed1c000 +#define HPET_BASE_ADDRESS 0xfed00000 /* IO Port base */ #define ACPI_BASE_ADDRESS 0x0400 diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c index 63f0fb3..5267927 100644 --- a/src/soc/intel/baytrail/placeholders.c +++ b/src/soc/intel/baytrail/placeholders.c @@ -7,10 +7,6 @@ void generate_cpu_entries(void) {} -void acpi_create_intel_hpet(acpi_hpet_t * hpet) {} - -void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} - unsigned long acpi_fill_mcfg(unsigned long current) { return current; } void smm_init(void) {}

1 0

Patch set updated for coreboot: 145e1b8 baytrail: Add IOSF functions for USBPHY and USHPHY
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4916 -gerrit commit 145e1b87dd086691e564fc7c7df1ef19c28eefc1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 31 08:20:48 2013 -0700 baytrail: Add IOSF functions for USBPHY and USHPHY These are needed for USB2 and USB3 PHY init sequences. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Id284d882034e15eceeaa910b8b73bc0d8d895199 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175227 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 7 ++++++ src/soc/intel/baytrail/iosf.c | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 7f0c7f5..b234552 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -64,6 +64,10 @@ uint32_t iosf_dunit_ch0_read(int reg); uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); +uint32_t iosf_ushphy_read(int reg); +void iosf_ushphy_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -76,6 +80,7 @@ void iosf_punit_write(int reg, uint32_t val); #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -96,6 +101,8 @@ void iosf_punit_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) #define IOSF_OP_READ_USBPHY 0x06 #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_USHPHY 0x06 +#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) #define IOSF_OP_READ_SATAPHY 0x00 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index b050eba..7d420cc 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -121,3 +121,47 @@ void iosf_punit_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_usbphy_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | + IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | + IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} + +uint32_t iosf_ushphy_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | + IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_ushphy_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | + IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +}

1 0

Patch set updated for coreboot: 8e28db9 lenovo/x60: Support digitizer on X60t and X201t.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5239 -gerrit commit 8e28db92229bb4ef3bba2a6681f3893f9e6d7532 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 17:00:46 2014 +0100 lenovo/x60: Support digitizer on X60t and X201t. Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/Kconfig | 4 +- src/mainboard/lenovo/x201/Kconfig | 4 +- src/mainboard/lenovo/x201/acpi_tables.c | 2 + src/mainboard/lenovo/x201/devicetree.cb | 14 +++ src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/lenovo/x60/Kconfig | 3 +- src/mainboard/lenovo/x60/acpi_tables.c | 2 + src/mainboard/lenovo/x60/devicetree.cb | 7 +- src/odm_oem/Kconfig | 2 + src/odm_oem/lenovo/Kconfig | 28 +++++ src/odm_oem/lenovo/Makefile.inc | 1 + src/odm_oem/lenovo/lenovo.h | 3 + src/odm_oem/lenovo/wacom.c | 174 ++++++++++++++++++++++++++++++++ 13 files changed, 239 insertions(+), 7 deletions(-) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index a29fdbf..1de11a8 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -4,7 +4,7 @@ choice prompt "Mainboard model" config BOARD_LENOVO_X60 - bool "ThinkPad X60 / X60s" + bool "ThinkPad X60 / X60s / X60t" help The following X60 series ThinkPad machines have been verified to work correctly: @@ -13,7 +13,7 @@ config BOARD_LENOVO_X60 ThinkPad X60 (Model 1709) config BOARD_LENOVO_X201 - bool "ThinkPad X201" + bool "ThinkPad X201 / X201s / X201t" help Lenovo X201 laptop. Consult wiki for details. diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 8e7ebae..4caf58c 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -18,6 +18,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_WACOM config MAINBOARD_DIR string @@ -29,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MAINBOARD_VERSION string - default "ThinkPad X201" + default "ThinkPad X201 / X201s / X201t" config MAINBOARD_VENDOR string diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 165de0d..981c52e 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -31,6 +31,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "southbridge/intel/ibexpeak/nvs.h" +#include "odm_oem/lenovo/lenovo.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -93,6 +94,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); return (unsigned long)(acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 6c5229b..72dcb30 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -139,6 +139,20 @@ chip northbridge/intel/nehalem end device pci 1f.0 on # PCI-LPC bridge subsystemid 0x17aa 0x2166 + chip superio/nsc/pc87382 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 + end + # IR, not connected + device pnp 164e.2 off end + # GPIO, not connected + device pnp 164e.7 off end + # DLPC, not connected + device pnp 164e.19 off end + end end device pci 1f.2 on # IDE/SATA subsystemid 0x17aa 0x2168 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 07687b8..565c9a5 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + COMA_LPC_EN | GAMEL_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..8c1417e 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select DRIVERS_LENOVO_WACOM config MAINBOARD_DIR string @@ -41,7 +42,7 @@ config DCACHE_RAM_SIZE config MAINBOARD_PART_NUMBER string - default "ThinkPad X60 / X60s" + default "ThinkPad X60 / X60s / X60t" config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index f6ed4ae..d6ce4ba 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -29,6 +29,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "odm_oem/lenovo/lenovo.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC @@ -86,6 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 3880f18..5b4e37f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -127,8 +127,11 @@ chip northbridge/intel/i945 io 0x60 = 0x2f8 end - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 + device pnp 164e.3 on # Digitizer + io 0x60 = 0x200 + irq 0x29 = 0xb0 + irq 0x70 = 0x5 + irq 0xf0 = 0x82 end device pnp 164e.7 on # GPIO diff --git a/src/odm_oem/Kconfig b/src/odm_oem/Kconfig index 6eb2993..e1f5243 100644 --- a/src/odm_oem/Kconfig +++ b/src/odm_oem/Kconfig @@ -1,3 +1,5 @@ menu "OEM / ODM" +source "src/odm_oem/lenovo/Kconfig" + endmenu diff --git a/src/odm_oem/lenovo/Kconfig b/src/odm_oem/lenovo/Kconfig new file mode 100644 index 0000000..5056b1e --- /dev/null +++ b/src/odm_oem/lenovo/Kconfig @@ -0,0 +1,28 @@ +config DRIVERS_LENOVO_WACOM + bool + default n + +if DRIVERS_LENOVO_WACOM + +choice + prompt "Digitizer" + +config DIGITIZER_AUTODETECT + bool "Autodetect" + help + The presence of digitizer is inferred from model number stored in + AT24RF chip. + +config DIGITIZER_PRESENT + bool "Present" + help + The digitizer is assumed to be present. + +config DIGITIZER_ABSENT + bool "Absent" + help + The digitizer is assumed to be absent. + +endchoice + +endif diff --git a/src/odm_oem/lenovo/Makefile.inc b/src/odm_oem/lenovo/Makefile.inc index 18e2110..bbb39d4 100644 --- a/src/odm_oem/lenovo/Makefile.inc +++ b/src/odm_oem/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-y += serials.c +ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c diff --git a/src/odm_oem/lenovo/lenovo.h b/src/odm_oem/lenovo/lenovo.h index 6824eb6..25074bc 100644 --- a/src/odm_oem/lenovo/lenovo.h +++ b/src/odm_oem/lenovo/lenovo.h @@ -1 +1,4 @@ const char *lenovo_mainboard_partnumber(void); +int drivers_lenovo_is_wacom_present(void); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, + int have_dock_serial); diff --git a/src/odm_oem/lenovo/wacom.c b/src/odm_oem/lenovo/wacom.c new file mode 100644 index 0000000..c5be6ed --- /dev/null +++ b/src/odm_oem/lenovo/wacom.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2, or (at your + * option) any later version, of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pnp.h> +#include <string.h> +#include "odm_oem/lenovo/lenovo.h" + +const char tablet_numbers[][5] = { + /* X60t. */ + "6363", "6364", "6365", "6366", + "6367", "6368", "7762", "7763", + "7764", "7767", "7768", "7769", + /* X201t. */ + "0053", "0831", "2985", "3093", + "3113", "3144", "3239", "4184", + "7448", "7449", "7450", "7453", + "2263", "2266", +}; + +int +drivers_lenovo_is_wacom_present(void) +{ +#if IS_ENABLED(CONFIG_DIGITIZER_PRESENT) + printk (BIOS_INFO, "Digitizer state forced as present\n"); + return 1; +#elif IS_ENABLED(CONFIG_DIGITIZER_ABSENT) + printk (BIOS_INFO, "Digitizer state forced as absent\n"); + return 0; +#else + const char *pn; + int i; + static int result = -1; + device_t superio; + u8 sioid; + + if (result != -1) + return result; + superio = dev_find_slot_pnp (0x164e, 3); + if (!superio) { + printk (BIOS_INFO, "No Super I/O, skipping wacom\n"); + return (result = 0); + } + + /* Probe ID. */ + sioid = pnp_read_config(superio, 0x20); + if (sioid == 0xff) { + printk (BIOS_INFO, "Super I/O probe failed, skipping wacom\n"); + return (result = 0); + } + + pn = lenovo_mainboard_partnumber(); + if (!pn) + return 0; + printk (BIOS_DEBUG, "Lenovo P/N is %s\n", pn); + for (i = 0; i < sizeof (tablet_numbers) / sizeof (tablet_numbers[0]); + i++) + if (memcmp (tablet_numbers[i], pn, 4) == 0) { + printk (BIOS_DEBUG, "Lenovo P/N %s is a tablet\n", pn); + return (result = 1); + } + printk (BIOS_DEBUG, "Lenovo P/N %s is not a tablet\n", pn); + return (result = 0); +#endif +} + +void +drivers_lenovo_serial_ports_ssdt_generate(const char *scope, + int have_dock_serial) +{ + int scopelen, devicelen, reslen, methodlen; + + scopelen = acpigen_write_scope(scope); + + if (drivers_lenovo_is_wacom_present()) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("DTR"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("WACF004"); + + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x200, 0x200, 1, 8, 1); + reslen += acpigen_write_irq(0x20); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + + acpigen_patch_len(methodlen); + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + + if (have_dock_serial) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("COMA"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("PNP0501"); + devicelen += acpigen_write_name("_UID"); + /* Byte */ + devicelen += acpigen_write_byte(0x2); + + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); + reslen += acpigen_write_irq(0x10); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + acpigen_patch_len(methodlen); + + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + + acpigen_patch_len(scopelen - 1); +}

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Patch set updated for coreboot: 25db36a acpigen: Add acpigen_write_irq.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5241 -gerrit commit 25db36a5f88f0e8b05a9c7b19adb7a0e01aef4af Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 18:57:17 2014 +0100 acpigen: Add acpigen_write_irq. Change-Id: Iba52dc2d52b7ac9a65d1d17b43e7204f5ede373e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 15 +++++++++++++++ src/arch/x86/include/arch/acpigen.h | 1 + 2 files changed, 16 insertions(+) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index d149129..b2a17cb 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -623,6 +623,21 @@ int acpigen_write_register(acpi_addr_t *addr) return 15; } +int acpigen_write_irq(u16 mask) +{ + /* + * acpi 3.0b section 6.4.2.1: IRQ Descriptor + * Byte 0: + * Bit7 : 0 => small item + * Bit6-3: 0100 (0x4) => IRQ port descriptor + * Bit2-0: 010 (0x2) => 2 Bytes long + */ + acpigen_emit_byte(0x22); + acpigen_emit_byte(mask & 0xff); + acpigen_emit_byte((mask >> 8) & 0xff); + return 3; +} + int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index eaa29a5..3217dbe 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -63,6 +63,7 @@ int acpigen_write_resourcetemplate_header(void); int acpigen_write_resourcetemplate_footer(int len); int acpigen_write_mainboard_resource_template(void); int acpigen_write_mainboard_resources(const char *scope, const char *name); +int acpigen_write_irq(u16 mask); int get_cst_entries(acpi_cstate_t **);

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coreboot-gerrit February 2014