coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

1 participants
1135 discussions

New patch to review for coreboot: 6acf561 coreboot: introduce arch_payload_run()
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5300 -gerrit commit 6acf56103bfcddeb42d29f2cd4454374bba63d4b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Feb 24 22:27:39 2014 -0600 coreboot: introduce arch_payload_run() The selfboot() function relied on global variables within the selfboot.c compilation unit. Now that the bounce buffer is a part of struct payload use a new architecture-specific arch_payload_run() function for jumping to the payload. selfboot() can then be removed. Change-Id: Icec74942e94599542148561b3311ce5096ac5ea5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/armv7/boot.c | 7 ++++--- src/arch/armv7/include/arch/stages.h | 1 - src/arch/x86/boot/boot.c | 19 +++++++++++++------ src/arch/x86/include/arch/stages.h | 1 - src/include/payload_loader.h | 4 +++- src/lib/loaders/load_and_run_payload.c | 2 +- src/lib/selfboot.c | 7 ------- 7 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/boot.c b/src/arch/armv7/boot.c index 6774802..94a645f 100644 --- a/src/arch/armv7/boot.c +++ b/src/arch/armv7/boot.c @@ -19,9 +19,10 @@ #include <console/console.h> #include <arch/stages.h> +#include <payload_loader.h> -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) +void arch_payload_run(struct payload *payload) { - printk(BIOS_SPEW, "entry = %p\n", entry); - stage_exit(entry); + printk(BIOS_SPEW, "entry = %p\n", payload->entry); + stage_exit(payload->entry); } diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/armv7/include/arch/stages.h index 3fd54b9..671c02b 100644 --- a/src/arch/armv7/include/arch/stages.h +++ b/src/arch/armv7/include/arch/stages.h @@ -24,6 +24,5 @@ extern void main(void); void stage_entry(void) __attribute__((section(".text.stage_entry.armv7"))); void stage_exit(void *); -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); #endif diff --git a/src/arch/x86/boot/boot.c b/src/arch/x86/boot/boot.c index 3ef46a5..54c2b23 100644 --- a/src/arch/x86/boot/boot.c +++ b/src/arch/x86/boot/boot.c @@ -1,12 +1,12 @@ #include <console/console.h> #include <arch/stages.h> +#include <payload_loader.h> #include <ip_checksum.h> #include <string.h> -#if CONFIG_RELOCATABLE_RAMSTAGE /* When the ramstage is relocatable the elf loading ensures an elf image cannot * be loaded over the ramstage code. */ -void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) +static void jmp_payload_no_bounce_buffer(void *entry) { /* Jump to kernel */ __asm__ __volatile__( @@ -22,8 +22,8 @@ void jmp_to_elf_entry(void *entry, unsigned long unused1, unsigned long unused2) "r" (entry) ); } -#else -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) + +static void jmp_payload(void *entry, unsigned long buffer, unsigned long size) { extern unsigned char _ram_seg, _eram_seg; unsigned long lb_start, lb_size; @@ -122,6 +122,13 @@ void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size) "ri"(0), "ri" (0) ); } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ - +void arch_payload_run(const struct payload *payload) +{ + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + jmp_payload_no_bounce_buffer(payload->entry); + } else { + jmp_payload(payload->entry, (uintptr_t)payload->bounce.data, + payload->bounce.size); + } +} diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 91d0db6..4eae698 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -23,7 +23,6 @@ #include <arch/cpu.h> void asmlinkage copy_and_run(void); -void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size); static inline void stage_exit(void *entry) { diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 0c526c2..0715d37 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -44,6 +44,9 @@ struct payload *payload_load(void); /* Run the loaded payload. */ void payload_run(const struct payload *payload); +/* architecture specific function to run payload. */ +void arch_payload_run(const struct payload *payload); + /* Payload loading operations. */ struct payload_loader_ops { const char *name; @@ -57,6 +60,5 @@ struct payload_loader_ops { /* Defined in src/lib/selfboot.c */ struct lb_memory; void *selfload(struct lb_memory *mem, struct payload *payload); -void selfboot(void *entry); #endif /* PAYLOAD_LOADER_H */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 54ee252..cab437d 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -93,5 +93,5 @@ void payload_run(const struct payload *payload) */ checkstack(_estack, 0); - selfboot(payload->entry); + arch_payload_run(payload); } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index ba07480..6dc3a75 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -19,7 +19,6 @@ */ #include <arch/byteorder.h> -#include <arch/stages.h> #include <console/console.h> #include <cpu/cpu.h> #include <boot/coreboot_tables.h> @@ -526,9 +525,3 @@ void *selfload(struct lb_memory *mem, struct payload *payload) out: return NULL; } - -void selfboot(void *entry) -{ - /* Jump to kernel */ - jmp_to_elf_entry(entry, bounce_buffer, bounce_size); -}

1 0

New patch to review for coreboot: 27deff6 selfboot: store bounce buffer in struct payload
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5299 -gerrit commit 27deff64db1f803bee4f069539329924f132c987 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Feb 24 22:11:45 2014 -0600 selfboot: store bounce buffer in struct payload In order to break the dependency on selfboot for jumping to payload the bounce buffer location needs to be communicated. Therefore, add the bounce buffer to struct payload. Change-Id: I9d9396e5c5bfba7a63940227ee0bdce6cba39578 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/payload_loader.h | 6 ++++-- src/lib/selfboot.c | 26 +++++++++++++++----------- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 1dc06c7..0c526c2 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -22,14 +22,16 @@ #include <stdint.h> #include <stddef.h> -struct payload_backing_store { +struct buffer_area { void *data; size_t size; }; struct payload { const char *name; - struct payload_backing_store backing_store; + struct buffer_area backing_store; + /* Used when payload wants memory coreboot ramstage is running at. */ + struct buffer_area bounce; void *entry; }; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index bd1206f..ba07480 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -74,22 +74,22 @@ struct segment { static unsigned long bounce_size, bounce_buffer; -#if CONFIG_RELOCATABLE_RAMSTAGE -static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) -{ - /* When the ramstage is relocatable there is no need for a bounce - * buffer. All payloads should not overlap the ramstage. - */ - bounce_buffer = ~0UL; - bounce_size = 0; -} -#else static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) { unsigned long lb_size; unsigned long mem_entries; unsigned long buffer; int i; + + /* When the ramstage is relocatable there is no need for a bounce + * buffer. All payloads should not overlap the ramstage. + */ + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + bounce_buffer = ~0UL; + bounce_size = 0; + return; + } + lb_size = lb_end - lb_start; /* Plus coreboot size so I have somewhere * to place a copy to return to. @@ -120,7 +120,6 @@ static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) bounce_buffer = buffer; bounce_size = req_size; } -#endif /* CONFIG_RELOCATABLE_RAMSTAGE */ static int valid_area(struct lb_memory *mem, unsigned long buffer, unsigned long start, unsigned long len) @@ -417,6 +416,11 @@ static int load_self_segments( printk(BIOS_ERR, "Could not find a bounce buffer...\n"); return 0; } + + /* Update the payload's bounce buffer data used when loading. */ + payload->bounce.data = (void *)(uintptr_t)bounce_buffer; + payload->bounce.size = bounce_size; + for(ptr = head->next; ptr != head; ptr = ptr->next) { /* Verify the memory addresses in the segment are valid */ if (!valid_area(mem, bounce_buffer, ptr->s_dstaddr, ptr->s_memsz))

1 0

New patch to review for coreboot: 9c852fd coreboot: use struct payload for selfload()
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5298 -gerrit commit 9c852fd7d1979c7689ebfe05e21d3af77aacbf0f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Feb 24 21:50:24 2014 -0600 coreboot: use struct payload for selfload() In order to encapsulate more data for self loading use struct payload as the type. That way modifications to what is needed for payload loading does not introduce more global variables. Change-Id: I5b8facd7881e397ca7de1c04cec747fc1dce2d5f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/payload_loader.h | 3 +-- src/lib/loaders/load_and_run_payload.c | 2 +- src/lib/selfboot.c | 10 ++++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 27b62d3..1dc06c7 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -54,8 +54,7 @@ struct payload_loader_ops { /* Defined in src/lib/selfboot.c */ struct lb_memory; -struct cbfs_payload; -void *selfload(struct lb_memory *mem, struct cbfs_payload *payload); +void *selfload(struct lb_memory *mem, struct payload *payload); void selfboot(void *entry); #endif /* PAYLOAD_LOADER_H */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 8be4e3c..54ee252 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -65,7 +65,7 @@ struct payload *payload_load(void) return NULL; mem = get_lb_mem(); - entry = selfload(mem, payload->backing_store.data); + entry = selfload(mem, payload); if (entry == NULL) return NULL; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 6f200fa..bd1206f 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -302,14 +302,16 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( struct segment *head, struct lb_memory *mem, - struct cbfs_payload *payload, uintptr_t *entry) + struct payload *payload, uintptr_t *entry) { struct segment *new; struct segment *ptr; struct cbfs_payload_segment *segment, *first_segment; + struct cbfs_payload *cbfs_payload; + cbfs_payload = payload->backing_store.data; memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &payload->segments; + first_segment = segment = &cbfs_payload->segments; while(1) { printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); @@ -394,7 +396,7 @@ static int build_self_segment_list( static int load_self_segments( struct segment *head, struct lb_memory *mem, - struct cbfs_payload *payload) + struct payload *payload) { struct segment *ptr; @@ -500,7 +502,7 @@ static int load_self_segments( return 1; } -void *selfload(struct lb_memory *mem, struct cbfs_payload *payload) +void *selfload(struct lb_memory *mem, struct payload *payload) { uintptr_t entry = 0; struct segment head;

1 0

New patch to review for coreboot: c1e7d89 coreboot: move common code to payload_run() from selfboot()
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5297 -gerrit commit c1e7d8920d04001191192af6cc15c2e36c81d7d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Feb 24 21:24:28 2014 -0600 coreboot: move common code to payload_run() from selfboot() The selfboot() routine was perfoming most of the common teardown and stack checking infrastructure. Move that code into payload_run() to prepare removal of the selfboot() function. Change-Id: I29f2a5cfcc692f7a0fe2656cb1cda18158c49c6e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/loaders/load_and_run_payload.c | 16 ++++++++++++++++ src/lib/selfboot.c | 19 ------------------- 2 files changed, 16 insertions(+), 19 deletions(-) diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index dba5898..8be4e3c 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -21,7 +21,10 @@ #include <stdlib.h> #include <console/console.h> #include <boot/coreboot_tables.h> +#include <fallback.h> +#include <lib.h> #include <payload_loader.h> +#include <timestamp.h> extern const struct payload_loader_ops vboot_payload_loader; extern const struct payload_loader_ops cbfs_payload_loader; @@ -77,5 +80,18 @@ void payload_run(const struct payload *payload) if (payload == NULL) return; + /* Reset to booting from this image as late as possible */ + boot_successful(); + + printk(BIOS_DEBUG, "Jumping to boot code at %p\n", payload->entry); + post_code(POST_ENTER_ELF_BOOT); + + timestamp_add_now(TS_SELFBOOT_JUMP); + + /* Before we go off to run the payload, see if + * we stayed within our bounds. + */ + checkstack(_estack, 0); + selfboot(payload->entry); } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index c0986d1..6f200fa 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -22,16 +22,12 @@ #include <arch/stages.h> #include <console/console.h> #include <cpu/cpu.h> -#include <fallback.h> #include <boot/coreboot_tables.h> #include <stdint.h> #include <stdlib.h> #include <string.h> #include <cbfs.h> #include <lib.h> -#if CONFIG_COLLECT_TIMESTAMPS -#include <timestamp.h> -#endif #include <payload_loader.h> /* Maximum physical address we can use for the coreboot bounce buffer. */ @@ -527,21 +523,6 @@ out: void selfboot(void *entry) { - /* Reset to booting from this image as late as possible */ - boot_successful(); - - printk(BIOS_DEBUG, "Jumping to boot code at %p\n", entry); - post_code(POST_ENTER_ELF_BOOT); - -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_add_now(TS_SELFBOOT_JUMP); -#endif - - /* Before we go off to run the payload, see if - * we stayed within our bounds. - */ - checkstack(_estack, 0); - /* Jump to kernel */ jmp_to_elf_entry(entry, bounce_buffer, bounce_size); }

1 0

New patch to review for coreboot: 2464f16 coreboot: infrastructure for loading payloads
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5296 -gerrit commit 2464f16875c60a408e0052a11707fccabe45b074 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Feb 24 14:56:34 2014 -0600 coreboot: infrastructure for loading payloads A payload can be loaded either from a vboot region or from cbfs. Provide a common place for choosing where the payload is loaded from. Additionally, place the logic in the 'loaders' directory similarly to the ramstage loader infrastructure. Change-Id: I6b0034ea5ebd04a3d058151819ac77a126a6bfe2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbfs.h | 6 --- src/include/payload_loader.h | 61 +++++++++++++++++++++++ src/lib/cbfs.c | 19 -------- src/lib/hardwaremain.c | 22 ++++----- src/lib/loaders/Makefile.inc | 2 + src/lib/loaders/cbfs_payload_loader.c | 45 +++++++++++++++++ src/lib/loaders/load_and_run_payload.c | 81 +++++++++++++++++++++++++++++++ src/lib/selfboot.c | 1 + src/vendorcode/google/chromeos/chromeos.c | 25 +++++++++- src/vendorcode/google/chromeos/chromeos.h | 1 - 10 files changed, 223 insertions(+), 40 deletions(-) diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 9ce862b..ebdbf43 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -54,7 +54,6 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, uint16_t device, void * dest); -void *cbfs_load_payload(struct cbfs_media *media, const char *name); void *cbfs_load_stage(struct cbfs_media *media, const char *name); /* Simple buffer for streaming media. */ @@ -75,11 +74,6 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, // Utility functions int run_address(void *f); -/* Defined in src/lib/selfboot.c */ -struct lb_memory; -void *selfload(struct lb_memory *mem, struct cbfs_payload *payload); -void selfboot(void *entry); - /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h new file mode 100644 index 0000000..27b62d3 --- /dev/null +++ b/src/include/payload_loader.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#ifndef PAYLOAD_LOADER_H +#define PAYLOAD_LOADER_H + +#include <stdint.h> +#include <stddef.h> + +struct payload_backing_store { + void *data; + size_t size; +}; + +struct payload { + const char *name; + struct payload_backing_store backing_store; + void *entry; +}; + +/* + * Load payload into memory and return pointer to payload structure. Returns + * NULL on error. + */ +struct payload *payload_load(void); + +/* Run the loaded payload. */ +void payload_run(const struct payload *payload); + +/* Payload loading operations. */ +struct payload_loader_ops { + const char *name; + /* + * Fill in payload_backing_store structure. Return 0 on success, < 0 + * if failure. + */ + int (*locate)(struct payload *payload); +}; + +/* Defined in src/lib/selfboot.c */ +struct lb_memory; +struct cbfs_payload; +void *selfload(struct lb_memory *mem, struct cbfs_payload *payload); +void selfboot(void *entry); + +#endif /* PAYLOAD_LOADER_H */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 99eeac8..dc08937 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -65,12 +65,6 @@ #include "cbfs_core.c" -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <vendorcode/google/chromeos/chromeos.h> -#else -static inline void *vboot_get_payload(int *len) { return NULL; } -#endif - #ifndef __SMM__ static inline int tohex4(unsigned int c) { @@ -160,19 +154,6 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) return (void *) entry; } -void *cbfs_load_payload(struct cbfs_media *media, const char *name) -{ - struct cbfs_payload *payload; - - payload = vboot_get_payload(NULL); - if (payload != NULL) - return payload; - - payload = (struct cbfs_payload *)cbfs_get_file_content( - media, name, CBFS_TYPE_PAYLOAD, NULL); - return payload; -} - /* Simple buffer */ void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index fed153b..d90e0f6 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -32,7 +32,7 @@ #include <stdlib.h> #include <reset.h> #include <boot/tables.h> -#include <cbfs.h> +#include <payload_loader.h> #include <lib.h> #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> @@ -226,30 +226,26 @@ static boot_state_t bs_write_tables(void *arg) static boot_state_t bs_payload_load(void *arg) { - void *payload; - void *entry; + struct payload *payload; timestamp_add_now(TS_LOAD_PAYLOAD); - payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA, - CONFIG_CBFS_PREFIX "/payload"); - if (! payload) - die("Could not find a payload\n"); - - entry = selfload(get_lb_mem(), payload); + payload = payload_load(); - if (! entry) + if (! payload) die("Could not load payload\n"); /* Pass the payload to the next state. */ - boot_states[BS_PAYLOAD_BOOT].arg = entry; + boot_states[BS_PAYLOAD_BOOT].arg = payload; return BS_PAYLOAD_BOOT; } -static boot_state_t bs_payload_boot(void *entry) +static boot_state_t bs_payload_boot(void *arg) { - selfboot(entry); + struct payload *payload = arg; + + payload_run(payload); printk(BIOS_EMERG, "Boot failed"); /* Returning from this state will fail because the following signals diff --git a/src/lib/loaders/Makefile.inc b/src/lib/loaders/Makefile.inc index eceaa00..356e47e 100644 --- a/src/lib/loaders/Makefile.inc +++ b/src/lib/loaders/Makefile.inc @@ -19,3 +19,5 @@ romstage-y += cbfs_ramstage_loader.c romstage-y += load_and_run_ramstage.c +ramstage-y += cbfs_payload_loader.c +ramstage-y += load_and_run_payload.c diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c new file mode 100644 index 0000000..c115572 --- /dev/null +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <payload_loader.h> + +static int cbfs_locate_payload(struct payload *payload) +{ + void *buffer; + size_t size; + const int type = CBFS_TYPE_PAYLOAD; + + buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, + type, &size); + + if (buffer == NULL) + return -1; + + payload->backing_store.data = buffer; + payload->backing_store.size = size; + + return 0; +} + +const struct payload_loader_ops cbfs_payload_loader = { + .name = "CBFS", + .locate = cbfs_locate_payload, +}; + diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c new file mode 100644 index 0000000..dba5898 --- /dev/null +++ b/src/lib/loaders/load_and_run_payload.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <console/console.h> +#include <boot/coreboot_tables.h> +#include <payload_loader.h> + +extern const struct payload_loader_ops vboot_payload_loader; +extern const struct payload_loader_ops cbfs_payload_loader; + +static const struct payload_loader_ops *payload_ops[] = { +#if CONFIG_VBOOT_VERIFY_FIRMWARE + &vboot_payload_loader, +#endif + &cbfs_payload_loader, +}; + +static struct payload global_payload = { + .name = CONFIG_CBFS_PREFIX "/payload", +}; + +struct payload *payload_load(void) +{ + int i; + void *entry; + struct lb_mem *mem; + const struct payload_loader_ops *ops; + struct payload *payload = &global_payload; + + for (i = 0; i < ARRAY_SIZE(payload_ops); i++) { + ops = payload_ops[i]; + if (ops->locate(payload) < 0) { + printk(BIOS_DEBUG, "%s: could not locate payload.\n", + ops->name); + continue; + } + printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", + ops->name, payload->backing_store.data, + payload->backing_store.size); + break; + } + + if (i == ARRAY_SIZE(payload_ops)) + return NULL; + + mem = get_lb_mem(); + entry = selfload(mem, payload->backing_store.data); + + if (entry == NULL) + return NULL; + + payload->entry = entry; + + return payload; +} + +void payload_run(const struct payload *payload) +{ + if (payload == NULL) + return; + + selfboot(payload->entry); +} diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 222eae2..c0986d1 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -32,6 +32,7 @@ #if CONFIG_COLLECT_TIMESTAMPS #include <timestamp.h> #endif +#include <payload_loader.h> /* Maximum physical address we can use for the coreboot bounce buffer. */ #ifndef MAX_ADDR diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 54fe8db..e917ba1 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -82,7 +82,9 @@ int recovery_mode_enabled(void) } #if CONFIG_VBOOT_VERIFY_FIRMWARE -void *vboot_get_payload(size_t *len) +#include <payload_loader.h> + +static void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; struct firmware_component *fwc; @@ -109,6 +111,27 @@ void *vboot_get_payload(size_t *len) return (void *)fwc->address; } +static int vboot_locate_payload(struct payload *payload) +{ + void *buffer; + size_t size; + + buffer = vboot_get_payload(&size); + + if (buffer == NULL) + return -1; + + payload->backing_store.data = buffer; + payload->backing_store.size = size; + + return 0; +} + +const struct payload_loader_ops vboot_payload_loader = { + .name = "VBOOT", + .locate = vboot_locate_payload, +}; + int vboot_get_handoff_info(void **addr, uint32_t *size) { struct vboot_handoff *vboot_handoff; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 0359c91..7fe8f06 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -47,7 +47,6 @@ int recovery_mode_enabled(void); void init_chromeos(int bootmode); #if CONFIG_VBOOT_VERIFY_FIRMWARE -void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); #endif

1 0

Patch set updated for coreboot: 98eda4b baytrail: add support for disabling south cluster pci devices
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4911 -gerrit commit 98eda4b2b7da8eb9acb35ebab681564e16f0f65f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 16:37:10 2013 -0500 baytrail: add support for disabling south cluster pci devices When the southcluster pci devices are listed in the devicetree add the ability to perform the proper disabling sequence for turning off devices. This only turns off the pci device interface as well as put the device into D3Hot. It is not yet known how to put the TXE device into D3Hot so it's currently not possible to disable that device. Also, expose the southcluster_enable_dev() function so that other devices can call this if they require doing specific things before disabling the device. The southcluster_enable_dev() is only called on devices found in the devicetree and if they currently have no ops associated with them. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Interrogated output to ensure devices were being properly disabled. Change-Id: I537ddcb9379907af2fe012948542b6150a8bf7c5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174644 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 4 + src/soc/intel/baytrail/baytrail/pmc.h | 33 +++++ src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.c | 8 +- src/soc/intel/baytrail/southcluster.c | 204 ++++++++++++++++++++++++++++- 5 files changed, 247 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 8b0335e..f20102a 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -102,12 +102,16 @@ /* PCIe Ports */ #define PCIE_DEV 28 +# define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 # define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 # define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 # define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 # define PCIE_PORT4_DEVID 0x0f4e diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index e0e5cff..51f8887 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -33,6 +33,39 @@ # define IGNORE_HPET (1 << 21) # define CF9GR (1 << 20) # define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index eaa8f6b..4fa6ddd 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -27,6 +27,7 @@ void baytrail_init_pre_device(void); void baytrail_init_cpus(device_t dev); void set_max_freq(void); +void southcluster_enable_dev(device_t dev); #if CONFIG_HAVE_REFCODE_BLOB void baytrail_run_reference_code(void); #else diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index 0f686fa..eedae39 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -53,13 +53,17 @@ static struct device_operations cpu_bus_ops = { static void enable_dev(device_t dev) { - printk(BIOS_DEBUG, "enable_dev(%s, %d)\n", - dev_name(dev), dev->path.type); /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } } } diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 32b8799..b16a9cf 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -20,6 +20,7 @@ #include <stdint.h> #include <arch/io.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -29,6 +30,7 @@ #include <baytrail/lpc.h> #include <baytrail/nvs.h> #include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> #include <baytrail/ramstage.h> static inline void @@ -113,12 +115,212 @@ static void sc_read_resources(device_t dev) sc_add_io_resources(dev); } +/* + * Common code for the south cluster devices. + */ + +/* Set bit in function disble register to hide this device. */ +static void sc_disable_devfn(device_t dev) +{ + const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS; + const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2; + uint32_t mask = 0; + uint32_t mask2 = 0; + +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask2 |= name_ ## _DIS + + switch (dev->path.pci.devfn) { + SET_DIS_MASK(SDIO); + break; + SET_DIS_MASK(SD); + break; + SET_DIS_MASK(SATA); + break; + SET_DIS_MASK(XHCI); + /* Disable super speed PHY when XHCI is not available. */ + mask2 |= USH_SS_PHY_DIS; + break; + SET_DIS_MASK(LPE); + break; + SET_DIS_MASK(MMC); + break; + SET_DIS_MASK(SIO_DMA1); + break; + SET_DIS_MASK(I2C1); + break; + SET_DIS_MASK(I2C2); + break; + SET_DIS_MASK(I2C3); + break; + SET_DIS_MASK(I2C4); + break; + SET_DIS_MASK(I2C5); + break; + SET_DIS_MASK(I2C6); + break; + SET_DIS_MASK(I2C7); + break; + SET_DIS_MASK(TXE); + break; + SET_DIS_MASK(HDA); + break; + SET_DIS_MASK(PCIE_PORT1); + break; + SET_DIS_MASK(PCIE_PORT2); + break; + SET_DIS_MASK(PCIE_PORT3); + break; + SET_DIS_MASK(PCIE_PORT4); + break; + SET_DIS_MASK(EHCI); + break; + SET_DIS_MASK(SIO_DMA2); + break; + SET_DIS_MASK(PWM1); + break; + SET_DIS_MASK(PWM2); + break; + SET_DIS_MASK(HSUART1); + break; + SET_DIS_MASK(HSUART2); + break; + SET_DIS_MASK(SPI); + break; + SET_DIS_MASK2(SMBUS); + break; + } + + if (mask != 0) { + write32(func_dis, read32(func_dis) | mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (mask2 != 0) { + write32(func_dis2, read32(func_dis2) | mask2); + /* Ensure posted write hits. */ + read32(func_dis2); + } +} + +static inline void set_d3hot_bits(device_t dev, int offset) +{ + uint32_t reg8; + printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); + reg8 = pci_read_config8(dev, offset + 4); + reg8 |= 0x3; + pci_write_config8(dev, offset + 4, reg8); +} + +static int place_device_in_d3hot(device_t dev) +{ + unsigned offset; + + offset = pci_find_capability(dev, PCI_CAP_ID_PM); + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + /* For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. */ +#define DEV_CASE(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + DEV_CASE(SDIO): + DEV_CASE(SD): + DEV_CASE(MMC): + DEV_CASE(LPE): + DEV_CASE(SIO_DMA1): + DEV_CASE(I2C1): + DEV_CASE(I2C2): + DEV_CASE(I2C3): + DEV_CASE(I2C4): + DEV_CASE(I2C5): + DEV_CASE(I2C6): + DEV_CASE(I2C7): + DEV_CASE(SIO_DMA2): + DEV_CASE(PWM1): + DEV_CASE(PWM2): + DEV_CASE(HSUART1): + DEV_CASE(HSUART2): + DEV_CASE(SPI): + offset = 0x80; + break; + DEV_CASE(SATA): + DEV_CASE(XHCI): + DEV_CASE(EHCI): + offset = 0x70; + break; + DEV_CASE(HDA): + DEV_CASE(SMBUS): + offset = 0x50; + break; + DEV_CASE(TXE): + break; + DEV_CASE(PCIE_PORT1): + DEV_CASE(PCIE_PORT2): + DEV_CASE(PCIE_PORT3): + DEV_CASE(PCIE_PORT4): + offset = 0xa0; + break; + } + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + return -1; +} + +/* Common PCI device function disable. */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Place device in D3Hot */ + if (place_device_in_d3hot(dev) < 0) { + printk(BIOS_WARNING, + "Could not place %02x.%01x into D3Hot. " + "Keeping device visible.\n", slot, func); + return; + } + /* Disable this device if possible */ + sc_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + static struct device_operations device_ops = { .read_resources = sc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = NULL, .init = NULL, - .enable = NULL, + .enable = southcluster_enable_dev, .scan_bus = NULL, .ops_pci = &soc_pci_ops, };

1 0

Patch set updated for coreboot: 7ab6ae8 baytrail: use MCRX in iosf access functions
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4909 -gerrit commit 7ab6ae80f87c217f14769c841ab69c179bdcfe20 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Oct 29 10:57:31 2013 -0500 baytrail: use MCRX in iosf access functions While most registers accesses don't need the use of the MCRX register (upper 24 bits of address) the MCRX register should be protected. The reference code could be doing accesses to registers that initialized the MCRX register. Thus, any access after that should ensure the MCRX register is initialized appropriately. BUG=None BRANCH=None TEST=Verified assembly output. Also, built and booted through depthcharge. Change-Id: I4d6cfbe6bb1666790c69778b8f2c8baeaf015264 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174643 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 1 + src/soc/intel/baytrail/iosf.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 920061f..7f0c7f5 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -45,6 +45,7 @@ #define IOSF_OPCODE(x) ((x) << 24) #define IOSF_PORT(x) ((0xff & (x)) << 16) #define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) (((~0xff) & (x))) #define IOSF_BYTE_EN_0 0x10 #define IOSF_BYTE_EN_1 0x20 #define IOSF_BYTE_EN_2 0x40 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index b9f1531..b050eba 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -47,6 +47,7 @@ uint32_t iosf_bunit_read(int reg) uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -57,6 +58,7 @@ void iosf_bunit_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } @@ -66,6 +68,7 @@ uint32_t iosf_dunit_read(int reg) IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -81,6 +84,7 @@ uint32_t iosf_dunit_ch1_read(int reg) IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -92,6 +96,7 @@ void iosf_dunit_write(int reg, uint32_t val) IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } @@ -101,6 +106,7 @@ uint32_t iosf_punit_read(int reg) IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } @@ -112,5 +118,6 @@ void iosf_punit_write(int reg, uint32_t val) IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); }

1 0

Patch set updated for coreboot: 91771d8 baytrail: use common code for iosf accessors
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4922 -gerrit commit 91771d8432727674e06a571c88ab227f00defcaa Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 31 11:58:32 2013 -0500 baytrail: use common code for iosf accessors The same sequence is used regardless of the port being read or written. Therefore, use the same implementation for reading or writing to a port. BUG=None BRANCH=None TEST=Built and booted through depthcharge. Dev and recovery screens still work. Nothing bizarre in console output. Change-Id: I1a64b54b50472fa7d601e199653eb4a76accf910 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175441 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/iosf.c | 115 +++++++++++++++--------------------------- 1 file changed, 41 insertions(+), 74 deletions(-) diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 8016446..a7f7a90 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -42,35 +42,42 @@ static inline uint32_t read_iosf_reg(int reg) } #endif -uint32_t iosf_bunit_read(int reg) +/* Common sequences for all the port accesses. */ +static uint32_t iosf_read_port(uint32_t cr, int reg) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; - + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); return read_iosf_reg(MDR_REG); } -void iosf_bunit_write(int reg, uint32_t val) +static void iosf_write_port(uint32_t cr, int reg, uint32_t val) { - uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | - IOSF_PORT(IOSF_PORT_BUNIT) | IOSF_REG(reg) | IOSF_BYTE_EN; - + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; write_iosf_reg(MDR_REG, val); write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } +uint32_t iosf_bunit_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_BUNIT) | + IOSF_PORT(IOSF_PORT_BUNIT); + return iosf_read_port(cr, reg); +} + +void iosf_bunit_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | + IOSF_PORT(IOSF_PORT_BUNIT); + iosf_write_port(cr, reg, val); +} + uint32_t iosf_dunit_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_SYSMEMC); + return iosf_read_port(cr, reg); } uint32_t iosf_dunit_ch0_read(int reg) @@ -81,109 +88,69 @@ uint32_t iosf_dunit_ch0_read(int reg) uint32_t iosf_dunit_ch1_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_DUNIT_CH1); + return iosf_read_port(cr, reg); } void iosf_dunit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) | - IOSF_PORT(IOSF_PORT_SYSMEMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_SYSMEMC); + iosf_write_port(cr, reg, val); } uint32_t iosf_punit_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_PMC) | - IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_PMC); + return iosf_read_port(cr, reg); } void iosf_punit_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | - IOSF_PORT(IOSF_PORT_PMC) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_PMC); + iosf_write_port(cr, reg, val); } uint32_t iosf_usbphy_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_USBPHY); + return iosf_read_port(cr, reg); } void iosf_usbphy_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USBPHY) | - IOSF_PORT(IOSF_PORT_USBPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_USBPHY); + return iosf_write_port(cr, reg, val); } uint32_t iosf_ushphy_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_USHPHY); + return iosf_read_port(cr, reg); } void iosf_ushphy_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_USHPHY) | - IOSF_PORT(IOSF_PORT_USHPHY) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_USHPHY); + return iosf_write_port(cr, reg, val); } uint32_t iosf_lpss_read(int reg) { uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); - return read_iosf_reg(MDR_REG); + IOSF_PORT(IOSF_PORT_LPSS); + return iosf_read_port(cr, reg); } void iosf_lpss_write(int reg, uint32_t val) { uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | - IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | - IOSF_BYTE_EN; - - write_iosf_reg(MDR_REG, val); - write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); - write_iosf_reg(MCR_REG, cr); + IOSF_PORT(IOSF_PORT_LPSS); + return iosf_write_port(cr, reg, val); }

1 0

Patch set updated for coreboot: bbe9863 baytrail: add lpss iosf functions and regs
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4921 -gerrit commit bbe9863dd77f5068369dd177ad6a9f62ae5745cc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 31 10:46:56 2013 -0500 baytrail: add lpss iosf functions and regs The low power subsystem devices have a lot of their configuration done in the IOSF sideband message space. Add support for these access methods. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted through depthcharge. Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636 Signed-off-by: Aaron Durbin <adurbin(a)chromum.org> Reviewed-on: https://chromium-review.googlesource.com/175440 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 29 +++++++++++++++++++++++++++++ src/soc/intel/baytrail/iosf.c | 22 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index b234552..9b59fbc 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -68,6 +68,8 @@ uint32_t iosf_usbphy_read(int reg); void iosf_usbphy_write(int reg, uint32_t val); uint32_t iosf_ushphy_read(int reg); void iosf_ushphy_write(int reg, uint32_t val); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -81,6 +83,7 @@ void iosf_ushphy_write(int reg, uint32_t val); #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -103,6 +106,8 @@ void iosf_ushphy_write(int reg, uint32_t val); #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) #define IOSF_OP_READ_USHPHY 0x06 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_LPSS 0x06 +#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) #define IOSF_OP_READ_SATAPHY 0x00 #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 @@ -167,4 +172,28 @@ void iosf_ushphy_write(int reg, uint32_t val); #define PUNIT_PWRGT_STATUS 0x61 #define PUNIT_GPU_EC_VIRUS 0xd2 +/* + * LPSS Registers + */ +#define LPSS_SIO_DMA1_CTL 0x280 +#define LPSS_I2C1_CTL 0x288 +#define LPSS_I2C2_CTL 0x290 +#define LPSS_I2C3_CTL 0x298 +#define LPSS_I2C4_CTL 0x2a0 +#define LPSS_I2C5_CTL 0x2a8 +#define LPSS_I2C6_CTL 0x2b0 +#define LPSS_I2C7_CTL 0x2b8 +#define LPSS_SIO_DMA2_CTL 0x240 +#define LPSS_PWM1_CTL 0x248 +#define LPSS_PWM2_CTL 0x250 +#define LPSS_HSUART1_CTL 0x258 +#define LPSS_HSUART2_CTL 0x260 +#define LPSS_SPI_CTL 0x268 +# define LPSS_CTL_ACPI_INT_EN (1 << 21) +# define LPSS_CTL_PCI_CFG_DIS (1 << 20) +# define LPSS_CTL_SNOOP (1 << 18) +# define LPSS_CTL_NOSNOOP (1 << 19) +# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) + + #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 7d420cc..8016446 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -165,3 +165,25 @@ void iosf_ushphy_write(int reg, uint32_t val) write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); write_iosf_reg(MCR_REG, cr); } + +uint32_t iosf_lpss_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +void iosf_lpss_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) | + IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) | + IOSF_BYTE_EN; + + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +}

1 0

Patch set updated for coreboot: 512c792 baytrail: Fix EHCI function number and XHCI typo
by Aaron Durbin 25 Feb '14

25 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4920 -gerrit commit 512c792168dc2af7fd6036dd742695bd46da1957 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 1 07:55:07 2013 -0700 baytrail: Fix EHCI function number and XHCI typo BUG=chrome-os-partner:23635 BRANCH=rambi TEST=successfully disable EHCI controller in devicetree.cb Change-Id: I8a22e25a9f7c263d2a6debf0cd1606cb0f6f7645 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175403 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pci_devs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pci_devs.h b/src/soc/intel/baytrail/baytrail/pci_devs.h index 6b38a71..96e9547 100644 --- a/src/soc/intel/baytrail/baytrail/pci_devs.h +++ b/src/soc/intel/baytrail/baytrail/pci_devs.h @@ -53,7 +53,7 @@ /* xHCI */ #define XHCI_DEV 20 #define XHCI_FUNC 0 -# define XCHI_DEVID 0x0f35 +# define XHCI_DEVID 0x0f35 /* LPE Audio */ #define LPE_DEV 21 @@ -119,7 +119,7 @@ /* EHCI */ #define EHCI_DEV 29 -#define EHCI_FUNC 29 +#define EHCI_FUNC 0 # define EHCI_DEVID 0x0f34 /* Serial IO 2 */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2014