coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d674e2c acpigen: Add acpigen_emit_eisaid.
by Vladimir Serbinenko 26 Feb '14

26 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5240 -gerrit commit d674e2cdffac8ae70ca042e5f4011e87bf453846 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 18:59:40 2014 +0100 acpigen: Add acpigen_emit_eisaid. Change-Id: Ib92142a133445018cd152dabe299792ba5f36548 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 28 ++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 1 + 2 files changed, 29 insertions(+) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 6496d75..d149129 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -739,3 +739,31 @@ int acpigen_write_mainboard_resources(const char *scope, const char *name) acpigen_patch_len(len - 1); return len; } + +static int hex2bin(char c) +{ + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return c - '0'; +} + +int acpigen_emit_eisaid(const char *eisaid) +{ + u32 compact = 0; + compact |= (eisaid[0] - 'A' + 1) << 26; + compact |= (eisaid[1] - 'A' + 1) << 21; + compact |= (eisaid[2] - 'A' + 1) << 16; + compact |= hex2bin(eisaid[3]) << 12; + compact |= hex2bin(eisaid[4]) << 8; + compact |= hex2bin(eisaid[5]) << 4; + compact |= hex2bin(eisaid[6]); + + acpigen_emit_byte(0xc); + acpigen_emit_byte((compact >> 24) & 0xff); + acpigen_emit_byte((compact >> 16) & 0xff); + acpigen_emit_byte((compact >> 8) & 0xff); + acpigen_emit_byte(compact & 0xff); + return 5; +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index be138ce..eaa29a5 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -34,6 +34,7 @@ int acpigen_write_byte(unsigned int data); int acpigen_emit_byte(unsigned char data); int acpigen_emit_stream(const char *data, int size); int acpigen_emit_namestring(const char *namepath); +int acpigen_emit_eisaid(const char *eisaid); int acpigen_write_dword(unsigned int data); int acpigen_write_qword(uint64_t data); int acpigen_write_name(const char *name);

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Patch set updated for coreboot: 725a085 lenovo/t60: Enable Infrared port.
by Vladimir Serbinenko 26 Feb '14

26 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5243 -gerrit commit 725a085636e19ae9d3ca39c81d3ad43152fd5dbc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:17:10 2014 +0100 lenovo/t60: Enable Infrared port. Change-Id: I10f05334328c9929a99352185d286a7a17898801 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/acpi/superio.asl | 16 ++++++++++++++++ src/mainboard/lenovo/t60/devicetree.cb | 4 ++++ src/mainboard/lenovo/t60/romstage.c | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl index e69de29..a0d8e0a 100644 --- a/src/mainboard/lenovo/t60/acpi/superio.asl +++ b/src/mainboard/lenovo/t60/acpi/superio.asl @@ -0,0 +1,16 @@ + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..cce5f93 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -148,6 +148,10 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + drq 0x74 = 0x1 + irq 0xf0 = 0x82 end device pnp 164e.3 off # Serial Port diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..237e967 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -79,7 +79,7 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);

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Patch set updated for coreboot: 366b047 lenovo/x60: Enable Infrared port.
by Vladimir Serbinenko 26 Feb '14

26 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5242 -gerrit commit 366b0478463898360f2962dc285ca61e5d842430 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:13:00 2014 +0100 lenovo/x60: Enable Infrared port. Change-Id: I8ce0195bc85a983627826b31eb9879c3dbc80dd9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/lenovo/lenovo.h | 3 ++- src/drivers/lenovo/wacom.c | 44 ++++++++++++++++++++++++++++++++- src/mainboard/lenovo/x201/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/devicetree.cb | 4 +++ src/mainboard/lenovo/x60/romstage.c | 2 +- 6 files changed, 52 insertions(+), 5 deletions(-) diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..06b52e5 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,4 @@ int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); + int have_dock_serial, + int have_infrared); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index f786ed1..f7987ff 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -90,7 +90,8 @@ drivers_lenovo_is_wacom_present(void) void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) + int have_dock_serial, + int have_infrared) { int scopelen, devicelen, reslen, methodlen; @@ -132,6 +133,47 @@ drivers_lenovo_serial_ports_ssdt_generate(const char *scope, scopelen += devicelen; } + if (have_infrared) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("FIR"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("IBM0071"); + devicelen += acpigen_write_name("_CID"); + devicelen += acpigen_emit_eisaid("PNP0511"); + devicelen += acpigen_write_name("_UID"); + + /* One */ + devicelen += acpigen_write_byte(0x1); + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x2f8, 0x2f8, 1, 8, 1); + reslen += acpigen_write_irq(0x08); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + acpigen_patch_len(methodlen); + + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + if (have_dock_serial) { /* Device op. */ scopelen += acpigen_emit_byte(0x5b); diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index b6e99dd..710e369 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -94,7 +94,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0, 0); return (unsigned long)(acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index cf07067..c8fce7f 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -87,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1, 1); return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 5b4e37f..acd5af3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -125,6 +125,10 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + drq 0x74 = 0x1 + irq 0xf0 = 0x82 end device pnp 164e.3 on # Digitizer diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..8eca464 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -86,7 +86,7 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);

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Patch set updated for coreboot: 5d3d24f lenovo: Add lenovo_mainboard_partnumber.
by Vladimir Serbinenko 26 Feb '14

26 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5246 -gerrit commit 5d3d24ff23dbda2f7f9c74ca3673f88171353f3e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:56:51 2014 +0100 lenovo: Add lenovo_mainboard_partnumber. Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/i2c/at24rf08c/lenovo.h | 1 + src/drivers/i2c/at24rf08c/lenovo_serials.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/at24rf08c/lenovo.h b/src/drivers/i2c/at24rf08c/lenovo.h new file mode 100644 index 0000000..6824eb6 --- /dev/null +++ b/src/drivers/i2c/at24rf08c/lenovo.h @@ -0,0 +1 @@ +const char *lenovo_mainboard_partnumber(void); diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 8c63d7d..7a5b259 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -24,6 +24,7 @@ #include <device/smbus.h> #include <smbios.h> #include <console/console.h> +#include "lenovo.h" static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { @@ -71,7 +72,7 @@ const char *smbios_mainboard_serial_number(void) return result; } -const char *smbios_mainboard_product_name(void) +const char *lenovo_mainboard_partnumber(void) { static char result[12]; static int already_read; @@ -86,6 +87,11 @@ const char *smbios_mainboard_product_name(void) return result; } +const char *smbios_mainboard_product_name(void) +{ + return lenovo_mainboard_partnumber(); +} + void smbios_mainboard_set_uuid(u8 *uuid) { static char result[16];

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Patch set updated for coreboot: eff7505 coreboot: remove get_lb_mem() function
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5304 -gerrit commit eff750512793edb45b49f33e906c6d67772dcf2d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 00:24:22 2014 -0600 coreboot: remove get_lb_mem() function The get_lb_mem() is no longer used. Therefore, remove it. Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 5 ----- src/lib/coreboot_table.c | 15 +-------------- 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 9b87f3d..c4ad572 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -338,11 +338,6 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - void fill_lb_gpios(struct lb_gpios *gpios); #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index cb7179d..667c685 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -354,18 +354,6 @@ static unsigned long lb_table_fini(struct lb_header *head) return (unsigned long)rec + rec->size; } -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementation. - */ -static struct lb_memory *mem_ranges = NULL; - -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) @@ -430,8 +418,7 @@ unsigned long write_coreboot_table( /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ - mem_ranges = lb_memory(head); - bootmem_write_memory_table(mem_ranges); + bootmem_write_memory_table(lb_memory(head)); /* Record our motherboard */ lb_mainboard(head);

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Patch set updated for coreboot: 8384982 coreboot: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5305 -gerrit commit 83849826991ecb81a8e1ef5f417823ef051b9f31 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 20:36:56 2014 -0600 coreboot: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/Kconfig | 10 +++++++ src/lib/loaders/load_and_run_payload.c | 53 ++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 4040705..da6960d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -697,6 +697,16 @@ config LINUX_INITRD help An initrd image to add to the Linux kernel. +config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING + bool "Copy payload contents to ram before loading to final destination." + default n + help + On certain platforms a boot speed gain can be realized if mirroring + the payload data stored in non-volatile storage. On x86 systems the + payload would typically live in a memory-mapped SPI part. Copying + the SPI contents to ram before performing the load can speed up + the boot process. + endmenu menu "Debugging" diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 7e1383e..f3156b5 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -19,7 +19,9 @@ #include <stdint.h> #include <stdlib.h> +#include <string.h> #include <console/console.h> +#include <bootmem.h> #include <fallback.h> #include <lib.h> #include <payload_loader.h> @@ -39,6 +41,53 @@ static struct payload global_payload = { .name = CONFIG_CBFS_PREFIX "/payload", }; +static void mirror_payload(struct payload *payload) +{ + char *buffer; + size_t size; + char *src; + uintptr_t alignment_diff; + const unsigned long cacheline_size = 64; + const uintptr_t intra_cacheline_mask = cacheline_size - 1; + const uintptr_t cacheline_mask = ~intra_cacheline_mask; + + src = payload->backing_store.data; + size = payload->backing_store.size; + + /* + * Adjust size so that the start and end points are aligned to a + * cacheline. The SPI hardware controllers on Intel machines hould + * ead and cache full length cachelines as well as prefetch data. + * Once the data is mirrored in memory all accesses should hit the + * CPU's cache. + */ + alignment_diff = (intra_cacheline_mask & (uintptr_t)src); + size += alignment_diff; + + size = ALIGN(size, cacheline_size); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%zx\n", size); + + buffer = bootmem_allocate_buffer(size); + + if (buffer == NULL) { + printk(BIOS_DEBUG, "No buffer for mirroring payload.\n"); + return; + } + + src = (void *)(cacheline_mask & (uintptr_t)src); + + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(buffer, src, size); + + /* Update the payload's backing store. */ + payload->backing_store.data = &buffer[alignment_diff]; +} + struct payload *payload_load(void) { int i; @@ -62,6 +111,10 @@ struct payload *payload_load(void) if (i == ARRAY_SIZE(payload_ops)) return NULL; + if (IS_ENABLED(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING)) { + mirror_payload(payload); + } + entry = selfload(payload); if (entry == NULL)

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Patch set updated for coreboot: 0537e7e coreboot: don't return struct lb_memory * from write_tables()
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5301 -gerrit commit 0537e7e5a778f75dc626af60eb2d81940b4afde5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 18 19:36:05 2014 -0600 coreboot: don't return struct lb_memory * from write_tables() No one is interrogating the write_tables() return value. Therefore, drop it. Change-Id: I97e707f071942239c9a0fa0914af3679ee7a9c3c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/armv7/tables.c | 6 ++---- src/arch/x86/boot/tables.c | 4 +--- src/include/boot/tables.h | 2 +- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c index 7e7cbe4..20c5a9f 100644 --- a/src/arch/armv7/tables.c +++ b/src/arch/armv7/tables.c @@ -46,7 +46,7 @@ void cbmem_fail_resume(void) { } -struct lb_memory *write_tables(void) +void write_tables(void) { unsigned long table_pointer, new_table_pointer; @@ -56,7 +56,7 @@ struct lb_memory *write_tables(void) MAX_COREBOOT_TABLE_SIZE); if (!table_pointer) { printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n"); - return NULL; + return; } new_table_pointer = write_coreboot_table(0UL, 0UL, @@ -74,6 +74,4 @@ struct lb_memory *write_tables(void) /* Print CBMEM sections */ cbmem_list(); - - return get_lb_mem(); } diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index e980ed8..42e431e 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -38,7 +38,7 @@ void cbmem_arch_init(void) move_gdt(); } -struct lb_memory *write_tables(void) +void write_tables(void) { unsigned long low_table_start, low_table_end; unsigned long rom_table_start, rom_table_end; @@ -244,6 +244,4 @@ struct lb_memory *write_tables(void) /* Print CBMEM sections */ cbmem_list(); - - return get_lb_mem(); } diff --git a/src/include/boot/tables.h b/src/include/boot/tables.h index f9e91a4..e86adfc 100644 --- a/src/include/boot/tables.h +++ b/src/include/boot/tables.h @@ -3,6 +3,6 @@ #include <boot/coreboot_tables.h> -struct lb_memory *write_tables(void); +void write_tables(void); #endif /* BOOT_TABLES_H */

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Patch set updated for coreboot: d1fe29e coreboot: introduce notion of bootmem for memory map at boot
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5302 -gerrit commit d1fe29e09601d39e02a497e4e248015cb8a75ab1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 18 21:55:02 2014 -0600 coreboot: introduce notion of bootmem for memory map at boot The write_coreboot_table() in coreboot_table.c was already using struct memrange for managing and building up the entries that eventually go into the lb_memory table. Abstract that concept out to a bootmem memory map. The bootmem concept can then be used as a basis for loading payloads, for example. Change-Id: I7edbbca6bbd0568f658fde39ca93b126cab88367 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 3 - src/include/bootmem.h | 48 ++++++++++ src/include/cbmem.h | 5 +- src/lib/Makefile.inc | 1 + src/lib/bootmem.c | 177 +++++++++++++++++++++++++++++++++++++ src/lib/cbmem.c | 6 +- src/lib/coreboot_table.c | 90 +++---------------- src/lib/dynamic_cbmem.c | 6 +- 8 files changed, 245 insertions(+), 91 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 6243d45..9b87f3d 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -338,9 +338,6 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size); - /* Routines to extract part so the coreboot table or information * from the coreboot table. */ diff --git a/src/include/bootmem.h b/src/include/bootmem.h new file mode 100644 index 0000000..656769f --- /dev/null +++ b/src/include/bootmem.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BOOTMEM_H +#define BOOTMEM_H + +#include <memrange.h> +#include <stdint.h> +#include <boot/coreboot_tables.h> + +/* + * Initialize the memory address space prior to payload loading. The bootmem + * serves as the source for the lb_mem table. + */ +void bootmem_init(void); + +/* Add a range of a given type to the bootmem address space. */ +void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type); + +/* Write memory coreboot table. */ +void bootmem_write_memory_table(struct lb_memory *mem); + +/* Print current range map of boot memory. */ +void bootmem_dump_ranges(void); + +/* Return 1 if region targets usable RAM, 0 otherwise. */ +int bootmem_region_targets_usable_ram(uint64_t start, uint64_t size); + +/* Allocate a temporary buffer from the unused RAM areas. */ +void *bootmem_allocate_buffer(size_t size); + +#endif /* BOOTMEM_H */ diff --git a/src/include/cbmem.h b/src/include/cbmem.h index eb307d4..7cb12b2 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -174,9 +174,8 @@ void *cbmem_find(u32 id); #ifndef __PRE_RAM__ /* Ramstage only functions. */ -/* Add the cbmem memory used to the memory tables. */ -struct lb_memory; -void cbmem_add_lb_mem(struct lb_memory *mem); +/* Add the cbmem memory used to the memory map at boot. */ +void cbmem_add_bootmem(void); void cbmem_list(void); void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5c37329..cb75dbf 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -63,6 +63,7 @@ romstage-$(CONFIG_ARCH_X86) += gcc.c ramstage-y += hardwaremain.c ramstage-y += selfboot.c ramstage-y += coreboot_table.c +ramstage-y += bootmem.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) ramstage-y += memset.c endif diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c new file mode 100644 index 0000000..f1bd7cc --- /dev/null +++ b/src/lib/bootmem.c @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003-2004 Eric Biederman + * Copyright (C) 2005-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <bootmem.h> +#include <cbmem.h> +#include <device/resource.h> +#include <stdlib.h> + +static struct memranges bootmem; + +void bootmem_init(void) +{ + const unsigned long cacheable = IORESOURCE_CACHEABLE; + const unsigned long reserved = IORESOURCE_RESERVE; + struct memranges *bm = &bootmem; + + /* + * Fill the memory map out. The order of operations is important in + * that each overlapping range will take over the next. Therefore, + * add cacheable resources as RAM then add the reserved resources. + */ + memranges_init(bm, cacheable, cacheable, LB_MEM_RAM); + memranges_add_resources(bm, reserved, reserved, LB_MEM_RESERVED); + + /* Add memory used by CBMEM. */ + cbmem_add_bootmem(); +} + +void bootmem_add_range(uint64_t start, uint64_t size, uint32_t type) +{ + memranges_insert(&bootmem, start, size, type); +} + +void bootmem_write_memory_table(struct lb_memory *mem) +{ + const struct range_entry *r; + struct lb_memory_range *lb_r; + + lb_r = &mem->map[0]; + + bootmem_dump_ranges(); + + memranges_each_entry(r, &bootmem) { + lb_r->start = pack_lb64(range_entry_base(r)); + lb_r->size = pack_lb64(range_entry_size(r)); + lb_r->type = range_entry_tag(r); + + lb_r++; + mem->size += sizeof(struct lb_memory_range); + } +} + +struct range_strings { + unsigned long tag; + const char *str; +}; + +static const struct range_strings type_strings[] = { + { LB_MEM_RAM, "RAM" }, + { LB_MEM_RESERVED, "RESERVED" }, + { LB_MEM_ACPI, "ACPI" }, + { LB_MEM_NVS, "NVS" }, + { LB_MEM_UNUSABLE, "UNUSABLE" }, + { LB_MEM_VENDOR_RSVD, "VENDOR RESERVED" }, + { LB_MEM_TABLE, "CONFIGURATION TABLES" }, +}; + +static const char *bootmem_range_string(unsigned long tag) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(type_strings); i++) { + if (type_strings[i].tag == tag) + return type_strings[i].str; + } + + return "UNKNOWN!"; +} + +void bootmem_dump_ranges(void) +{ + int i; + const struct range_entry *r; + + i = 0; + memranges_each_entry(r, &bootmem) { + printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", + i, range_entry_base(r), range_entry_end(r) - 1, + bootmem_range_string(range_entry_tag(r))); + i++; + } +} + +int bootmem_region_targets_usable_ram(uint64_t start, uint64_t size) +{ + const struct range_entry *r; + uint64_t end = start + size; + + memranges_each_entry(r, &bootmem) { + /* All further bootmem entries are beyond this range. */ + if (end <= range_entry_base(r)) + break; + + if (start >= range_entry_base(r) && end <= range_entry_end(r)) { + if (range_entry_tag(r) == LB_MEM_RAM) + return 1; + } + } + return 0; +} + +void *bootmem_allocate_buffer(size_t size) +{ + const struct range_entry *r; + const struct range_entry *region; + /* All allocated buffers fall below the 32-bit boundary. */ + const resource_t max_addr = 1ULL << 32; + resource_t begin; + resource_t end; + + /* 4KiB alignment. */ + size = ALIGN(size, 4096); + region = NULL; + memranges_each_entry(r, &bootmem) { + if (range_entry_size(r) < size) + continue; + + if (range_entry_tag(r) != LB_MEM_RAM) + continue; + + if (range_entry_base(r) >= max_addr) + continue; + + end = range_entry_end(r); + if (end > max_addr) + end = max_addr; + + if ((end - range_entry_base(r)) < size) + continue; + + region = r; + } + + if (region == NULL) + return NULL; + + /* region now points to the highest usable region for the given size. */ + begin = range_entry_base(region); + end = range_entry_end(region); + if (end > max_addr) + end = max_addr; + begin = end - size; + + /* Mark buffer as unusuable for future buffer use. */ + bootmem_add_range(begin, size, LB_MEM_UNUSABLE); + + return (void *)(uintptr_t)begin; +} diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index d97f6af..33fa721 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -19,9 +19,9 @@ #include <types.h> #include <string.h> +#include <bootmem.h> #include <bootstate.h> #include <cbmem.h> -#include <boot/coreboot_tables.h> #include <console/console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) @@ -265,9 +265,9 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_post_device, NULL), }; -void cbmem_add_lb_mem(struct lb_memory *mem) +void cbmem_add_bootmem(void) { - lb_add_memory_range(mem, LB_MEM_TABLE, cbmem_base, cbmem_size); + bootmem_add_range(cbmem_base, cbmem_size, LB_MEM_TABLE); } void cbmem_list(void) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 904185a..cb7179d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -29,7 +29,7 @@ #include <stdlib.h> #include <cbfs.h> #include <cbmem.h> -#include <memrange.h> +#include <bootmem.h> #if CONFIG_CHROMEOS #if CONFIG_GENERATE_ACPI_TABLES #include <arch/acpi.h> @@ -366,78 +366,11 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } -/* This structure keeps track of the coreboot table memory ranges. */ -static struct memranges lb_ranges; - -static struct lb_memory *build_lb_mem(struct lb_header *head) -{ - struct lb_memory *mem; - - /* Record where the lb memory ranges will live */ - mem = lb_memory(head); - mem_ranges = mem; - - /* Fill the memory map out. The order of operations is important in - * that each overlapping range will take over the next. Therefore, - * add cacheable resources as RAM then add the reserved resources. */ - memranges_init(&lb_ranges, IORESOURCE_CACHEABLE, - IORESOURCE_CACHEABLE, LB_MEM_RAM); - memranges_add_resources(&lb_ranges, IORESOURCE_RESERVE, - IORESOURCE_RESERVE, LB_MEM_RESERVED); - - return mem; -} - -static void commit_lb_memory(struct lb_memory *mem) -{ - struct range_entry *r; - struct lb_memory_range *lb_r; - int i; - - lb_r = &mem->map[0]; - i = 0; - - memranges_each_entry(r, &lb_ranges) { - const char *entry_type; - - switch (range_entry_tag(r)) { - case LB_MEM_RAM: entry_type="RAM"; break; - case LB_MEM_RESERVED: entry_type="RESERVED"; break; - case LB_MEM_ACPI: entry_type="ACPI"; break; - case LB_MEM_NVS: entry_type="NVS"; break; - case LB_MEM_UNUSABLE: entry_type="UNUSABLE"; break; - case LB_MEM_VENDOR_RSVD: entry_type="VENDOR RESERVED"; break; - case LB_MEM_TABLE: entry_type="CONFIGURATION TABLES"; break; - default: entry_type="UNKNOWN!"; break; - } - - printk(BIOS_DEBUG, "%2d. %016llx-%016llx: %s\n", - i, range_entry_base(r), range_entry_end(r)-1, - entry_type); - - lb_r->start = pack_lb64(range_entry_base(r)); - lb_r->size = pack_lb64(range_entry_size(r)); - lb_r->type = range_entry_tag(r); - - i++; - lb_r++; - mem->size += sizeof(struct lb_memory_range); - } -} - -void lb_add_memory_range(struct lb_memory *mem, - uint32_t type, uint64_t start, uint64_t size) -{ - memranges_insert(&lb_ranges, start, size, type); -} - - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) { struct lb_header *head; - struct lb_memory *mem; if (low_table_start || low_table_end) { printk(BIOS_DEBUG, "Writing table forward entry at 0x%08lx\n", @@ -476,30 +409,29 @@ unsigned long write_coreboot_table( } #endif - /* The Linux kernel assumes this region is reserved */ - /* Record where RAM is located */ - mem = build_lb_mem(head); + /* Initialize the memory map at boot time. */ + bootmem_init(); if (low_table_start || low_table_end) { + uint64_t size = low_table_end - low_table_start; /* Record the mptable and the the lb_table. * (This will be adjusted later) */ - lb_add_memory_range(mem, LB_MEM_TABLE, - low_table_start, low_table_end - low_table_start); + bootmem_add_range(low_table_start, size, LB_MEM_TABLE); } /* Record the pirq table, acpi tables, and maybe the mptable. However, * these only need to be added when the rom_table is sitting below * 1MiB. If it isn't that means high tables are being written. * The code below handles high tables correctly. */ - if (rom_table_end <= (1 << 20)) - lb_add_memory_range(mem, LB_MEM_TABLE, - rom_table_start, rom_table_end - rom_table_start); - - cbmem_add_lb_mem(mem); + if (rom_table_end <= (1 << 20)) { + uint64_t size = rom_table_end - rom_table_start; + bootmem_add_range(rom_table_start, size, LB_MEM_TABLE); + } /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ - commit_lb_memory(mem); + mem_ranges = lb_memory(head); + bootmem_write_memory_table(mem_ranges); /* Record our motherboard */ lb_mainboard(head); diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 0cc6295..322ead0 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -18,7 +18,7 @@ */ #include <bootstate.h> -#include <boot/tables.h> +#include <bootmem.h> #include <console/console.h> #include <cbmem.h> #include <string.h> @@ -431,14 +431,14 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_pre_device, NULL), }; -void cbmem_add_lb_mem(struct lb_memory *mem) +void cbmem_add_bootmem(void) { unsigned long base; unsigned long top; base = (unsigned long)cbmem_base(); top = (unsigned long)get_top_aligned(); - lb_add_memory_range(mem, LB_MEM_TABLE, base, top - base); + bootmem_add_range(base, top - base, LB_MEM_TABLE); } void cbmem_list(void)

1 0

Patch set updated for coreboot: f488707 selfboot: use bootmem infrastructure
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5303 -gerrit commit f488707ef90a0ffb19d3e1ad765ce38714a99bd9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 00:21:10 2014 -0600 selfboot: use bootmem infrastructure Instead of packing and unpacking entries in lb_mem use the bootmem infrastructure for performing sanity checks during payload loading. Change-Id: Ica2bee7ebb0f6bf9ded31deac8cb700aa387bc7a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/payload_loader.h | 3 +- src/lib/loaders/load_and_run_payload.c | 5 +- src/lib/selfboot.c | 140 ++++++++------------------------- 3 files changed, 33 insertions(+), 115 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 0715d37..6f4a858 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -58,7 +58,6 @@ struct payload_loader_ops { }; /* Defined in src/lib/selfboot.c */ -struct lb_memory; -void *selfload(struct lb_memory *mem, struct payload *payload); +void *selfload(struct payload *payload); #endif /* PAYLOAD_LOADER_H */ diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 3e1eafb..7e1383e 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <stdlib.h> #include <console/console.h> -#include <boot/coreboot_tables.h> #include <fallback.h> #include <lib.h> #include <payload_loader.h> @@ -44,7 +43,6 @@ struct payload *payload_load(void) { int i; void *entry; - struct lb_memory *mem; const struct payload_loader_ops *ops; struct payload *payload = &global_payload; @@ -64,8 +62,7 @@ struct payload *payload_load(void) if (i == ARRAY_SIZE(payload_ops)) return NULL; - mem = get_lb_mem(); - entry = selfload(mem, payload); + entry = selfload(payload); if (entry == NULL) return NULL; diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 6dc3a75..74a74f9 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -21,19 +21,14 @@ #include <arch/byteorder.h> #include <console/console.h> #include <cpu/cpu.h> -#include <boot/coreboot_tables.h> #include <stdint.h> #include <stdlib.h> #include <string.h> #include <cbfs.h> #include <lib.h> +#include <bootmem.h> #include <payload_loader.h> -/* Maximum physical address we can use for the coreboot bounce buffer. */ -#ifndef MAX_ADDR -#define MAX_ADDR -1UL -#endif - /* from coreboot_ram.ld: */ extern unsigned char _ram_seg; extern unsigned char _eram_seg; @@ -73,12 +68,10 @@ struct segment { static unsigned long bounce_size, bounce_buffer; -static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) +static void get_bounce_buffer(unsigned long req_size) { unsigned long lb_size; - unsigned long mem_entries; - unsigned long buffer; - int i; + void *buffer; /* When the ramstage is relocatable there is no need for a bounce * buffer. All payloads should not overlap the ramstage. @@ -94,93 +87,15 @@ static void get_bounce_buffer(struct lb_memory *mem, unsigned long req_size) * to place a copy to return to. */ lb_size = req_size + lb_size; - mem_entries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); - buffer = 0; - for(i = 0; i < mem_entries; i++) { - unsigned long mstart, mend; - unsigned long msize; - unsigned long tbuffer; - if (mem->map[i].type != LB_MEM_RAM) - continue; - if (unpack_lb64(mem->map[i].start) > MAX_ADDR) - continue; - if (unpack_lb64(mem->map[i].size) < lb_size) - continue; - mstart = unpack_lb64(mem->map[i].start); - msize = MAX_ADDR - mstart +1; - if (msize > unpack_lb64(mem->map[i].size)) - msize = unpack_lb64(mem->map[i].size); - mend = mstart + msize; - tbuffer = mend - lb_size; - if (tbuffer < buffer) - continue; - buffer = tbuffer; - } - bounce_buffer = buffer; - bounce_size = req_size; -} - -static int valid_area(struct lb_memory *mem, unsigned long buffer, - unsigned long start, unsigned long len) -{ - /* Check through all of the memory segments and ensure - * the segment that was passed in is completely contained - * in RAM. - */ - int i; - unsigned long end = start + len; - unsigned long mem_entries = (mem->size - sizeof(*mem)) / - sizeof(mem->map[0]); - /* See if I conflict with the bounce buffer */ - if (end >= buffer) { - return 0; - } + buffer = bootmem_allocate_buffer(lb_size); - /* Walk through the table of valid memory ranges and see if I - * have a match. - */ - for(i = 0; i < mem_entries; i++) { - uint64_t mstart, mend; - uint32_t mtype; - mtype = mem->map[i].type; - mstart = unpack_lb64(mem->map[i].start); - mend = mstart + unpack_lb64(mem->map[i].size); - if ((mtype == LB_MEM_RAM) && (start >= mstart) && (end < mend)) { - break; - } - if ((mtype == LB_MEM_TABLE) && (start >= mstart) && (end < mend)) { - printk(BIOS_ERR, "Payload is overwriting coreboot tables.\n"); - break; - } - } - if (i == mem_entries) { - if (start < (1024*1024) && end <=(1024*1024)) { - printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded" - " into a reserved area in the lower 1MB\n"); - return 1; - } - printk(BIOS_ERR, "No matching ram area found for range:\n"); - printk(BIOS_ERR, " [0x%016lx, 0x%016lx)\n", start, end); - printk(BIOS_ERR, "Ram areas\n"); - for(i = 0; i < mem_entries; i++) { - uint64_t mstart, mend; - uint32_t mtype; - mtype = mem->map[i].type; - mstart = unpack_lb64(mem->map[i].start); - mend = mstart + unpack_lb64(mem->map[i].size); - printk(BIOS_ERR, " [0x%016lx, 0x%016lx) %s\n", - (unsigned long)mstart, - (unsigned long)mend, - (mtype == LB_MEM_RAM)?"RAM":"Reserved"); + printk(BIOS_SPEW, "Bounce Buffer at %p, %lu bytes\n", buffer, lb_size); - } - return 0; - } - return 1; + bounce_buffer = (uintptr_t)buffer; + bounce_size = req_size; } - static int overlaps_coreboot(struct segment *seg) { unsigned long start, end; @@ -299,7 +214,6 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) static int build_self_segment_list( struct segment *head, - struct lb_memory *mem, struct payload *payload, uintptr_t *entry) { struct segment *new; @@ -393,24 +307,37 @@ static int build_self_segment_list( static int load_self_segments( struct segment *head, - struct lb_memory *mem, struct payload *payload) { struct segment *ptr; - unsigned long bounce_high = lb_end; + + for(ptr = head->next; ptr != head; ptr = ptr->next) { + if (!bootmem_region_targets_usable_ram(ptr->s_dstaddr, + ptr->s_memsz)) { + printk(BIOS_ERR, "SELF Payload doesn't target RAM:\n"); + printk(BIOS_ERR, "Failed Segment: 0x%lx, %lu bytes\n", + ptr->s_dstaddr, ptr->s_memsz); + bootmem_dump_ranges(); + return 0; + } + } + for(ptr = head->next; ptr != head; ptr = ptr->next) { + /* + * Add segments to bootmem memory map before a bounce buffer is + * allocated so that there aren't conflicts with the actual + * payload. + */ + bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, + LB_MEM_UNUSABLE); + if (!overlaps_coreboot(ptr)) continue; -#if CONFIG_RELOCATABLE_RAMSTAGE - /* payloads are required to not overlap ramstage. */ - return 0; -#else if (ptr->s_dstaddr + ptr->s_memsz > bounce_high) bounce_high = ptr->s_dstaddr + ptr->s_memsz; -#endif } - get_bounce_buffer(mem, bounce_high - lb_start); + get_bounce_buffer(bounce_high - lb_start); if (!bounce_buffer) { printk(BIOS_ERR, "Could not find a bounce buffer...\n"); return 0; @@ -421,11 +348,6 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - /* Verify the memory addresses in the segment are valid */ - if (!valid_area(mem, bounce_buffer, ptr->s_dstaddr, ptr->s_memsz)) - return 0; - } - for(ptr = head->next; ptr != head; ptr = ptr->next) { unsigned char *dest, *src; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -505,17 +427,17 @@ static int load_self_segments( return 1; } -void *selfload(struct lb_memory *mem, struct payload *payload) +void *selfload(struct payload *payload) { uintptr_t entry = 0; struct segment head; /* Preprocess the self segments */ - if (!build_self_segment_list(&head, mem, payload, &entry)) + if (!build_self_segment_list(&head, payload, &entry)) goto out; /* Load the segments */ - if (!load_self_segments(&head, mem, payload)) + if (!load_self_segments(&head, payload)) goto out; printk(BIOS_SPEW, "Loaded segments\n");

1 0

Patch set updated for coreboot: b1bed87 coreboot: remove get_lb_mem() function
by Aaron Durbin 26 Feb '14

26 Feb '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5304 -gerrit commit b1bed87575929789711e8fc61d16f9f9b6228359 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 00:24:22 2014 -0600 coreboot: remove get_lb_mem() function The get_lb_mem() is no longer used. Therefore, remove it. Change-Id: I2d8427c460cfbb2b7a9870dfd54f4a75738cfb88 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/boot/coreboot_tables.h | 5 ----- src/lib/coreboot_table.c | 15 +-------------- 2 files changed, 1 insertion(+), 19 deletions(-) diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 9b87f3d..c4ad572 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -338,11 +338,6 @@ unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end); -/* Routines to extract part so the coreboot table or information - * from the coreboot table. - */ -struct lb_memory *get_lb_mem(void); - void fill_lb_gpios(struct lb_gpios *gpios); #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index cb7179d..667c685 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -354,18 +354,6 @@ static unsigned long lb_table_fini(struct lb_header *head) return (unsigned long)rec + rec->size; } -/* Routines to extract part so the coreboot table or - * information from the coreboot table after we have written it. - * Currently get_lb_mem relies on a global we can change the - * implementation. - */ -static struct lb_memory *mem_ranges = NULL; - -struct lb_memory *get_lb_mem(void) -{ - return mem_ranges; -} - unsigned long write_coreboot_table( unsigned long low_table_start, unsigned long low_table_end, unsigned long rom_table_start, unsigned long rom_table_end) @@ -430,8 +418,7 @@ unsigned long write_coreboot_table( /* No other memory areas can be added after the memory table has been * committed as the entries won't show up in the serialize mem table. */ - mem_ranges = lb_memory(head); - bootmem_write_memory_table(mem_ranges); + bootmem_write_memory_table(lb_memory(head)); /* Record our motherboard */ lb_mainboard(head);

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coreboot-gerrit February 2014