coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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1135 discussions

Patch set updated for coreboot: 3acebb2 acpigen: Add acpigen_emit_eisaid.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5240 -gerrit commit 3acebb205a8dd2e0781ce8e804ca33db42b8249f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 18:59:40 2014 +0100 acpigen: Add acpigen_emit_eisaid. Change-Id: Ib92142a133445018cd152dabe299792ba5f36548 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpigen.c | 28 ++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 1 + 2 files changed, 29 insertions(+) diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c index 6496d75..d149129 100644 --- a/src/arch/x86/boot/acpigen.c +++ b/src/arch/x86/boot/acpigen.c @@ -739,3 +739,31 @@ int acpigen_write_mainboard_resources(const char *scope, const char *name) acpigen_patch_len(len - 1); return len; } + +static int hex2bin(char c) +{ + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + return c - '0'; +} + +int acpigen_emit_eisaid(const char *eisaid) +{ + u32 compact = 0; + compact |= (eisaid[0] - 'A' + 1) << 26; + compact |= (eisaid[1] - 'A' + 1) << 21; + compact |= (eisaid[2] - 'A' + 1) << 16; + compact |= hex2bin(eisaid[3]) << 12; + compact |= hex2bin(eisaid[4]) << 8; + compact |= hex2bin(eisaid[5]) << 4; + compact |= hex2bin(eisaid[6]); + + acpigen_emit_byte(0xc); + acpigen_emit_byte((compact >> 24) & 0xff); + acpigen_emit_byte((compact >> 16) & 0xff); + acpigen_emit_byte((compact >> 8) & 0xff); + acpigen_emit_byte(compact & 0xff); + return 5; +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index be138ce..eaa29a5 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -34,6 +34,7 @@ int acpigen_write_byte(unsigned int data); int acpigen_emit_byte(unsigned char data); int acpigen_emit_stream(const char *data, int size); int acpigen_emit_namestring(const char *namepath); +int acpigen_emit_eisaid(const char *eisaid); int acpigen_write_dword(unsigned int data); int acpigen_write_qword(uint64_t data); int acpigen_write_name(const char *name);

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Patch set updated for coreboot: 50c4777 lenovo/t60: Enable Infrared port.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5243 -gerrit commit 50c4777cdd6be119f527fde26f4f8299d684f22c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:17:10 2014 +0100 lenovo/t60: Enable Infrared port. Change-Id: I10f05334328c9929a99352185d286a7a17898801 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/acpi/superio.asl | 16 ++++++++++++++++ src/mainboard/lenovo/t60/devicetree.cb | 4 ++++ src/mainboard/lenovo/t60/romstage.c | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t60/acpi/superio.asl b/src/mainboard/lenovo/t60/acpi/superio.asl index e69de29..a0d8e0a 100644 --- a/src/mainboard/lenovo/t60/acpi/superio.asl +++ b/src/mainboard/lenovo/t60/acpi/superio.asl @@ -0,0 +1,16 @@ + Device (FIR) // Infrared + { + Name(_HID, EISAID("IBM0071")) + Name(_CID, EISAID("PNP0511")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x2f8, 0x2f8, 0x01, 0x08) + IRQNoFlags () {3} + }) + + Method (_STA, 0) + { + Return (0xf) + } + } diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..cce5f93 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -148,6 +148,10 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + drq 0x74 = 0x1 + irq 0xf0 = 0x82 end device pnp 164e.3 off # Serial Port diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index dae917c..237e967 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -79,7 +79,7 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601);

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Patch set updated for coreboot: e1dbdcd lenovo/x60: Enable Infrared port.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5242 -gerrit commit e1dbdcd17cf6d2e6a7d58e16f02873463ef9c22b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:13:00 2014 +0100 lenovo/x60: Enable Infrared port. Change-Id: I8ce0195bc85a983627826b31eb9879c3dbc80dd9 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/acpi_tables.c | 2 +- src/mainboard/lenovo/x60/devicetree.cb | 4 +++ src/mainboard/lenovo/x60/romstage.c | 2 +- src/odm_oem/lenovo/lenovo.h | 3 ++- src/odm_oem/lenovo/wacom.c | 44 ++++++++++++++++++++++++++++++++- 6 files changed, 52 insertions(+), 5 deletions(-) diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 981c52e..26c8f02 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -94,7 +94,7 @@ unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0, 0); return (unsigned long)(acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c index d6ce4ba..c7c0a1a 100644 --- a/src/mainboard/lenovo/x60/acpi_tables.c +++ b/src/mainboard/lenovo/x60/acpi_tables.c @@ -87,7 +87,7 @@ unsigned long acpi_fill_madt(unsigned long current) unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { generate_cpu_entries(); - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1, 1); return (unsigned long) (acpigen_get_current()); } diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 5b4e37f..acd5af3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -125,6 +125,10 @@ chip northbridge/intel/i945 chip superio/nsc/pc87382 device pnp 164e.2 on # IR io 0x60 = 0x2f8 + irq 0x29 = 0xb0 + irq 0x70 = 0x3 + drq 0x74 = 0x1 + irq 0xf0 = 0x82 end device pnp 164e.3 on # Digitizer diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 1198fb2..8eca464 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -86,7 +86,7 @@ static void ich7_enable_lpc(void) // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0f); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); diff --git a/src/odm_oem/lenovo/lenovo.h b/src/odm_oem/lenovo/lenovo.h index 25074bc..9abda4b 100644 --- a/src/odm_oem/lenovo/lenovo.h +++ b/src/odm_oem/lenovo/lenovo.h @@ -1,4 +1,5 @@ const char *lenovo_mainboard_partnumber(void); int drivers_lenovo_is_wacom_present(void); void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); + int have_dock_serial, + int have_infrared); diff --git a/src/odm_oem/lenovo/wacom.c b/src/odm_oem/lenovo/wacom.c index c5be6ed..bc962c8 100644 --- a/src/odm_oem/lenovo/wacom.c +++ b/src/odm_oem/lenovo/wacom.c @@ -89,7 +89,8 @@ drivers_lenovo_is_wacom_present(void) void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) + int have_dock_serial, + int have_infrared) { int scopelen, devicelen, reslen, methodlen; @@ -131,6 +132,47 @@ drivers_lenovo_serial_ports_ssdt_generate(const char *scope, scopelen += devicelen; } + if (have_infrared) { + /* Device op. */ + scopelen += acpigen_emit_byte(0x5b); + scopelen += acpigen_emit_byte(0x82); + devicelen = acpigen_write_len_f(); + devicelen += acpigen_emit_namestring("FIR"); + + devicelen += acpigen_write_name("_HID"); + devicelen += acpigen_emit_eisaid("IBM0071"); + devicelen += acpigen_write_name("_CID"); + devicelen += acpigen_emit_eisaid("PNP0511"); + devicelen += acpigen_write_name("_UID"); + + /* One */ + devicelen += acpigen_write_byte(0x1); + devicelen += acpigen_write_name("_CRS"); + + reslen = acpigen_write_resourcetemplate_header(); + reslen += acpigen_write_io16(0x2f8, 0x2f8, 1, 8, 1); + reslen += acpigen_write_irq(0x08); + + devicelen += reslen; + devicelen += acpigen_write_resourcetemplate_footer(reslen); + + /* method op */ + devicelen += acpigen_emit_byte(0x14); + methodlen = acpigen_write_len_f(); + methodlen += acpigen_emit_namestring("_STA"); + /* no fnarg */ + methodlen += acpigen_emit_byte(0x00); + /* return */ + methodlen += acpigen_emit_byte(0xa4); + methodlen += acpigen_write_byte(0xf); + acpigen_patch_len(methodlen); + + devicelen += methodlen; + + acpigen_patch_len(devicelen - 1); + scopelen += devicelen; + } + if (have_dock_serial) { /* Device op. */ scopelen += acpigen_emit_byte(0x5b);

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Patch set updated for coreboot: 06a2bf1 odm_oem: Add support for ODM/OEM Kconfig
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5245 -gerrit commit 06a2bf1df15351cd4e50ca644987420f4ed8f34d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:44:11 2014 +0100 odm_oem: Add support for ODM/OEM Kconfig Change-Id: Ief3da76db0a6ea198fab47396e42bdc6a22d5d85 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 1 + src/odm_oem/Kconfig | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index bb25afd..0856179 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -215,6 +215,7 @@ config COVERAGE endmenu source src/mainboard/Kconfig +source src/odm_oem/Kconfig # This option is used to set the architecture of a mainboard to X86. # It is usually set in mainboard/*/Kconfig. diff --git a/src/odm_oem/Kconfig b/src/odm_oem/Kconfig new file mode 100644 index 0000000..6eb2993 --- /dev/null +++ b/src/odm_oem/Kconfig @@ -0,0 +1,3 @@ +menu "OEM / ODM" + +endmenu

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Patch set updated for coreboot: a9533e0 lenovo: Move lenovo_serials.c to src/odm_oem/lenovo.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5244 -gerrit commit a9533e0280efccc01210cca6949aa7c9d6ad0040 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:29:59 2014 +0100 lenovo: Move lenovo_serials.c to src/odm_oem/lenovo. Change-Id: Ifa18c61ed01008085d40df24b0a2d194cfc234b1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Makefile.inc | 1 + src/drivers/i2c/at24rf08c/Makefile.inc | 1 - src/drivers/i2c/at24rf08c/lenovo_serials.c | 137 ----------------------------- src/odm_oem/Makefile.inc | 1 + src/odm_oem/lenovo/Makefile.inc | 1 + src/odm_oem/lenovo/serials.c | 137 +++++++++++++++++++++++++++++ 6 files changed, 140 insertions(+), 138 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 19ba294..2339123 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,6 +52,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs # root source directories of coreboot subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode +subdirs-y += src/odm_oem subdirs-y += util/cbfstool util/sconfig util/nvramtool subdirs-y += src/arch/$(ARCHDIR-y) subdirs-y += src/mainboard/$(MAINBOARDDIR) diff --git a/src/drivers/i2c/at24rf08c/Makefile.inc b/src/drivers/i2c/at24rf08c/Makefile.inc index 10c91d1..8a81560 100644 --- a/src/drivers/i2c/at24rf08c/Makefile.inc +++ b/src/drivers/i2c/at24rf08c/Makefile.inc @@ -1,2 +1 @@ ramstage-$(CONFIG_VENDOR_LENOVO) += at24rf08c.c -ramstage-$(CONFIG_VENDOR_LENOVO) += lenovo_serials.c diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c deleted file mode 100644 index 8c63d7d..0000000 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <arch/io.h> -#include <device/device.h> -#include <device/smbus.h> -#include <smbios.h> -#include <console/console.h> - -static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) -{ - int i; - device_t dev; - - dev = dev_find_slot_on_smbus(1, 0x54 | bank); - if (dev == 0) { - printk(BIOS_WARNING, "EEPROM not found\n"); - memcpy(result, "*INVALID*", sizeof ("*INVALID*")); - return; - } - - for (i = 0; i < len; i++) { - int t; - int j; - /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding. - Retry several times in case of failure. - */ - for (j = 0; j < 100; j++) { - t = smbus_read_byte(dev, start + i); - if (t >= 0) - break; - } - if (t < 0x20 || t > 0x7f) { - memcpy(result, "*INVALID*", sizeof ("*INVALID*")); - return; - } - result[i] = t; - } -} - -const char *smbios_mainboard_serial_number(void) -{ - static char result[12]; - static int already_read; - - if (already_read) - return result; - - memset(result, 0, sizeof (result)); - at24rf08c_read_string(0, 0x2e, 7, result); - - already_read = 1; - return result; -} - -const char *smbios_mainboard_product_name(void) -{ - static char result[12]; - static int already_read; - - if (already_read) - return result; - - memset (result, 0, sizeof (result)); - at24rf08c_read_string(0, 0x27, 7, result); - - already_read = 1; - return result; -} - -void smbios_mainboard_set_uuid(u8 *uuid) -{ - static char result[16]; - unsigned i; - static int already_read; - device_t dev; - const int remap[16] = { - /* UUID byteswap. */ - 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 - }; - - - if (already_read) { - memcpy (uuid, result, 16); - return; - } - - memset (result, 0, sizeof (result)); - - dev = dev_find_slot_on_smbus(1, 0x56); - if (dev == 0) { - printk(BIOS_WARNING, "eeprom not found\n"); - already_read = 1; - memset (uuid, 0, 16); - return; - } - - for (i = 0; i < 16; i++) { - int t; - int j; - /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding. - Retry several times in case of failure. - */ - for (j = 0; j < 100; j++) { - t = smbus_read_byte(dev, 0x12 + i); - if (t >= 0) - break; - } - if (t < 0) { - memset (result, 0, sizeof (result)); - break; - } - result[remap[i]] = t; - } - - already_read = 1; - - memcpy (uuid, result, 16); -} diff --git a/src/odm_oem/Makefile.inc b/src/odm_oem/Makefile.inc new file mode 100644 index 0000000..596d8ed --- /dev/null +++ b/src/odm_oem/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_VENDOR_LENOVO) += lenovo diff --git a/src/odm_oem/lenovo/Makefile.inc b/src/odm_oem/lenovo/Makefile.inc new file mode 100644 index 0000000..18e2110 --- /dev/null +++ b/src/odm_oem/lenovo/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += serials.c diff --git a/src/odm_oem/lenovo/serials.c b/src/odm_oem/lenovo/serials.c new file mode 100644 index 0000000..8c63d7d --- /dev/null +++ b/src/odm_oem/lenovo/serials.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/smbus.h> +#include <smbios.h> +#include <console/console.h> + +static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) +{ + int i; + device_t dev; + + dev = dev_find_slot_on_smbus(1, 0x54 | bank); + if (dev == 0) { + printk(BIOS_WARNING, "EEPROM not found\n"); + memcpy(result, "*INVALID*", sizeof ("*INVALID*")); + return; + } + + for (i = 0; i < len; i++) { + int t; + int j; + /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding. + Retry several times in case of failure. + */ + for (j = 0; j < 100; j++) { + t = smbus_read_byte(dev, start + i); + if (t >= 0) + break; + } + if (t < 0x20 || t > 0x7f) { + memcpy(result, "*INVALID*", sizeof ("*INVALID*")); + return; + } + result[i] = t; + } +} + +const char *smbios_mainboard_serial_number(void) +{ + static char result[12]; + static int already_read; + + if (already_read) + return result; + + memset(result, 0, sizeof (result)); + at24rf08c_read_string(0, 0x2e, 7, result); + + already_read = 1; + return result; +} + +const char *smbios_mainboard_product_name(void) +{ + static char result[12]; + static int already_read; + + if (already_read) + return result; + + memset (result, 0, sizeof (result)); + at24rf08c_read_string(0, 0x27, 7, result); + + already_read = 1; + return result; +} + +void smbios_mainboard_set_uuid(u8 *uuid) +{ + static char result[16]; + unsigned i; + static int already_read; + device_t dev; + const int remap[16] = { + /* UUID byteswap. */ + 3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15 + }; + + + if (already_read) { + memcpy (uuid, result, 16); + return; + } + + memset (result, 0, sizeof (result)); + + dev = dev_find_slot_on_smbus(1, 0x56); + if (dev == 0) { + printk(BIOS_WARNING, "eeprom not found\n"); + already_read = 1; + memset (uuid, 0, 16); + return; + } + + for (i = 0; i < 16; i++) { + int t; + int j; + /* After a register write AT24RF08C (which we issued in init function) sometimes stops responding. + Retry several times in case of failure. + */ + for (j = 0; j < 100; j++) { + t = smbus_read_byte(dev, 0x12 + i); + if (t >= 0) + break; + } + if (t < 0) { + memset (result, 0, sizeof (result)); + break; + } + result[remap[i]] = t; + } + + already_read = 1; + + memcpy (uuid, result, 16); +}

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Patch set updated for coreboot: c79106b lenovo: Add lenovo_mainboard_partnumber.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5246 -gerrit commit c79106b26cafe561a1ed76eea32e31c2874948d3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 15 19:56:51 2014 +0100 lenovo: Add lenovo_mainboard_partnumber. Change-Id: Ie10dcb742fe0884dd94ff5960e2e4b116f633243 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/odm_oem/lenovo/lenovo.h | 1 + src/odm_oem/lenovo/serials.c | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/odm_oem/lenovo/lenovo.h b/src/odm_oem/lenovo/lenovo.h new file mode 100644 index 0000000..6824eb6 --- /dev/null +++ b/src/odm_oem/lenovo/lenovo.h @@ -0,0 +1 @@ +const char *lenovo_mainboard_partnumber(void); diff --git a/src/odm_oem/lenovo/serials.c b/src/odm_oem/lenovo/serials.c index 8c63d7d..7a5b259 100644 --- a/src/odm_oem/lenovo/serials.c +++ b/src/odm_oem/lenovo/serials.c @@ -24,6 +24,7 @@ #include <device/smbus.h> #include <smbios.h> #include <console/console.h> +#include "lenovo.h" static void at24rf08c_read_string(u8 bank, u8 start, u8 len, char *result) { @@ -71,7 +72,7 @@ const char *smbios_mainboard_serial_number(void) return result; } -const char *smbios_mainboard_product_name(void) +const char *lenovo_mainboard_partnumber(void) { static char result[12]; static int already_read; @@ -86,6 +87,11 @@ const char *smbios_mainboard_product_name(void) return result; } +const char *smbios_mainboard_product_name(void) +{ + return lenovo_mainboard_partnumber(); +} + void smbios_mainboard_set_uuid(u8 *uuid) { static char result[16];

1 0

Patch merged into coreboot/master: d59d1bd Kill ALT_CBFS_LOAD_PAYLOAD
by gerrit＠coreboot.org 25 Feb '14

25 Feb '14

the following patch was just integrated into master: commit d59d1bd64417bd38a56667a1a71eeece23a9c3e3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:27:22 2014 +0100 Kill ALT_CBFS_LOAD_PAYLOAD Not used anymore. Change-Id: Icf3a4a7f932776981048b805478582ad2b784182 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5132 for details. -gerrit

1 0

Patch merged into coreboot/master: a87fc5f lynxpoint: Kill alternative cbfs_load_payload.
by gerrit＠coreboot.org 25 Feb '14

25 Feb '14

the following patch was just integrated into master: commit a87fc5ff9b92518359a243368d6aa409eb807a8b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:23:56 2014 +0100 lynxpoint: Kill alternative cbfs_load_payload. With generic load using 32-bit accesses this is no longer has a huge impact it previously did. It's also unnecessarily component-speficific. Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/5131 for details. -gerrit

1 0

Patch set updated for coreboot: a87fc5f lynxpoint: Kill alternative cbfs_load_payload.
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5131 -gerrit commit a87fc5ff9b92518359a243368d6aa409eb807a8b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Feb 5 14:23:56 2014 +0100 lynxpoint: Kill alternative cbfs_load_payload. With generic load using 32-bit accesses this is no longer has a huge impact it previously did. It's also unnecessarily component-speficific. Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/lynxpoint/Kconfig | 1 - src/southbridge/intel/lynxpoint/Makefile.inc | 1 - src/southbridge/intel/lynxpoint/spi_loading.c | 90 --------------------------- 3 files changed, 92 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5ff00db..970a11d 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -32,7 +32,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select SPI_FLASH - select ALT_CBFS_LOAD_PAYLOAD config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 7be2d03..b691e6f 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -41,7 +41,6 @@ ramstage-y += me_status.c ramstage-y += reset.c ramstage-y += watchdog.c ramstage-y += acpi.c -ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += spi.c diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c deleted file mode 100644 index 57e3af8..0000000 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 ChromeOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdlib.h> -#include <string.h> -#include <arch/byteorder.h> -#include <cbmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#if CONFIG_VBOOT_VERIFY_FIRMWARE -#include <vendorcode/google/chromeos/chromeos.h> -#else -static inline void *vboot_get_payload(size_t *len) { return NULL; } -#endif - -#define CACHELINE_SIZE 64 -#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) -#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) - -/* Mirror the payload file to the default SMM location if it is small enough. - * The default SMM region can be used since no one is using the memory at this - * location at this stage in the boot. */ -static inline void *spi_mirror(void *file_start, int file_len) -{ - int alignment_diff; - char *src; - char *dest = (void *)SMM_DEFAULT_BASE; - - alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); - - /* Adjust file length so that the start and end points are aligned to a - * cacheline. Coupled with the ROM caching in the CPU the SPI hardware - * will read and cache full length cachelines. It will also prefetch - * data as well. Once things are mirrored in memory all accesses should - * hit the CPUs cache. */ - file_len += alignment_diff; - file_len = ALIGN(file_len, CACHELINE_SIZE); - - printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); - - /* Just pass back the pointer to ROM space if the file is larger - * than the RAM mirror region. */ - if (file_len > SMM_DEFAULT_SIZE) - return file_start; - - src = (void *)(CACHELINE_MASK & (long)file_start); - /* Note that if mempcy is not using 32-bit moves the performance will - * degrade because the SPI hardware prefetchers look for - * cacheline-aligned 32-bit accesses to kick in. */ - memcpy(dest, src, file_len); - - /* Provide pointer into mirrored space. */ - return &dest[alignment_diff]; -} - -void *cbfs_load_payload(struct cbfs_media *media, const char *name) -{ - size_t file_len; - void *file_start; - - file_start = vboot_get_payload(&file_len); - - if (file_start != NULL) - return spi_mirror(file_start, file_len); - - file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - - if (file_start == NULL) - return NULL; - - return spi_mirror(file_start, file_len); -}

1 0

Patch set updated for coreboot: c859186 NOTFORMERGE: x60gfx: step 9
by Vladimir Serbinenko 25 Feb '14

25 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5287 -gerrit commit c85918691e65dd24f5746ae8421c8149e2ed56e4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Feb 23 14:17:03 2014 +0100 NOTFORMERGE: x60gfx: step 9 Change-Id: I91c5619d7c2a212a55e301733374de8b23f8aa1f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 20 +- src/drivers/intel/gma/i915_reg.h | 5 + src/mainboard/lenovo/x60/Kconfig | 1 + src/mainboard/lenovo/x60/Makefile.inc | 2 - src/mainboard/lenovo/x60/i915.c | 601 +++++---- src/mainboard/lenovo/x60/i915io.c | 2273 --------------------------------- src/mainboard/lenovo/x60/i915io.h | 86 -- src/northbridge/intel/i945/gma.c | 6 +- 8 files changed, 389 insertions(+), 2605 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 0066b6a..15affd3 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -32,7 +32,7 @@ wait_rdy(u32 mmio) unsigned try = 100; while (try--) { - if (read32(mmio + PCH_GMBUS2) & (1 << 11)) + if (read32(mmio + GMBUS2) & (1 << 11)) return; udelay(10); } @@ -45,29 +45,29 @@ intel_gmbus_read_edid(u32 mmio, u8 bus, u8 slave, u8 *edid) wait_rdy(mmio); /* 100 KHz, hold 0ns, */ - write32(mmio + PCH_GMBUS0, bus); + write32(mmio + GMBUS0, bus); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x46000000 | (slave << 1)); + write32(mmio + GMBUS5, 0); + write32(mmio + GMBUS1, 0x46000000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + PCH_GMBUS5, 0); - write32(mmio + PCH_GMBUS1, 0x4a800001 | (slave << 1)); + write32(mmio + GMBUS5, 0); + write32(mmio + GMBUS1, 0x4a800001 | (slave << 1)); for (i = 0; i < 128 / 4; i++) { u32 reg32; wait_rdy(mmio); - reg32 = read32(mmio + PCH_GMBUS3); + reg32 = read32(mmio + GMBUS3); edid[4 * i] = reg32 & 0xff; edid[4 * i + 1] = (reg32 >> 8) & 0xff; edid[4 * i + 2] = (reg32 >> 16) & 0xff; edid[4 * i + 3] = (reg32 >> 24) & 0xff; } wait_rdy(mmio); - write32(mmio + PCH_GMBUS1, 0x4a800000 | (slave << 1)); + write32(mmio + GMBUS1, 0x4a800000 | (slave << 1)); wait_rdy(mmio); - write32(mmio + PCH_GMBUS0, 0x48000000); - write32(mmio + PCH_GMBUS2, 0x00008000); + write32(mmio + GMBUS0, 0x48000000); + write32(mmio + GMBUS2, 0x00008000); printk (BIOS_INFO, "EDID:\n"); for (i = 0; i < 128; i++) { diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 8c08d9f..9f134d0 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -959,6 +959,11 @@ #define DVOC_ON (1<<31) #define LVDS 0x61180 #define LVDS_ON (1<<31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) /* Scratch pad debug 0 reg: */ diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 7ed2665..977d9e5 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT + select INTEL_EDID config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index ecb7ce5..7ad57cd 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -21,5 +21,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c romstage-y += dock.c ramstage-y += dock.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c -ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c index 4870fd8..4399167 100644 --- a/src/mainboard/lenovo/x60/i915.c +++ b/src/mainboard/lenovo/x60/i915.c @@ -42,16 +42,20 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <edid.h> -#include "i915io.h" - -enum { - vmsg = 1, vio = 2, vspin = 4, -}; +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/i915.h> + +#define LVDS_DETECTED (1 << 1) +#define LVDS_BORDER_ENABLE (1 << 15) +#define LVDS_PORT_ENABLE (1 << 31) +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ #define PGETLB_CTL 0x2020 -static int verbose = 0; - static unsigned int *mmio; static unsigned int graphics; static unsigned short addrport; @@ -62,74 +66,6 @@ static unsigned int physbase; #define PGETBL_ENABLED 0x00000001 -static u32 htotal, hblank, hsync, vtotal, vblank, vsync; - -const u8 x60_edid_data[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26, - 0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, - 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88, - 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, - 0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61, - 0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe, - 0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00, -}; -#define READ32(addr) io_i915_READ32(addr) -#define WRITE32(val, addr) io_i915_WRITE32(val, addr) - -static char *regname(unsigned long addr) -{ - static char name[16]; - snprintf(name, sizeof (name), "0x%lx", addr); - return name; -} - -unsigned long io_i915_READ32(unsigned long addr) -{ - unsigned long val; - outl(addr, addrport); - val = inl(dataport); - if (verbose & vio) - printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); - return val; -} - -void io_i915_WRITE32(unsigned long val, unsigned long addr) -{ - if (verbose & vio) - printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); - outl(addr, addrport); - outl(val, dataport); -} - - -/* - 2560 - 4 words per - 4 *p - 10240 - 4k bytes per page - 4096/p - 2.50 - 1700 lines - 1700 * p - 4250.00 - PTEs -*/ -static void -setgtt(int start, int end, unsigned long base, int inc) -{ - int i; - - printk(BIOS_INFO, "%s(%d,%d,0x%08lx,%d);\n", - __func__, start, end, base, inc); - - for (i = start; i < end; i++) { - u32 word = base + i*inc; - WRITE32(word|1, (i*4)|1); - } -} - int gtt_setup(unsigned int mmiobase); int gtt_setup(unsigned int mmiobase) { @@ -174,114 +110,26 @@ static unsigned long globalmicroseconds(void) return microseconds(globalstart, rdtscll()); } -extern struct iodef iodefs[]; -extern int niodefs; - -/* fill the palette. This runs when the P opcode is hit. */ -static void palette(void) -{ - int i; - unsigned long color = 0; - - for (i = 0; i < 256; i++, color += 0x010101) - io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2)); -} - -static unsigned long times[4096]; - -static int run(int index) -{ - int i, prev = 0; - struct iodef *id, *lastidread = 0; - unsigned long u, t; - if (index >= niodefs) - return index; - /* state machine! */ - for (i = index, id = &iodefs[i]; id->op; i++, id++) { - switch (id->op) { - case M: - if (verbose & vmsg) - printk(BIOS_SPEW, "%ld: %s\n", - globalmicroseconds(), id->msg); - break; - case P: - palette(); - break; - case R: - u = READ32(id->addr); - if (verbose & vio) - printk(BIOS_SPEW, "\texpect %08lx\n", id->data); - /* we're looking for something. */ - if (lastidread->addr == id->addr) { - /* they're going to be polling. - * just do it 1000 times - */ - for (t = 0; t < 1000 && id->data != u; t++) - u = READ32(id->addr); - - if (verbose & vspin) - printk(BIOS_SPEW, - "%s: # loops %ld got %08lx want %08lx\n", - regname(id->addr), - t, u, id->data); - } - lastidread = id; - break; - case W: - WRITE32(id->data, id->addr); - if (id->addr == PCH_PP_CONTROL) { - if (verbose & vio) - printk(BIOS_SPEW, "PCH_PP_CONTROL\n"); - switch (id->data & 0xf) { - case 8: - break; - case 7: - break; - default: - udelay(100000); - if (verbose & vio) - printk(BIOS_SPEW, "U %d\n", - 100000); - } - } - break; - case V: - if (id->count < 8) { - prev = verbose; - verbose = id->count; - } else { - verbose = prev; - } - printk(BIOS_SPEW, "Change verbosity to %d\n", verbose); - break; - case I: - printk(BIOS_SPEW, "run: return %d\n", i+1); - return i+1; - break; - default: - printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", - id->op, i); - return -1; - } - if (id->udelay) - udelay(id->udelay); - if (i < ARRAY_SIZE(times)) - times[i] = globalmicroseconds(); - } - printk(BIOS_SPEW, "run: return %d\n", i); - return i+1; -} - int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio, unsigned int gfx); int i915lightup(unsigned int pphysbase, unsigned int piobase, unsigned int pmmio, unsigned int pgfx) { - static struct edid edid; - - int index; + struct edid edid; + u8 x60_edid_data[256]; unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 hactive, vactive; + int i; + mmio = (void *)pmmio; addrport = piobase; dataport = addrport + 4; @@ -293,67 +141,352 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, globalstart = rdtscll(); - decode_edid((unsigned char *)&x60_edid_data, + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + intel_gmbus_read_edid(pmmio, 3, 0x50, x60_edid_data); + decode_edid(x60_edid_data, sizeof(x60_edid_data), &edid); - htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal); - - hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank); - - hsync = (edid.ha + edid.hso - 1) | - ((edid.ha + edid.hso + edid.hspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync); - - vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal); - - vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank); - - vsync = (edid.va + edid.vso - 1) | - ((edid.va + edid.vso + edid.vspw - 1) << 16); - printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync); - - printk(BIOS_SPEW, "Table has %d elements\n", niodefs); - - index = run(0); - printk(BIOS_SPEW, "Run returns %d\n", index); - - verbose = 0; - /* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * There are 4250 GTTs on Link: - * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. We will be exploiting this - * trick in a later rev of this code. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. - */ + hactive = edid.x_resolution; + vactive = edid.y_resolution; + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + +#define IS_DUAL_CHANNEL 0 +#define USE_SSC 1 + + target_frequency = IS_DUAL_CHANNEL ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + 60000) / 120000; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (120000 * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } + + + read32(pmmio+PP_ON_DELAYS); // 0x00000000 + read32(pmmio+PP_OFF_DELAYS); // 0x00000000 + write32(pmmio+PP_ON_DELAYS,0x00000000); + write32(pmmio+PP_OFF_DELAYS,0x00000000); + write32(pmmio+INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800); + write32(pmmio+RENDER_RING_BASE,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x4,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x8,0x00000000); + write32(pmmio+RENDER_RING_BASE+0xc,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x10,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x14,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x18,0x00000000); + write32(pmmio+RENDER_RING_BASE+0x1c,0x00000000); + write32(pmmio+FENCE_REG_965_0,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x4,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x8,0x00000000); + write32(pmmio+FENCE_REG_965_0+0xc,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x10,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x14,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x18,0x00000000); + write32(pmmio+FENCE_REG_965_0+0x1c,0x00000000); + write32(pmmio+VGACNTRL, VGA_DISP_DISABLE | 0x80000000); + read32(pmmio+PFIT_CONTROL); // 0x00000000 + read32(pmmio+PP_CONTROL); // 0x00000000 + write32(pmmio+PP_CONTROL,0xabcd0000); + read32(pmmio+BLC_PWM_CTL); // 0x00000000 + read32(pmmio+DVOB); // 0x00300000 + read32(pmmio+DVOC); // 0x00300000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+TV_DAC); // 0x00000000 + write32(pmmio+TV_DAC,0x08000000); + read32(pmmio+TV_DAC); // 0x08000000 + write32(pmmio+TV_DAC,0x00000000); + read32(pmmio+TV_DAC); // 0x00000000 + write32(pmmio+TV_DAC,0x00000000); + write32(pmmio+HWS_PGA,0x352d2000); + write32(pmmio+PRB0_CTL,0x00000000); + write32(pmmio+PRB0_HEAD,0x00000000); + write32(pmmio+PRB0_TAIL,0x00000000); + read32(pmmio+PRB0_HEAD); // 0x00000000 + write32(pmmio+PRB0_START,0x00000000); + write32(pmmio+PRB0_CTL,0x0001f001); + read32(pmmio+PRB0_CTL); // 0x0001f001 + read32(pmmio+PRB0_START); // 0x00000000 + read32(pmmio+PRB0_HEAD); // 0x00000000 + read32(pmmio+PRB0_TAIL); // 0x00000000 + read32(pmmio+0x6104); // 0x00000000 + write32(pmmio+0x6104,0x0000000b); + write32(pmmio+ECOSKPD,0x00010000); + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+_DSPACNTR); // 0x00000000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + write32(pmmio+_PIPEBCONF,0x00000000); + read32(pmmio+_DSPBCNTR); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x00000000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_EN,0x00000000); + read32(pmmio+PORT_HOTPLUG_STAT); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_STAT,0x00000000); + write32(pmmio+HWSTAM,0x0000effe); + write32(pmmio+_PIPEASTAT,0x00000000); + write32(pmmio+_PIPEBSTAT,0x00000000); + read32(pmmio+PORT_HOTPLUG_EN); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220); + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220 + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228); + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228 + read32(pmmio+PORT_HOTPLUG_EN); // CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220 + read32(pmmio+PORT_HOTPLUG_STAT); // 0x00000000 + write32(pmmio+PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800); + write32(pmmio+PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220); + write32(pmmio+_DSPBSIZE,0x03ff04ff); + write32(pmmio+_DSPBPOS,0x00000000); + write32(pmmio+_PIPEACONF,0x00000000); + write32(pmmio+_DSPBCNTR,0x40000000); + read32(pmmio+_DSPBCNTR); // 0x40000000 + write32(pmmio+_DSPBCNTR,0x58000000); + write32(pmmio+_DSPBADDR,0x00020000); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + read32(pmmio+TV_CTL); // 0x00000000 + write32(pmmio+TV_H_CTL_1,0x00400359); + write32(pmmio+TV_H_CTL_2,0x80480022); + write32(pmmio+TV_H_CTL_3,0x007c0344); + write32(pmmio+TV_V_CTL_1,0x00f01415); + write32(pmmio+TV_V_CTL_2,0x00060607); + write32(pmmio+TV_V_CTL_3,0x80120001); + write32(pmmio+TV_V_CTL_4,0x000900f0); + write32(pmmio+TV_V_CTL_5,0x000a00f0); + write32(pmmio+TV_V_CTL_6,0x000900f0); + write32(pmmio+TV_V_CTL_7,0x000a00f0); + write32(pmmio+TV_SC_CTL_1,0xc1710087); + write32(pmmio+TV_SC_CTL_2,0x6b405140); + write32(pmmio+TV_SC_CTL_3,0x00000000); + write32(pmmio+TV_CSC_Y,0x0332012d); + write32(pmmio+TV_CSC_Y2,0x07d30104); + write32(pmmio+TV_CSC_U,0x0733052d); + write32(pmmio+TV_CSC_U2,0x05c70200); + write32(pmmio+TV_CSC_V,0x0340030c); + write32(pmmio+TV_CSC_V2,0x06d00200); + write32(pmmio+TV_CLR_KNOBS,0x00606000); + write32(pmmio+TV_CLR_LEVEL,0x010b00e1); + write32(pmmio+_PFA_CTL_1,0x00000000); + write32(pmmio+_PFA_WIN_POS,0x00000000); + write32(pmmio+_PFA_WIN_SZ,0x00000000); + read32(pmmio+TV_DAC); // 0x70000000 + write32(pmmio+TV_DAC,0x00000000); + write32(pmmio+TV_CTL,0x000c0000); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC_SELF,0x0001002f); + write32(pmmio+FW_BLC,0x0101011a); + write32(pmmio+FW_BLC2,0x00000102); + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000); + read32(pmmio+PP_CONTROL); // 0xabcd0000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_DSPBCNTR); // 0x58000000 + write32(pmmio+_DSPBCNTR,0xd8000000); + read32(pmmio+_DSPBADDR); // 0x00020000 + write32(pmmio+_DSPBADDR,0x00020000); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_CTL); // 0x000c0000 + write32(pmmio+TV_CTL,0x800c0000); + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x800c0000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x800c0000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_DAC); // 0x70000000 + read32(pmmio+TV_CTL); // 0x800c0000 + write32(pmmio+TV_CTL,0x000c0007); + write32(pmmio+TV_DAC,0x0f0000aa); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_DAC); // 0x7f0000aa + write32(pmmio+TV_DAC,0x70000000); + write32(pmmio+TV_CTL,0x800c0000); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+TV_CTL); // 0x800c0000 + write32(pmmio+TV_CTL,0x000c0000); + write32(pmmio+INSTPM,0x08000800); + read32(pmmio+_DSPBCNTR); // 0xd8000000 + write32(pmmio+_DSPBCNTR,0x58000000); + read32(pmmio+_DSPBADDR); // 0x00020000 + write32(pmmio+_DSPBADDR,0x00020000); + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + write32(pmmio+_PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203); + read32(pmmio+_PIPEASTAT); // 0x00000000 + read32(pmmio+_PIPEASTAT); // PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203 + read32(pmmio+_DSPACNTR); // 0x00000000 + read32(pmmio+_DSPBCNTR); // 0x58000000 + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x000c0000 + read32(pmmio+LVDS); // 0x40000000 + read32(pmmio+_FDI_TXB_CTL); // 0x00000000 + read32(pmmio+TV_CTL); // 0x000c0000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+_PIPEBCONF); // 0x00000000 + read32(pmmio+LVDS); // 0x40000000 + write32(pmmio+_DPLL_B, DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x18046000); + read32(pmmio+LVDS); // 0x40000000 + write32(pmmio+LVDS, LVDS_ON | PLL_P1_DIVIDE_BY_TWO | DISPLAY_RATE_SELECT_FPA1 | 0xc0300300); + write32(pmmio+_DPLL_B, DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS | DPLLB_MODE_LVDS | 0x98046000); + read32(pmmio+_PIPEBCONF); // 0x00000000 + write32(pmmio+_HTOTAL_B,0x053f03ff); + write32(pmmio+_HBLANK_B,0x053f03ff); + write32(pmmio+_HSYNC_B,0x049f0417); + write32(pmmio+_VTOTAL_B,0x032502ff); + write32(pmmio+_VBLANK_B,0x032502ff); + write32(pmmio+_VSYNC_B,0x03080302); + write32(pmmio+_PIPEBSRC,0x03ff02ff); + write32(pmmio+_DSPASIZE,0x02ff03ff); + write32(pmmio+_DSPASTRIDE+0x4,0x00000000); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC,0x011d011a); + write32(pmmio+FW_BLC2,0x00000102); + read32(pmmio+DSPARB); // (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80000000); + write32(pmmio+FW_BLC_SELF,0x0001003f); + write32(pmmio+FW_BLC,0x011d0109); + write32(pmmio+FW_BLC2,0x00000102); + write32(pmmio+FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0x80008000); + write32(pmmio+PFIT_PGM_RATIOS,0x00000000); + write32(pmmio+PFIT_CONTROL,(PFIT_PIPE_SHIFT & 0x8) | 0x00000008); + read32(pmmio+BLC_PWM_CTL); // 0x00000000 + write32(pmmio+BLC_PWM_CTL,0x00000002); + + + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (IS_DUAL_CHANNEL ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((USE_SSC ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (IS_DUAL_CHANNEL ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((USE_SSC ? 3 : 0) << 13) + | (0x1 << (pixel_p1 - 1))); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0x20000); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), (1 << 31)); + write32(pmmio + LVDS, + LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (IS_DUAL_CHANNEL ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL | (1 << 30)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if (((reg32 >> 28) & 3) == 0) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); if (gtt_setup(pmmio)) { printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); return 0; } - setgtt(0, 800 , physbase, 4096); - - temp = READ32(PGETLB_CTL); + temp = read32(pmmio + PGETLB_CTL); printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp); if (temp & 1) @@ -362,11 +495,17 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase, printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", - (void *)graphics, FRAME_BUFFER_BYTES); - memset((void *)graphics, 0x00, FRAME_BUFFER_BYTES); + (void *)graphics, hactive * vactive * 4); + memset((void *)graphics, 0x00, hactive * vactive * 4); printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff); + set_vbe_mode_info_valid(&edid, graphics); return 0; diff --git a/src/mainboard/lenovo/x60/i915io.c b/src/mainboard/lenovo/x60/i915io.c deleted file mode 100644 index 3552867..0000000 --- a/src/mainboard/lenovo/x60/i915io.c +++ /dev/null @@ -1,2273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include "i915io.h" - -struct iodef iodefs[] = { -{V, 0,}, -{M, 1, "Linux agpgart interface v0.103", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:Intel 945GM Chipset", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:detected gtt size:262144K total, 262144K mappable", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:detected 8192K stolen memory", 0x0, 0x0, 0}, -{M, 1, "agpgart-intel 0000:00:00.0:AGP aperture is 256M @ 0xd0000000", 0x0, 0x0, 0}, -{M, 1, "[drm] Initialized drm 1.1.0 20060810", 0x0, 0x0, 0}, -{M, 1, "[drm] radeon defaulting to kernel modesetting.", 0x0, 0x0, 0}, -{M, 1, "[drm] radeon kernel modesetting enabled.", 0x0, 0x0, 0}, -{M, 1, "i915 0000:00:02.0:setting latency timer to 64", 0x0, 0x0, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{R, 1, "", PP_ON_DELAYS, 0x00000000, 0}, -{R, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, -{W, 1, "", PP_ON_DELAYS, 0x00000000, 0}, -{W, 1, "", PP_OFF_DELAYS, 0x00000000, 0}, -{W, 1, "", INSTPM+0x24, MI_ARB_C3_LP_WRITE_ENABLE | 0x08000800, 0}, -{W, 1, "", RENDER_RING_BASE, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x4, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x8, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0xc, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x10, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x14, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x18, 0x00000000, 0}, -{W, 1, "", RENDER_RING_BASE+0x1c, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x4, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x8, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0xc, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x10, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x14, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x18, 0x00000000, 0}, -{W, 1, "", FENCE_REG_965_0+0x1c, 0x00000000, 0}, -{R, 1, "", DCC, DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED | DCC_CHANNEL_XOR_BIT_17 | 0x000f0202, 0}, -{M, 1, "[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).", 0x0, 0x0, 0}, -{M, 1, "[drm] Driver supports precise vblank timestamp query.", 0x0, 0x0, 0}, -{M, 1, "i915 0000:00:02.0:Invalid ROM contents", 0x0, 0x0, 0}, -{M, 1, "[drm] failed to find VBIOS tables", 0x0, 0x0, 0}, -{M, 1, "vgaarb:device changed decodes:PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem", 0x0, 0x0, 0}, -{W, 1, "", VGACNTRL, VGA_DISP_DISABLE | 0x80000000, 0}, -{R, 1, "", PFIT_CONTROL, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 1, "", 0x5108, 0x00004a00, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{W, 1, "", 0x5100, 0x00000003, 0}, -{W, 1, "", 0x5104, 0x468000a1, 0}, -{R, 1, "", 0x5108, 0x00008a08, 0}, -{R, 1, "", 0x510c, 0xffffff00, 0}, -{R, 1, "", 0x5108, 0x00008a0c, 0}, -{R, 1, "", 0x510c, 0x00ffffff, 0}, -{R, 1, "", 0x5108, 0x00008a10, 0}, -{R, 1, "", 0x510c, 0x4000ae30, 0}, -{R, 1, "", 0x5108, 0x00008a14, 0}, -{R, 1, "", 0x510c, 0x00000000, 0}, -{R, 1, "", 0x5108, 0x00008a18, 0}, -{R, 1, "", 0x510c, 0x03010f00, 0}, -{R, 1, "", 0x5108, 0x00008a1c, 0}, -{R, 1, "", 0x510c, 0x78121980, 0}, -{R, 1, "", 0x5108, 0x00008a20, 0}, -{R, 1, "", 0x510c, 0x9175edea, 0}, -{R, 1, "", 0x5108, 0x00008a24, 0}, -{R, 1, "", 0x510c, 0x268b4f57, 0}, -{R, 1, "", 0x5108, 0x00008a28, 0}, -{R, 1, "", 0x510c, 0x21545021, 0}, -{R, 1, "", 0x5108, 0x00008a2c, 0}, -{R, 1, "", 0x510c, 0x01010008, 0}, -{R, 1, "", 0x5108, 0x00008a30, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a34, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a38, 0}, -{R, 1, "", 0x510c, 0x01010101, 0}, -{R, 1, "", 0x5108, 0x00008a3c, 0}, -{R, 1, "", 0x510c, 0x15280101, 0}, -{R, 1, "", 0x5108, 0x00008a40, 0}, -{R, 1, "", 0x510c, 0x00414000, 0}, -{R, 1, "", 0x5108, 0x00008a44, 0}, -{R, 1, "", 0x510c, 0x88183026, 0}, -{R, 1, "", 0x5108, 0x00008a48, 0}, -{R, 1, "", 0x510c, 0xb9f60036, 0}, -{R, 1, "", 0x5108, 0x00008a4c, 0}, -{R, 1, "", 0x510c, 0x18000000, 0}, -{R, 1, "", 0x5108, 0x00008a50, 0}, -{R, 1, "", 0x510c, 0x400010ed, 0}, -{R, 1, "", 0x5108, 0x00008a54, 0}, -{R, 1, "", 0x510c, 0x30260041, 0}, -{R, 1, "", 0x5108, 0x00008a58, 0}, -{R, 1, "", 0x510c, 0x00368818, 0}, -{R, 1, "", 0x5108, 0x00008a5c, 0}, -{R, 1, "", 0x510c, 0x0000b9f6, 0}, -{R, 1, "", 0x5108, 0x00008a60, 0}, -{R, 1, "", 0x510c, 0x00001800, 0}, -{R, 1, "", 0x5108, 0x00008a64, 0}, -{R, 1, "", 0x510c, 0x61000f00, 0}, -{R, 1, "", 0x5108, 0x00008a68, 0}, -{R, 1, "", 0x510c, 0x43613243, 0}, -{R, 1, "", 0x5108, 0x00008a6c, 0}, -{R, 1, "", 0x510c, 0x00010f28, 0}, -{R, 1, "", 0x5108, 0x00008a70, 0}, -{R, 1, "", 0x510c, 0x4a58a34c, 0}, -{R, 1, "", 0x5108, 0x00008a74, 0}, -{R, 1, "", 0x510c, 0xfe000000, 0}, -{R, 1, "", 0x5108, 0x00008a78, 0}, -{R, 1, "", 0x510c, 0x4e544c00, 0}, -{R, 1, "", 0x5108, 0x00008a7c, 0}, -{R, 1, "", 0x510c, 0x58313231, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x304c2d4a, 0}, -{R, 1, "", 0x5108, 0x0000ca00, 0}, -{R, 1, "", 0x510c, 0x00000a37, 0}, -{R, 1, "", 0x5108, 0x0000c200, 0}, -{W, 1, "", 0x5104, 0x48000000, 0}, -{R, 1, "", 0x5108, 0x00008800, 0}, -{W, 1, "", 0x5100, 0x00000000, 0}, -{R, 1, "", PP_CONTROL, 0x00000000, 0}, -{W, 1, "", PP_CONTROL, 0xabcd0000, 0}, -{R, 2, "", BLC_PWM_CTL, 0x00000000, 0}, -{R, 2, "", DVOB, 0x00300000, 0}, -{R, 1, "", DVOC, 0x00300000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_DAC, 0x08000000, 0}, -{R, 1, "", TV_DAC, 0x08000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{R, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{M, 1, "tsc:Refined TSC clocksource calibration:1662.499 MHz", 0x0, 0x0, 0}, -{W, 1, "", HWS_PGA, 0x352d2000, 0}, -{W, 1, "", PRB0_CTL, 0x00000000, 0}, -{M, 1, "Switching to clocksource tsc", 0x0, 0x0, 0}, -{W, 1, "", PRB0_HEAD, 0x00000000, 0}, -{W, 1, "", PRB0_TAIL, 0x00000000, 0}, -{R, 1, "", PRB0_HEAD, 0x00000000, 0}, -{W, 1, "", PRB0_START, 0x00000000, 0}, -{W, 1, "", PRB0_CTL, 0x0001f001, 0}, -{R, 1, "", PRB0_CTL, 0x0001f001, 0}, -{R, 1, "", PRB0_START, 0x00000000, 0}, -{R, 2, "", PRB0_HEAD, 0x00000000, 0}, -{R, 1, "", PRB0_TAIL, 0x00000000, 0}, -{R, 1, "", 0x6104, 0x00000000, 0}, -{W, 1, "", 0x6104, 0x0000000b, 0}, -{W, 1, "", ECOSKPD, 0x00010000, 0}, -{M, 1, "[drm] initialized overlay support", 0x0, 0x0, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DSPACNTR, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", _PIPEBCONF, 0x00000000, 0}, -{R, 1, "", _DSPBCNTR, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _FDI_TXB_CTL, 0x00000000, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEBCONF, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, -{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", HWSTAM, 0x0000effe, 0}, -{W, 1, "", _PIPEASTAT, 0x00000000, 0}, -{W, 1, "", _PIPEBSTAT, 0x00000000, 0}, -{W, 1, "", IMR, 0xffffffff, 0}, -{W, 1, "", IER, 0x00000000, 0}, -{W, 1, "", EMR, 0xffffffed, 0}, -{W, 1, "", IMR, 0xfffd73ae, 0}, -{W, 1, "", IER, 0x00028053, 0}, -{R, 1, "", PORT_HOTPLUG_EN, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_FORCE_DETECT | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000228, 0}, -{R, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{R, 1, "", PORT_HOTPLUG_STAT, 0x00000000, 0}, -{W, 1, "", PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS | 0x00000800, 0}, -{W, 1, "", PORT_HOTPLUG_EN, CRT_HOTPLUG_INT_EN | CRT_HOTPLUG_VOLTAGE_COMPARE_50 | 0x00000220, 0}, -{W, 1, "", 0x5100, 0x00000002, 0}, -{W, 1, "", 0x5104, 0x460100a1, 0}, -{R, 2, "", 0x5108, 0x00009c00, 0}, -{W, 1, "", 0x5104, 0x80000000, 0}, -{W, 1, "", 0x5104, 0x00000000, 0}, -{W, 2, "", 0x5100, 0x00000000, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _FPA0, 0x00020e08, 0}, -{W, 1, "", _FPA1, 0x00020e08, 0}, -{W, 1, "", _DPLL_A, 0x14020003, 0}, -{W, 2, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _HTOTAL_A, 0x06af04ff, 0}, -{W, 1, "", _HBLANK_A, 0x06af04ff, 0}, -{W, 1, "", _HSYNC_A, 0x05d70557, 0}, -{W, 1, "", _VTOTAL_A, 0x044f03ff, 0}, -{W, 1, "", _VBLANK_A, 0x044f03ff, 0}, -{W, 1, "", _VSYNC_A, 0x04090402, 0}, -{W, 1, "", _PIPEASRC, 0x04ff03ff, 0}, -{W, 1, "", _DSPBSIZE, 0x03ff04ff, 0}, -{W, 1, "", _DSPBPOS, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _PIPEACONF, 0x00000000, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{W, 1, "", _PIPEASTAT, PIPE_GMBUS_INTERRUPT_STATUS | PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000a03, 0}, -{R, 2, "", _PIPEASTAT, 0x00000000, 0}, -{R, 2, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{R, 1, "", _PIPEASTAT, 0x00000000, 0}, -{R, 1, "", _PIPEASTAT, PIPE_VSYNC_INTERRUPT_STATUS | PIPE_VBLANK_INTERRUPT_STATUS | PIPE_OVERLAY_UPDATED_STATUS | 0x00000203, 0}, -{W, 1, "", _DSPBCNTR, 0x40000000, 0}, -{R, 1, "", _DSPBCNTR, 0x40000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBSTRIDE, 0x00001400, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, -{W, 1, "", FW_BLC, 0x011d011a, 0}, -{W, 1, "", FW_BLC2, 0x00000102, 0}, -{R, 1, "", TV_CTL, 0x00000000, 0}, -{W, 1, "", TV_H_CTL_1, 0x00400359, 0}, -{W, 1, "", TV_H_CTL_2, 0x80480022, 0}, -{W, 1, "", TV_H_CTL_3, 0x007c0344, 0}, -{W, 1, "", TV_V_CTL_1, 0x00f01415, 0}, -{W, 1, "", TV_V_CTL_2, 0x00060607, 0}, -{W, 1, "", TV_V_CTL_3, 0x80120001, 0}, -{W, 1, "", TV_V_CTL_4, 0x000900f0, 0}, -{W, 1, "", TV_V_CTL_5, 0x000a00f0, 0}, -{W, 1, "", TV_V_CTL_6, 0x000900f0, 0}, -{W, 1, "", TV_V_CTL_7, 0x000a00f0, 0}, -{W, 1, "", TV_SC_CTL_1, 0xc1710087, 0}, -{W, 1, "", TV_SC_CTL_2, 0x6b405140, 0}, -{W, 1, "", TV_SC_CTL_3, 0x00000000, 0}, -{W, 1, "", TV_CSC_Y, 0x0332012d, 0}, -{W, 1, "", TV_CSC_Y2, 0x07d30104, 0}, -{W, 1, "", TV_CSC_U, 0x0733052d, 0}, -{W, 1, "", TV_CSC_U2, 0x05c70200, 0}, -{W, 1, "", TV_CSC_V, 0x0340030c, 0}, -{W, 1, "", TV_CSC_V2, 0x06d00200, 0}, -{W, 1, "", TV_CLR_KNOBS, 0x00606000, 0}, -{W, 1, "", TV_CLR_LEVEL, 0x010b00e1, 0}, -{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{R, 1, "", _DSPBCNTR, 0x58000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _PIPEACONF, 0x00000000, 0}, -{R, 1, "", _PIPEADSL, 0x0000029e, 0}, -{R, 3, "", _PIPEADSL, 0x000003ff, 0}, -{W, 1, "", _PFA_CTL_1, 0x80000000, 0}, -{W, 1, "", _PFA_WIN_POS, 0x00360024, 0}, -{W, 1, "", _PFA_WIN_SZ, 0x02640198, 0}, -{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | 0x80000000, 0}, -{W, 1, "", _DSPBCNTR, 0x58000000, 0}, -{R, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", _DSPBADDR, 0x00020000, 0}, -{W, 1, "", TV_H_LUMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_LUMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_LUMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_LUMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_LUMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_LUMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_LUMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_LUMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_LUMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_LUMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_LUMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_LUMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_LUMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_LUMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_LUMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_LUMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_LUMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_LUMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_LUMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_LUMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_LUMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_LUMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_LUMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_LUMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68180, 0x3ae0b160, 0}, -{W, 1, "", 0x68184, 0x2b001810, 0}, -{W, 1, "", 0x68188, 0xb0c03120, 0}, -{W, 1, "", 0x6818c, 0xb140b020, 0}, -{W, 1, "", 0x68190, 0x18283ba0, 0}, -{W, 1, "", 0x68194, 0x30c02a80, 0}, -{W, 1, "", 0x68198, 0xb020b0a0, 0}, -{W, 1, "", 0x6819c, 0x3c60b140, 0}, -{W, 1, "", 0x681a0, 0x2a201838, 0}, -{W, 1, "", 0x681a4, 0xb0a03080, 0}, -{W, 1, "", 0x681a8, 0xb120b020, 0}, -{W, 1, "", 0x681ac, 0x18383d20, 0}, -{W, 1, "", 0x681b0, 0x304029c0, 0}, -{W, 1, "", 0x681b4, 0xb040b080, 0}, -{W, 1, "", 0x681b8, 0x3de0b100, 0}, -{W, 1, "", 0x681bc, 0x29601848, 0}, -{W, 1, "", 0x681c0, 0xb0803000, 0}, -{W, 1, "", 0x681c4, 0xb100b040, 0}, -{W, 1, "", 0x681c8, 0x18483ec0, 0}, -{W, 1, "", 0x681cc, 0xb0402900, 0}, -{W, 1, "", 0x681d0, 0xb040b060, 0}, -{W, 1, "", 0x681d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x681d8, 0x28801858, 0}, -{W, 1, "", 0x681dc, 0xb060b080, 0}, -{W, 1, "", 0x681e0, 0xb0a0b060, 0}, -{W, 1, "", 0x681e4, 0x18602820, 0}, -{W, 1, "", 0x681e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_LUMA_59, 0x0000b060, 0}, -{W, 1, "", TV_H_CHROMA_0, 0xb1403000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4, 0x2e203500, 0}, -{W, 1, "", TV_H_CHROMA_0+0x8, 0x35002e20, 0}, -{W, 1, "", TV_H_CHROMA_0+0xc, 0x3000b140, 0}, -{W, 1, "", TV_H_CHROMA_0+0x10, 0x35a0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x14, 0x2dc02e80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x18, 0xb1403480, 0}, -{W, 1, "", TV_H_CHROMA_0+0x1c, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x20, 0x2ea03640, 0}, -{W, 1, "", TV_H_CHROMA_0+0x24, 0x34002d80, 0}, -{W, 1, "", TV_H_CHROMA_0+0x28, 0x3000b120, 0}, -{W, 1, "", TV_H_CHROMA_0+0x2c, 0x36e0b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x30, 0x2d202ef0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x34, 0xb1203380, 0}, -{W, 1, "", TV_H_CHROMA_0+0x38, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x3c, 0x2f303780, 0}, -{W, 1, "", TV_H_CHROMA_0+0x40, 0x33002cc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x44, 0x3000b100, 0}, -{W, 1, "", TV_H_CHROMA_0+0x48, 0x3820b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x4c, 0x2c802f50, 0}, -{W, 1, "", TV_H_CHROMA_0+0x50, 0xb10032a0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x54, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x58, 0x2f9038c0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x5c, 0x32202c20, 0}, -{W, 1, "", TV_H_CHROMA_0+0x60, 0x3000b0e0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x64, 0x3980b160, 0}, -{W, 1, "", TV_H_CHROMA_0+0x68, 0x2bc02fc0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x6c, 0xb0e031c0, 0}, -{W, 1, "", TV_H_CHROMA_0+0x70, 0xb1603000, 0}, -{W, 1, "", TV_H_CHROMA_0+0x74, 0x2ff03a20, 0}, -{W, 1, "", TV_H_CHROMA_0+0x78, 0x31602b60, 0}, -{W, 1, "", TV_H_CHROMA_0+0x7c, 0xb020b0c0, 0}, -{W, 1, "", 0x68280, 0x3ae0b160, 0}, -{W, 1, "", 0x68284, 0x2b001810, 0}, -{W, 1, "", 0x68288, 0xb0c03120, 0}, -{W, 1, "", 0x6828c, 0xb140b020, 0}, -{W, 1, "", 0x68290, 0x18283ba0, 0}, -{W, 1, "", 0x68294, 0x30c02a80, 0}, -{W, 1, "", 0x68298, 0xb020b0a0, 0}, -{W, 1, "", 0x6829c, 0x3c60b140, 0}, -{W, 1, "", 0x682a0, 0x2a201838, 0}, -{W, 1, "", 0x682a4, 0xb0a03080, 0}, -{W, 1, "", 0x682a8, 0xb120b020, 0}, -{W, 1, "", 0x682ac, 0x18383d20, 0}, -{W, 1, "", 0x682b0, 0x304029c0, 0}, -{W, 1, "", 0x682b4, 0xb040b080, 0}, -{W, 1, "", 0x682b8, 0x3de0b100, 0}, -{W, 1, "", 0x682bc, 0x29601848, 0}, -{W, 1, "", 0x682c0, 0xb0803000, 0}, -{W, 1, "", 0x682c4, 0xb100b040, 0}, -{W, 1, "", 0x682c8, 0x18483ec0, 0}, -{W, 1, "", 0x682cc, 0xb0402900, 0}, -{W, 1, "", 0x682d0, 0xb040b060, 0}, -{W, 1, "", 0x682d4, 0x3f80b0c0, 0}, -{W, 1, "", 0x682d8, 0x28801858, 0}, -{W, 1, "", 0x682dc, 0xb060b080, 0}, -{W, 1, "", 0x682e0, 0xb0a0b060, 0}, -{W, 1, "", 0x682e4, 0x18602820, 0}, -{W, 1, "", 0x682e8, 0xb0a02820, 0}, -{W, 1, "", TV_H_CHROMA_59, 0x0000b060, 0}, -{W, 1, "", TV_V_LUMA_0, 0x36403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x4, 0x2d002cc0, 0}, -{W, 1, "", TV_V_LUMA_0+0x8, 0x30003640, 0}, -{W, 1, "", TV_V_LUMA_0+0xc, 0x2d0036c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x10, 0x35c02cc0, 0}, -{W, 1, "", TV_V_LUMA_0+0x14, 0x37403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x18, 0x2c802d40, 0}, -{W, 1, "", TV_V_LUMA_0+0x1c, 0x30003540, 0}, -{W, 1, "", TV_V_LUMA_0+0x20, 0x2d8037c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x24, 0x34c02c40, 0}, -{W, 1, "", TV_V_LUMA_0+0x28, 0x38403000, 0}, -{W, 1, "", TV_V_LUMA_0+0x2c, 0x2bc02e00, 0}, -{W, 1, "", TV_V_LUMA_0+0x30, 0x30003440, 0}, -{W, 1, "", TV_V_LUMA_0+0x34, 0x2e2038c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x38, 0x34002b80, 0}, -{W, 1, "", TV_V_LUMA_0+0x3c, 0x39803000, 0}, -{W, 1, "", TV_V_LUMA_0+0x40, 0x2b402e40, 0}, -{W, 1, "", TV_V_LUMA_0+0x44, 0x30003380, 0}, -{W, 1, "", TV_V_LUMA_0+0x48, 0x2e603a00, 0}, -{W, 1, "", TV_V_LUMA_0+0x4c, 0x33402b00, 0}, -{W, 1, "", TV_V_LUMA_0+0x50, 0x3a803040, 0}, -{W, 1, "", TV_V_LUMA_0+0x54, 0x2a802ea0, 0}, -{W, 1, "", TV_V_LUMA_0+0x58, 0x30403300, 0}, -{W, 1, "", TV_V_LUMA_0+0x5c, 0x2ec03b40, 0}, -{W, 1, "", TV_V_LUMA_0+0x60, 0x32802a40, 0}, -{W, 1, "", TV_V_LUMA_0+0x64, 0x3c003040, 0}, -{W, 1, "", TV_V_LUMA_0+0x68, 0x2a002ec0, 0}, -{W, 1, "", TV_V_LUMA_0+0x6c, 0x30803240, 0}, -{W, 1, "", TV_V_LUMA_0+0x70, 0x2ec03c80, 0}, -{W, 1, "", TV_V_LUMA_0+0x74, 0x320029c0, 0}, -{W, 1, "", TV_V_LUMA_0+0x78, 0x3d403080, 0}, -{W, 1, "", TV_V_LUMA_0+0x7c, 0x29402f00, 0}, -{W, 1, "", 0x68380, 0x308031c0, 0}, -{W, 1, "", 0x68384, 0x2f203dc0, 0}, -{W, 1, "", 0x68388, 0x31802900, 0}, -{W, 1, "", 0x6838c, 0x3e8030c0, 0}, -{W, 1, "", 0x68390, 0x28802f40, 0}, -{W, 1, "", 0x68394, 0x30c03140, 0}, -{W, 1, "", 0x68398, 0x2f203f40, 0}, -{W, 1, "", 0x6839c, 0x31402840, 0}, -{W, 1, "", 0x683a0, 0x28003100, 0}, -{W, 1, "", 0x683a4, 0x28002f00, 0}, -{W, 1, "", TV_V_LUMA_42, 0x00003100, 0}, -{W, 1, "", TV_V_CHROMA_0, 0x36403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x4, 0x2d002cc0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x8, 0x30003640, 0}, -{W, 1, "", TV_V_CHROMA_0+0xc, 0x2d0036c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x10, 0x35c02cc0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x14, 0x37403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x18, 0x2c802d40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x1c, 0x30003540, 0}, -{W, 1, "", TV_V_CHROMA_0+0x20, 0x2d8037c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x24, 0x34c02c40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x28, 0x38403000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x2c, 0x2bc02e00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x30, 0x30003440, 0}, -{W, 1, "", TV_V_CHROMA_0+0x34, 0x2e2038c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x38, 0x34002b80, 0}, -{W, 1, "", TV_V_CHROMA_0+0x3c, 0x39803000, 0}, -{W, 1, "", TV_V_CHROMA_0+0x40, 0x2b402e40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x44, 0x30003380, 0}, -{W, 1, "", TV_V_CHROMA_0+0x48, 0x2e603a00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x4c, 0x33402b00, 0}, -{W, 1, "", TV_V_CHROMA_0+0x50, 0x3a803040, 0}, -{W, 1, "", TV_V_CHROMA_0+0x54, 0x2a802ea0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x58, 0x30403300, 0}, -{W, 1, "", TV_V_CHROMA_0+0x5c, 0x2ec03b40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x60, 0x32802a40, 0}, -{W, 1, "", TV_V_CHROMA_0+0x64, 0x3c003040, 0}, -{W, 1, "", TV_V_CHROMA_0+0x68, 0x2a002ec0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x6c, 0x30803240, 0}, -{W, 1, "", TV_V_CHROMA_0+0x70, 0x2ec03c80, 0}, -{W, 1, "", TV_V_CHROMA_0+0x74, 0x320029c0, 0}, -{W, 1, "", TV_V_CHROMA_0+0x78, 0x3d403080, 0}, -{W, 1, "", TV_V_CHROMA_0+0x7c, 0x29402f00, 0}, -{W, 1, "", 0x68480, 0x308031c0, 0}, -{W, 1, "", 0x68484, 0x2f203dc0, 0}, -{W, 1, "", 0x68488, 0x31802900, 0}, -{W, 1, "", 0x6848c, 0x3e8030c0, 0}, -{W, 1, "", 0x68490, 0x28802f40, 0}, -{W, 1, "", 0x68494, 0x30c03140, 0}, -{W, 1, "", 0x68498, 0x2f203f40, 0}, -{W, 1, "", 0x6849c, 0x31402840, 0}, -{W, 1, "", 0x684a0, 0x28003100, 0}, -{W, 1, "", 0x684a4, 0x28002f00, 0}, -{W, 1, "", TV_V_CHROMA_42, 0x00003100, 0}, -{R, 1, "", TV_DAC, 0x70000000, 0}, -{W, 1, "", TV_DAC, 0x00000000, 0}, -{W, 1, "", TV_CTL, 0x000c0000, 0}, -{R, 2, "", DSPARB, (DSPARB_CSTART_SHIFT & 0x4) | 0x00001d9c, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80000000, 0}, -{W, 1, "", INSTPM+0x20, 0x0001002f, 0}, -{W, 1, "", FW_BLC, 0x0101011a, 0}, -{W, 1, "", FW_BLC2, 0x00000102, 0}, -{W, 1, "", INSTPM+0x20, FW_BLC_SELF_EN_MASK | 0x80008000, 0}, -{R, 1, "", PP_CONTROL, 0xabcd0000, 0}, -{R, 1, "", LVDS, 0x40000000, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{W, 3, "", _DPLL_A, 0x94020003, 0}, -{R, 1, "", _DPLL_A, 0x94020003, 0}, -{R, 2, "", _PIPEACONF, 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0000:00:02.0 on minor 0", 0x0, 0x0, 0}, -{0,}, -}; - -int niodefs = sizeof(iodefs) / sizeof(iodefs[0]); diff --git a/src/mainboard/lenovo/x60/i915io.h b/src/mainboard/lenovo/x60/i915io.h deleted file mode 100644 index 8f37d9b..0000000 --- a/src/mainboard/lenovo/x60/i915io.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i915_reg.h" -#include "drm_dp_helper.h" - -/* things that are, strangely, not defined anywhere? */ -#define PCH_PP_UNLOCK 0xabcd0000 -#define WMx_LP_SR_EN (1<<31) - -/* Google Link-specific defines */ -/* how many 4096-byte pages do we need for the framebuffer? - * There are 32 bits per pixel, or 4 bytes, - * which means 1024 pixels per page. - * HencetThere are 4250 GTTs on Link: - * 1024 (X) * 768 (Y) pixels / 1024 pixels per page. - */ -#define FRAME_BUFFER_PAGES ((1024*768)/1024) -#define FRAME_BUFFER_BYTES (0x300000) - -/* One-letter commands for code not meant to be ready for humans. - * The code was generated by a set of programs/scripts. - * M print out a kernel message - * R read a register. We do these mainly to ensure that if hardware wanted - * the register read, it was read; also, in debug, we can see what was expected - * and what was found. This has proven *very* useful to get this debugged. - * The udelay, if non-zero, will make sure there is a - * udelay() call with the value. - * The count is from the kernel and tells us how many times this read was done. - * Also useful for debugging and the state - * machine uses the info to drive a poll. - * W Write a register - * V set verbosity. It's a bit mask. - * 0 -> nothing - * 1 -> print kernel messages - * 2 -> print IO ops - * 4 -> print the number of times we spin on a register in a poll - * 8 -> restore whatever the previous verbosity level was - * (only one deep stack) - * - * Again, this is not really meant for human consumption. There is not a poll - * operator as such because, sometimes, there is a read/write/read where the - * second read is a poll, and this chipset is so touchy I'm reluctant to move - * things around and/or delete too many reads. - */ -#define M 1 -#define R 2 -#define W 4 -#define V 8 -#define I 16 -#define P 32 - -struct iodef { - unsigned char op; - unsigned int count; - const char *msg; - unsigned long addr; - unsigned long data; - unsigned long udelay; -}; - -/* i915.c */ -unsigned long io_i915_READ32(unsigned long addr); -void io_i915_WRITE32(unsigned long val, unsigned long addr); - -/* intel_dp.c */ -u32 pack_aux(u32 *src, int src_bytes); -void unpack_aux(u32 src, u32 *dst, int dst_bytes); -int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, - u32 *recv, int recv_size); diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 433152c..ad63c97 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -40,8 +40,8 @@ static void gma_func0_init(struct device *dev) /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); - + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT /* PCI Init, will run VBIOS */ @@ -92,7 +92,7 @@ static void gma_func1_init(struct device *dev) /* IGD needs to be Bus Master, also enable IO accesss */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | - PCI_COMMAND_MASTER | PCI_COMMAND_IO); + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); if (get_option(&val, "tft_brightness") == CB_SUCCESS) pci_write_config8(dev, 0xf4, val);

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coreboot-gerrit February 2014