coreboot-gerrit February 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 2981933 baytrail: Enable GFX device
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit 29819339d5dbb744ad2f81e3563713e9c0f46bbc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 28 15:49:34 2013 -0700 baytrail: Enable GFX device - Ungate display in PUNIT - Set GSM to 64MB since 32MB is not supported in <C0 stepping - Initialize power management registers in GTT - Execute VBIOS if found BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot to dev screen via HDMI on rambi Change-Id: Idb032c7ea7f16b651b4c921e3429a652fe663a5d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174922 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4907 for details. -gerrit

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Patch merged into coreboot/master: 803303a baytrail: IOSF write functions need to set data before control
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit 803303aa84a1dfd6ea32c812d21714d1178de180 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Oct 28 14:18:38 2013 -0700 baytrail: IOSF write functions need to set data before control The data needs to be available in the register before the control bits are set to make the write happen. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=successfully ungate power on PUNIT on rambi Change-Id: I8fae60d5385ce9a401c1dec9cbb39b70d157a6c2 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174898 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/4906 for details. -gerrit

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Patch merged into coreboot/master: 73a54b9 rambi: add chromeos EC support
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit 73a54b9b1cf468f87122700d3f1c25197b005d7c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 28 11:24:53 2013 -0500 rambi: add chromeos EC support As rambi has the ChromeOS EC on it the EC needs to be configured properly. Do this along with updating the ChromeOS support for passing on write protect state, recovery mode and developer mode. BUG=chrome-os-partner:23387 BRANCH=None TEST=Built and booted to depthcharge. EC software sync appears to work correctly. Additionaly, 'mainboard_ec_init' appears in the console output. Change-Id: I40c5c9410b4acaba662c2b18b261dd4514a7410a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174714 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4905 for details. -gerrit

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Patch merged into coreboot/master: d8121c2 baytrail: initialize chromeos EC if present in romstage
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit d8121c262fd67126b3249f6d0ec94c63ae6d89b5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 28 11:20:35 2013 -0500 baytrail: initialize chromeos EC if present in romstage The EC needs to be initialized early in romstage. Therefore perform the call after console has been initialized in order to view any messages that the code may spit out. BUG=chrome-os-partner:23387 BRANCH=None TEST=Built and booted with recovery mode and EC in RW. Noted that system reboots the EC. Change-Id: I35aa3ea4aa3dbd9bd806b6498e227f45ceebd7a1 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174713 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4904 for details. -gerrit

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Patch merged into coreboot/master: a4986cb baytrail: use version 2 of efi wrapper
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit a4986cb1e33252877ebec0a89c54a1a57431de04 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Oct 28 09:54:22 2013 -0500 baytrail: use version 2 of efi wrapper Version 2 of the efi wrapper wants the speed of the TSC timer initialized in the parameter structure. BUG=chrome-os-partner:22866 BRANCH=None TEST=Built and booted through depthcharge. No errors spit out by wrapper. CQ-DEPEND=CL:*147256 Change-Id: I9cd265ea6bde93be85fc6fbc905d83af57fc2773 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174712 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4903 for details. -gerrit

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Patch merged into coreboot/master: e45421b baytrail: remove gfx read_resources() work around
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit e45421b66ede1c5a8b7474f08d040ca4e96c53df Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 25 09:12:45 2013 -0500 baytrail: remove gfx read_resources() work around Before the special PUNIT settings the GFX pci device had the same device id as the transaction router. This required a special case in the transaction router's driver to do the proper thing for read_resources(). However, that requirement is no longer needed as the PUNIT special message is now being done. Therefore, remove the work around. BUG=None BRANCH=None TEST=Built and looked at resource allocation logs to confirm work around is no longer needed. Change-Id: I90b155cb5560ca3291f146c2f586456e5529f6b2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174652 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4902 for details. -gerrit

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Patch merged into coreboot/master: 2b8ed2c baytrail: get rid of global microcode_ptr
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit 2b8ed2c0e32cf5639b1f0dffacee11d2d64ab229 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 24 14:55:42 2013 -0500 baytrail: get rid of global microcode_ptr A global microcode_ptr was added when doing the MP development work. However, this is unnecessary as the pattrs structure already contains the pointer. Use that instead. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted. Microcode still being loaded correctly. Change-Id: I0abba66fc7741699411d14bd3e1bb28cf1618028 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174552 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> See http://review.coreboot.org/4901 for details. -gerrit

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Patch merged into coreboot/master: c0810e1 baytrail: add microcode version 319
by gerrit＠coreboot.org 24 Feb '14

24 Feb '14

the following patch was just integrated into master: commit c0810e1fb537b21d44c0186f660cdbf14f175f9f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Oct 24 14:54:04 2013 -0500 baytrail: add microcode version 319 Update microcode version to 319. BUG=None BRANCH=None TEST=Built and booted. Noted 319 being used. Change-Id: I008f90a1c6b542d979e34da22e9f375224c0ffeb Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174551 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See http://review.coreboot.org/4900 for details. -gerrit

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Patch set updated for coreboot: 67f0176 qemu: Support textmode gfx init.
by Vladimir Serbinenko 24 Feb '14

24 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5283 -gerrit commit 67f017615a0d918942f52c5a16cc9855f5ef4368 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 22 10:35:45 2014 +0100 qemu: Support textmode gfx init. Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/emulation/qemu/Kconfig | 3 +++ src/drivers/emulation/qemu/bochs.c | 9 +++++++++ src/drivers/emulation/qemu/cirrus.c | 10 ++++++++++ src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/mainboard/emulation/qemu-q35/Kconfig | 1 + 5 files changed, 24 insertions(+) diff --git a/src/drivers/emulation/qemu/Kconfig b/src/drivers/emulation/qemu/Kconfig index 56fdaca..168b1c5 100644 --- a/src/drivers/emulation/qemu/Kconfig +++ b/src/drivers/emulation/qemu/Kconfig @@ -3,6 +3,7 @@ config DRIVERS_EMULATION_QEMU_BOCHS default y depends on BOARD_EMULATION_QEMU_X86 depends on MAINBOARD_DO_NATIVE_VGA_INIT + select VGA help VGA driver for qemu emulated vga cards supporting the bochs dispi interface. This includes @@ -13,9 +14,11 @@ config DRIVERS_EMULATION_QEMU_BOCHS config DRIVERS_EMULATION_QEMU_BOCHS_XRES int "bochs vga xres" default 800 + depends on FRAMEBUFFER_KEEP_VESA_MODE depends on DRIVERS_EMULATION_QEMU_BOCHS config DRIVERS_EMULATION_QEMU_BOCHS_YRES int "bochs vga yres" default 600 + depends on FRAMEBUFFER_KEEP_VESA_MODE depends on DRIVERS_EMULATION_QEMU_BOCHS diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 1e7986c..715c94c 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -11,6 +11,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <pc80/vga.h> +#include <pc80/vga_io.h> /* VGA init. We use the Bochs VESA VBE extensions */ #define VBE_DISPI_IOPORT_INDEX 0x01CE @@ -39,6 +41,7 @@ #define VBE_DISPI_LFB_ENABLED 0x40 #define VBE_DISPI_NOCLEARMEM 0x80 +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; @@ -53,9 +56,11 @@ static int bochs_read(int index) outw(index, VBE_DISPI_IOPORT_INDEX); return inw(VBE_DISPI_IOPORT_DATA); } +#endif static void bochs_init(device_t dev) { +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) struct edid edid; int id, mem, bar; u32 addr; @@ -111,6 +116,10 @@ static void bochs_init(device_t dev) edid.bytes_per_line = width * 4; edid.bpp = 32; set_vbe_mode_info_valid(&edid, addr); +#else + vga_misc_write(0x1); + vga_textmode_init(); +#endif } static struct device_operations qemu_graph_ops = { diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index b4928fe..5f8a01e 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -36,9 +36,11 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; static u32 addr = 0; +#endif enum { @@ -197,6 +199,7 @@ enum #define CIRRUS_SR_EXTENDED_MODE_32BPP 0x08 #define CIRRUS_HIDDEN_DAC_888COLOR 0xc5 +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) static void write_hidden_dac (uint8_t data) { @@ -207,9 +210,11 @@ write_hidden_dac (uint8_t data) inb (0x3c6); outb (data, 0x3c6); } +#endif static void cirrus_init(device_t dev) { +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) uint8_t cr_ext, cr_overlay; unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR; uint8_t sr_ext = 0, hidden_dac = 0; @@ -335,6 +340,11 @@ static void cirrus_init(device_t dev) edid.bytes_per_line = width * 4; edid.bpp = 32; set_vbe_mode_info_valid(&edid, addr); +#else + vga_misc_write(0x1); + + vga_textmode_init(); +#endif } static struct device_operations qemu_cirrus_graph_ops = { diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 0d4d07a..b9df41e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index cd7024b..ad7576b 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EARLY_CBMEM_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG config MAINBOARD_DIR string

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Patch set updated for coreboot: bd00913 devices: Allow to configure textmode in native gfx init.
by Vladimir Serbinenko 24 Feb '14

24 Feb '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5282 -gerrit commit bd00913ae6bf9f05cac0eea296fc47b0e573ea26 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Feb 22 10:34:47 2014 +0100 devices: Allow to configure textmode in native gfx init. Usefull to select between text mode which offers best compatibility with payloads and gfx mode which makes the best-looking screen. Also right now we have an unfortunate situation when qemu is in gfx mode while most real systems use text mode. Change-Id: Ifad7ba197875edfdd06eb932afeb5800229ef055 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/Kconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 4b2d4b8..eaa0c04 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -25,6 +25,10 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT bool default n +config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + bool + default n + config MAINBOARD_DO_NATIVE_VGA_INIT bool "Use native graphics initialization" depends on MAINBOARD_HAS_NATIVE_VGA_INIT @@ -431,7 +435,7 @@ config FRAMEBUFFER_VESA_MODE config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || !MAINBOARD_DO_NATIVE_VGA_INIT + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || (MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG && MAINBOARD_DO_NATIVE_VGA_INIT) help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a

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coreboot-gerrit February 2014