coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: d69ece1 gitmodules: Fix 3rdparty updates
by Stefan Reinauer 28 Jun '13

28 Jun '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3566 -gerrit commit d69ece1ab906b043486d4760d1a47100643707b9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jun 27 15:32:05 2013 -0700 gitmodules: Fix 3rdparty updates Commit 039223a: gitmodules: Ignore 3rdparty in "diff family" changed the behavior of our 3rdparty repository and disallowed updates to the checked out hash. Instead of "ignore=all" we want "ignore=dirty" to ignore local changes but allow changing to the HEAD of the 3rdparty repo. Change-Id: I66c35ad4fcfb0efb0ba611f67648a096a6de1479 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index 25ba6e3..8702ff0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,4 +2,4 @@ path = 3rdparty url = ../blobs.git update = none - ignore = all + ignore = dirty

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Patch set updated for coreboot: 232ff06 Add an alternative bootblock implementation.
by Denis Carikli 27 Jun '13

27 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit 232ff06c084858ce33e170905e1f7c1bacb1c669 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add an alternative bootblock implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 ++++++ src/arch/x86/include/arch/cbfs.h | 8 ++++ src/arch/x86/init/bootblock_failboot.c | 53 ++++++++++++++++++++++ src/cpu/amd/agesa/cache_as_ram.inc | 9 +++- src/cpu/amd/car/cache_as_ram.inc | 9 +++- src/cpu/amd/geode_gx2/cache_as_ram.inc | 11 +++++ src/cpu/amd/geode_lx/cache_as_ram.inc | 11 +++++ src/cpu/intel/car/cache_as_ram.inc | 9 ++++ src/cpu/intel/car/cache_as_ram_ht.inc | 12 +++++ src/cpu/intel/haswell/cache_as_ram.inc | 11 +++++ src/cpu/intel/model_2065x/cache_as_ram.inc | 9 ++++ src/cpu/intel/model_206ax/cache_as_ram.inc | 9 ++++ src/cpu/intel/model_6ex/cache_as_ram.inc | 9 ++++ src/cpu/via/car/cache_as_ram.inc | 8 ++++ src/cpu/x86/16bit/entry16.inc | 8 ++++ src/cpu/x86/32bit/entry32.inc | 10 +++- src/cpu/x86/fpu_enable.inc | 9 +++- src/cpu/x86/sse_enable.inc | 9 +++- src/drivers/pc80/mc146818rtc_early.c | 11 +++++ .../emulation/qemu-i440fx/cache_as_ram.inc | 10 ++++ src/northbridge/intel/i5000/halt_second_bsp.S | 9 ++++ 21 files changed, 241 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..721a487 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_failboot.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index 8a61d6e..b6df10b 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -45,4 +45,12 @@ static inline void call(unsigned long addr, unsigned long bist) { asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); } + +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline void call_cmos_stage(unsigned long addr, unsigned long bist, int normal) +{ + asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist),"b" (normal)); +} +#endif + #endif diff --git a/src/arch/x86/init/bootblock_failboot.c b/src/arch/x86/init/bootblock_failboot.c new file mode 100644 index 0000000..17e5ee3 --- /dev/null +++ b/src/arch/x86/init/bootblock_failboot.c @@ -0,0 +1,53 @@ +#include <bootblock_common.h> +#include <pc80/mc146818rtc.h> + +static const char *get_fallback(const char *stagelist) { + while (*stagelist) stagelist++; + return ++stagelist; +} + +static void main(unsigned long bist) +{ + unsigned long entry; + int boot_mode; + const char *default_filenames = "normal/romstage\0fallback/romstage"; + + if (boot_cpu()) { + bootblock_mainboard_init(); + +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + boot_mode = last_boot_normal(); + } else { + + /* Questionable single byte read from CMOS. + * Do not add any other CMOS access in the + * bootblock for AP CPUs. + */ + boot_mode = last_boot_normal(); + } + + char *filenames = (char *)walkcbfs("coreboot-stages"); + if (!filenames) { + filenames = default_filenames; + } + char *normal_candidate = filenames; + + if (boot_mode) + entry = findstage(normal_candidate); + else + entry = findstage(get_fallback(normal_candidate)); + + /* reset nvram to fallback */ + set_boot_fallback(); + + if (entry) call_cmos_stage(entry, bist, boot_mode); + + /* run fallback if normal can't be found */ + entry = findstage(get_fallback(normal_candidate)); + if (entry) call_cmos_stage(entry, bist, boot_mode); + + /* duh. we're stuck */ + asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); +} diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index c645a1e..780add6 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -57,7 +57,10 @@ cache_as_ram_setup: /* Save the BIST result */ cvtsi2sd %ebp, %xmm0 - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Not implemented for AGESA" +#endif /* for normal part %ebx already contain cpu_init_detected from fallback call */ /* Save the cpu_init_detected */ @@ -70,6 +73,10 @@ cache_as_ram_setup: /* Restore the BIST result */ cvtsd2si %xmm0, %edx +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Not implemented for AGESA" +#endif /* Restore the cpu_init_detected */ cvtsd2si %xmm1, %ebx diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..c8d6177 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -45,6 +45,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* * For normal part %ebx already contain cpu_init_detected @@ -408,7 +412,10 @@ CAR_FAM10_ap_out: /* Restore the BIST result. */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp pushl %ebx /* Init detected. */ diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..28c3f16 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -38,6 +38,11 @@ /** /***************************************************************************/ DCacheSetup: +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode GX2" + //movl %ebx, ??? +#endif /* Save the BIST result */ movl %eax, %ebx @@ -154,6 +159,12 @@ DCacheSetupGood: /* Restore the BIST result */ movl %ebx, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode GX2" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 45fd166..16a19e0 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -35,6 +35,11 @@ /** /***************************************************************************/ DCacheSetup: +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for Geode LX" + //movl %ebx, %??? +#endif /* Save the BIST result */ movl %eax, %ebx @@ -180,6 +185,12 @@ DCacheSetupGood: /* Restore the BIST result */ movl %ebx, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for Geode LX" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8..a3a9c29 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -32,6 +32,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %ebp +#endif CacheAsRam: /* Check whether the processor has HT capability. */ @@ -319,10 +323,15 @@ clear_fixed_var_mtrr_out: lout: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp pushl %eax /* BIST */ + // pushl %ebx /* nvram's boot_option */ ??? No ebp used after that... call main /* We don't need CAR from now on. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 8a845e9..954114f 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -35,6 +35,12 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available in src/cpu/intel/car/cache_as_ram_ht.inc" + //movl %ebx, %??? /* %esp and %ebx are used later... */ +#endif + cache_as_ram: post_code(0x20) @@ -343,6 +349,12 @@ no_msr_11e: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode src/cpu/intel/car/cache_as_ram_ht.inc" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 8601f46..7688a50 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -43,6 +43,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for haswell" + //movl %ebx, ??? /* %esp and %ebx are used later... */ +#endif cache_as_ram: post_code(0x20) @@ -170,6 +175,12 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for haswell" + //movl ??? , %ebx ??? +#endif + /* Setup the stack. */ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index db0eaae..2893ea7 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -38,6 +38,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -174,6 +179,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif before_romstage: post_code(0x29) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2652cb7..d9fb482 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -38,6 +38,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -174,6 +179,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif before_romstage: post_code(0x29) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 50fab35..ed25ef8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -30,6 +30,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -138,6 +143,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif post_code(0x23) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b83..eea0b93 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -35,6 +35,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif CacheAsRam: @@ -204,6 +208,10 @@ testok: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e4613bf..b7f90c2 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,6 +36,10 @@ _start: cli /* Save the BIST result */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif post_code(POST_RESET_VECTOR_CORRECT) @@ -114,6 +118,10 @@ _start: /* Restore BIST to %eax */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* Now that we are in protected mode jump to a 32 bit code segment. */ data32 ljmp $ROM_CODE_SEG, $__protected_start diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index f74e1b8..9299316 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -51,7 +51,10 @@ protected_start: __protected_start: /* Save the BIST value */ movl %eax, %ebp - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif post_code(POST_ENTER_PROTECTED_MODE) movw $ROM_DATA_SEG, %ax @@ -63,4 +66,7 @@ __protected_start: /* Restore the BIST value to %eax */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc index c08e8a0..2d43b34 100644 --- a/src/cpu/x86/fpu_enable.inc +++ b/src/cpu/x86/fpu_enable.inc @@ -20,7 +20,10 @@ __fpu_start: /* Preserve BIST. */ movl %eax, %ebp - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* * Clear the CR0[2] bit (the "Emulation" flag, EM). * @@ -37,3 +40,7 @@ __fpu_start: /* Restore BIST. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc index 09dea02..1e1ed49 100644 --- a/src/cpu/x86/sse_enable.inc +++ b/src/cpu/x86/sse_enable.inc @@ -19,6 +19,10 @@ /* Preserve BIST. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* Enable SSE instructions. */ movl %cr4, %eax @@ -27,4 +31,7 @@ /* Restore BIST. */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..df8215a 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,17 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline void set_boot_fallback(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + /* set it back to Fallback */ + byte &= ~(1<<0); + cmos_write(byte, RTC_BOOT_BYTE); +} +#endif + static inline int do_normal_boot(void) { unsigned char byte; diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 11ac91d..deb7b65 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -31,6 +31,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #warning "CONFIG_X86_BOOTBLOCK_FAILBOOT is used, the build may fail" + movl %ebx, %esp +#endif cache_as_ram: post_code(0x20) @@ -49,6 +54,11 @@ cache_as_ram: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #warning "CONFIG_X86_BOOTBLOCK_FAILBOOT is used, the build may fail" + movl %esp, %ebx +#endif movl %esp, %ebp pushl %eax diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 041807e..f21e23d 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -1,6 +1,11 @@ /* Save BIST result */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %ebx is not used */ + /* Do not clobber %ebx */ +#endif /* check if SPAD0 is cleared. If yes, it means this was a hard reset */ movl $0x800080d0, %eax @@ -56,3 +61,7 @@ loop: hlt /* Restore BIST */ mov %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* Nothing to do, since %ebx is not used */ +#endif

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Patch set updated for coreboot: 58ed92a i82801gx: Enable CONFIG_SPI_FLASH
by Denis Carikli 27 Jun '13

27 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3550 -gerrit commit 58ed92a6e69b433a6024c785223c3d57024e8661 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 26 19:55:21 2013 +0200 i82801gx: Enable CONFIG_SPI_FLASH That permits the user to select CONFIG_ELOG in "make menuconfig". Change-Id: I306d79697c730ba03730590554aeb540c0a1b5ed Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/bd82x6x/spi.c | 3 ++- src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801gx/Makefile.inc | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..943cda6 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -309,7 +309,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, */ static inline int get_ich_version(uint16_t device_id) { - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || + device_id == PCI_DEVICE_ID_INTEL_82801GBM_LPC) return 7; if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a991f60..716c5c7 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER + select SPI_FLASH if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index c21b684..ad9a66e 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -33,6 +33,8 @@ ramstage-y += usb_ehci.c ramstage-y += reset.c ramstage-y += watchdog.c +ramstage-y += ../bd82x6x/spi.c + ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

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Patch set updated for coreboot: ce412c1 Add an alternative bootblock implementation.
by Denis Carikli 27 Jun '13

27 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit ce412c14d773e34fa25639d50e0398e524f4457d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add an alternative bootblock implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 ++++++ src/arch/x86/include/arch/cbfs.h | 8 ++++ src/arch/x86/init/bootblock_failboot.c | 53 ++++++++++++++++++++++ src/cpu/amd/agesa/cache_as_ram.inc | 9 +++- src/cpu/amd/car/cache_as_ram.inc | 9 +++- src/cpu/amd/geode_gx2/cache_as_ram.inc | 11 +++++ src/cpu/amd/geode_lx/cache_as_ram.inc | 11 +++++ src/cpu/intel/car/cache_as_ram.inc | 9 ++++ src/cpu/intel/car/cache_as_ram_ht.inc | 12 +++++ src/cpu/intel/haswell/cache_as_ram.inc | 11 +++++ src/cpu/intel/model_2065x/cache_as_ram.inc | 9 ++++ src/cpu/intel/model_206ax/cache_as_ram.inc | 9 ++++ src/cpu/intel/model_6ex/cache_as_ram.inc | 9 ++++ src/cpu/via/car/cache_as_ram.inc | 8 ++++ src/cpu/x86/16bit/entry16.inc | 8 ++++ src/cpu/x86/32bit/entry32.inc | 10 +++- src/cpu/x86/fpu_enable.inc | 9 +++- src/cpu/x86/sse_enable.inc | 9 +++- src/drivers/pc80/mc146818rtc_early.c | 11 +++++ .../emulation/qemu-i440fx/cache_as_ram.inc | 10 ++++ src/northbridge/intel/i5000/halt_second_bsp.S | 9 ++++ 21 files changed, 241 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..8942a66 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failling to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting(like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_failboot.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index 8a61d6e..b6df10b 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -45,4 +45,12 @@ static inline void call(unsigned long addr, unsigned long bist) { asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); } + +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline void call_cmos_stage(unsigned long addr, unsigned long bist, int normal) +{ + asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist),"b" (normal)); +} +#endif + #endif diff --git a/src/arch/x86/init/bootblock_failboot.c b/src/arch/x86/init/bootblock_failboot.c new file mode 100644 index 0000000..17e5ee3 --- /dev/null +++ b/src/arch/x86/init/bootblock_failboot.c @@ -0,0 +1,53 @@ +#include <bootblock_common.h> +#include <pc80/mc146818rtc.h> + +static const char *get_fallback(const char *stagelist) { + while (*stagelist) stagelist++; + return ++stagelist; +} + +static void main(unsigned long bist) +{ + unsigned long entry; + int boot_mode; + const char *default_filenames = "normal/romstage\0fallback/romstage"; + + if (boot_cpu()) { + bootblock_mainboard_init(); + +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + boot_mode = last_boot_normal(); + } else { + + /* Questionable single byte read from CMOS. + * Do not add any other CMOS access in the + * bootblock for AP CPUs. + */ + boot_mode = last_boot_normal(); + } + + char *filenames = (char *)walkcbfs("coreboot-stages"); + if (!filenames) { + filenames = default_filenames; + } + char *normal_candidate = filenames; + + if (boot_mode) + entry = findstage(normal_candidate); + else + entry = findstage(get_fallback(normal_candidate)); + + /* reset nvram to fallback */ + set_boot_fallback(); + + if (entry) call_cmos_stage(entry, bist, boot_mode); + + /* run fallback if normal can't be found */ + entry = findstage(get_fallback(normal_candidate)); + if (entry) call_cmos_stage(entry, bist, boot_mode); + + /* duh. we're stuck */ + asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); +} diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index c645a1e..780add6 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -57,7 +57,10 @@ cache_as_ram_setup: /* Save the BIST result */ cvtsi2sd %ebp, %xmm0 - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Not implemented for AGESA" +#endif /* for normal part %ebx already contain cpu_init_detected from fallback call */ /* Save the cpu_init_detected */ @@ -70,6 +73,10 @@ cache_as_ram_setup: /* Restore the BIST result */ cvtsd2si %xmm0, %edx +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Not implemented for AGESA" +#endif /* Restore the cpu_init_detected */ cvtsd2si %xmm1, %ebx diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..c8d6177 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -45,6 +45,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* * For normal part %ebx already contain cpu_init_detected @@ -408,7 +412,10 @@ CAR_FAM10_ap_out: /* Restore the BIST result. */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp pushl %ebx /* Init detected. */ diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..28c3f16 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -38,6 +38,11 @@ /** /***************************************************************************/ DCacheSetup: +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode GX2" + //movl %ebx, ??? +#endif /* Save the BIST result */ movl %eax, %ebx @@ -154,6 +159,12 @@ DCacheSetupGood: /* Restore the BIST result */ movl %ebx, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode GX2" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 45fd166..16a19e0 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -35,6 +35,11 @@ /** /***************************************************************************/ DCacheSetup: +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for Geode LX" + //movl %ebx, %??? +#endif /* Save the BIST result */ movl %eax, %ebx @@ -180,6 +185,12 @@ DCacheSetupGood: /* Restore the BIST result */ movl %ebx, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for Geode LX" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8..a3a9c29 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -32,6 +32,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %ebp +#endif CacheAsRam: /* Check whether the processor has HT capability. */ @@ -319,10 +323,15 @@ clear_fixed_var_mtrr_out: lout: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp pushl %eax /* BIST */ + // pushl %ebx /* nvram's boot_option */ ??? No ebp used after that... call main /* We don't need CAR from now on. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 8a845e9..954114f 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -35,6 +35,12 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available in src/cpu/intel/car/cache_as_ram_ht.inc" + //movl %ebx, %??? /* %esp and %ebx are used later... */ +#endif + cache_as_ram: post_code(0x20) @@ -343,6 +349,12 @@ no_msr_11e: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode src/cpu/intel/car/cache_as_ram_ht.inc" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 8601f46..7688a50 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -43,6 +43,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for haswell" + //movl %ebx, ??? /* %esp and %ebx are used later... */ +#endif cache_as_ram: post_code(0x20) @@ -170,6 +175,12 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for haswell" + //movl ??? , %ebx ??? +#endif + /* Setup the stack. */ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index db0eaae..2893ea7 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -38,6 +38,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -174,6 +179,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif before_romstage: post_code(0x29) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2652cb7..d9fb482 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -38,6 +38,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -174,6 +179,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif before_romstage: post_code(0x29) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 50fab35..ed25ef8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -30,6 +30,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -138,6 +143,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif post_code(0x23) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b83..eea0b93 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -35,6 +35,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif CacheAsRam: @@ -204,6 +208,10 @@ testok: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e4613bf..b7f90c2 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,6 +36,10 @@ _start: cli /* Save the BIST result */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif post_code(POST_RESET_VECTOR_CORRECT) @@ -114,6 +118,10 @@ _start: /* Restore BIST to %eax */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* Now that we are in protected mode jump to a 32 bit code segment. */ data32 ljmp $ROM_CODE_SEG, $__protected_start diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index f74e1b8..9299316 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -51,7 +51,10 @@ protected_start: __protected_start: /* Save the BIST value */ movl %eax, %ebp - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif post_code(POST_ENTER_PROTECTED_MODE) movw $ROM_DATA_SEG, %ax @@ -63,4 +66,7 @@ __protected_start: /* Restore the BIST value to %eax */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc index c08e8a0..2d43b34 100644 --- a/src/cpu/x86/fpu_enable.inc +++ b/src/cpu/x86/fpu_enable.inc @@ -20,7 +20,10 @@ __fpu_start: /* Preserve BIST. */ movl %eax, %ebp - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* * Clear the CR0[2] bit (the "Emulation" flag, EM). * @@ -37,3 +40,7 @@ __fpu_start: /* Restore BIST. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc index 09dea02..1e1ed49 100644 --- a/src/cpu/x86/sse_enable.inc +++ b/src/cpu/x86/sse_enable.inc @@ -19,6 +19,10 @@ /* Preserve BIST. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* Enable SSE instructions. */ movl %cr4, %eax @@ -27,4 +31,7 @@ /* Restore BIST. */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..df8215a 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,17 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline void set_boot_fallback(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + /* set it back to Fallback */ + byte &= ~(1<<0); + cmos_write(byte, RTC_BOOT_BYTE); +} +#endif + static inline int do_normal_boot(void) { unsigned char byte; diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 11ac91d..deb7b65 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -31,6 +31,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #warning "CONFIG_X86_BOOTBLOCK_FAILBOOT is used, the build may fail" + movl %ebx, %esp +#endif cache_as_ram: post_code(0x20) @@ -49,6 +54,11 @@ cache_as_ram: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #warning "CONFIG_X86_BOOTBLOCK_FAILBOOT is used, the build may fail" + movl %esp, %ebx +#endif movl %esp, %ebp pushl %eax diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 041807e..f21e23d 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -1,6 +1,11 @@ /* Save BIST result */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %ebx is not used */ + /* Do not clobber %ebx */ +#endif /* check if SPAD0 is cleared. If yes, it means this was a hard reset */ movl $0x800080d0, %eax @@ -56,3 +61,7 @@ loop: hlt /* Restore BIST */ mov %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* Nothing to do, since %ebx is not used */ +#endif

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Patch set updated for coreboot: 0b8487f i82801gx: Enable CONFIG_SPI_FLASH
by Denis Carikli 27 Jun '13

27 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3550 -gerrit commit 0b8487f8915c0fd7e165cd9cd5657a21cdfd2be5 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 26 19:55:21 2013 +0200 i82801gx: Enable CONFIG_SPI_FLASH Change-Id: I306d79697c730ba03730590554aeb540c0a1b5ed Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/bd82x6x/spi.c | 3 ++- src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801gx/Makefile.inc | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..943cda6 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -309,7 +309,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, */ static inline int get_ich_version(uint16_t device_id) { - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC || + device_id == PCI_DEVICE_ID_INTEL_82801GBM_LPC) return 7; if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a991f60..716c5c7 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER + select SPI_FLASH if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index c21b684..ad9a66e 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -33,6 +33,8 @@ ramstage-y += usb_ehci.c ramstage-y += reset.c ramstage-y += watchdog.c +ramstage-y += ../bd82x6x/spi.c + ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

1 0

Patch set updated for coreboot: effcfe2 ELOG: Fix warning to fix the compilation.
by Denis Carikli 27 Jun '13

27 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3551 -gerrit commit effcfe25c797cc1dbf448a261b41395bd2680140 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 26 20:04:49 2013 +0200 ELOG: Fix warning to fix the compilation. Without that fix we have: src/drivers/elog/elog.c: In function 'elog_is_header_valid': src/drivers/elog/elog.c:213:3: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format] Change-Id: I71b80a94c03a04eedb688ae107d92c05a878315e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/drivers/elog/elog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 1a794d9..71e908b 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -210,7 +210,7 @@ static int elog_is_header_valid(struct elog_header *header) return 0; } if (header->header_size != sizeof(*header)) { - printk(BIOS_ERR, "ELOG: header size mismatch %u != %u\n", + printk(BIOS_ERR, "ELOG: header size mismatch %u != %zu\n", header->header_size, sizeof(*header)); return 0; }

1 0

Patch set updated for coreboot: 64a07ee libpayload: Add strerror
by Stefan Tauner 27 Jun '13

27 Jun '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3537 -gerrit commit 64a07ee4acd0090377ed1037d05ebef05fe822bd Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Thu Jun 27 17:06:27 2013 +0200 libpayload: Add strerror Change-Id: I33d45ad7d09473b8c6f5b7ee5fbadc0d184f9dcd Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- payloads/libpayload/include/string.h | 5 +++-- payloads/libpayload/libc/string.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/include/string.h b/payloads/libpayload/include/string.h index 9e4f791..952261f 100644 --- a/payloads/libpayload/include/string.h +++ b/payloads/libpayload/include/string.h @@ -63,8 +63,9 @@ char *strstr(const char *h, const char *n); char *strsep(char **stringp, const char *delim); size_t strspn(const char *s, const char *a); size_t strcspn(const char *s, const char *a); -char* strtok(char *str, const char *delim); -char* strtok_r(char *str, const char *delim, char **ptr); +char *strtok(char *str, const char *delim); +char *strtok_r(char *str, const char *delim, char **ptr); +char *strerror(int errnum); /** @} */ /** diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index 6151164..71dd1a6 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -639,3 +639,17 @@ void perror(const char *s) { printf("%s: %d\n", s?s:"(none)", errno); } + +/** + * Get a message string describing the given error number. + * + * @param errnum The error number to be interpreted + * @return A pointer to a string describing the given error number + */ +char *strerror(int errnum) +{ + /* Reserve enough space for the string below + INT64_MIN in decimal + \0 */ + static char errstr[35]; + snprintf(errstr, sizeof(errstr), "Unknown error %d", errnum); + return errstr; +}

1 0

Patch merged into coreboot/master: cb47d89 libpayload: Add more integer limits
by gerrit＠coreboot.org 27 Jun '13

27 Jun '13

the following patch was just integrated into master: commit cb47d89bbba78e370a420d4f15b631c9ce7532c8 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Tue Jun 25 18:48:31 2013 +0200 libpayload: Add more integer limits Change-Id: If0963237806804a2a9d7f622c33013321379a04d Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/3536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> See http://review.coreboot.org/3536 for details. -gerrit

1 0

Patch merged into coreboot/master: 3509ad3 libpayload: Fix whitespace errors
by gerrit＠coreboot.org 27 Jun '13

27 Jun '13

the following patch was just integrated into master: commit 3509ad366dceb346025d6882a59a7b6a4a357ee9 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Tue Jun 25 19:25:46 2013 +0200 libpayload: Fix whitespace errors Change-Id: Ibc36988745cbc7ede2a00da376b5dd295014ffb1 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-on: http://review.coreboot.org/3535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> See http://review.coreboot.org/3535 for details. -gerrit

1 0

Patch set updated for coreboot: 6c13b74 Add directive __SIMPLE_DEVICE__
by Kyösti Mälkki 27 Jun '13

27 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3555 -gerrit commit 6c13b74d2a899e7054f4a19c9ec9ab402dd83fdb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 25 23:17:43 2013 +0300 Add directive __SIMPLE_DEVICE__ The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/include/arch/rules.h | 35 +++++++++++++++++++++++++++ src/arch/x86/include/arch/cpu.h | 9 ++++--- src/arch/x86/include/arch/io.h | 6 ++++- src/arch/x86/include/arch/rules.h | 39 ++++++++++++++++++++++++++++++ src/include/device/device.h | 21 ++++++++++------ src/include/device/pci.h | 8 +++--- src/include/device/pnp.h | 6 +++-- src/lib/uart8250mem.c | 4 +-- src/northbridge/intel/gm45/ram_calc.c | 6 ++--- src/northbridge/intel/sch/port_access.c | 6 ++--- src/southbridge/amd/agesa/hudson/reset.c | 6 ++--- src/southbridge/amd/cimx/sb700/reset.c | 6 ++--- src/southbridge/amd/cimx/sb800/reset.c | 6 ++--- src/southbridge/amd/cimx/sb900/early.c | 6 ++--- src/southbridge/amd/cimx/sb900/reset.c | 6 ++--- src/southbridge/amd/sb600/reset.c | 6 ++--- src/southbridge/amd/sb700/reset.c | 3 ++- src/southbridge/amd/sb800/reset.c | 6 ++--- src/southbridge/intel/i82801gx/usb_debug.c | 6 ++--- 19 files changed, 141 insertions(+), 50 deletions(-) diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h new file mode 100644 index 0000000..222dfa1 --- /dev/null +++ b/src/arch/armv7/include/arch/rules.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__SIMPLE_DEVICE__) || defined(__PRE_RAM__) +#undef __SIMPLE_DEVICE__ +#define __SIMPLE_DEVICE__ +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 7363132..04398db 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -2,6 +2,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <arch/rules.h> /* * EFLAGS bits @@ -141,12 +142,14 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> +#include <arch/io.h> int cpu_phys_address_size(void); int cpu_have_cpuid(void); +#ifndef __SIMPLE_DEVICE__ +#include <device/device.h> + struct cpu_device_id { unsigned vendor; unsigned device; @@ -188,8 +191,6 @@ static inline unsigned long cpu_index(void) ci = cpu_info(); return ci->index; } -#else -#include <arch/io.h> #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index de4e1e3..b73137b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H #include <stdint.h> +#include <arch/rules.h> /* * This file contains the definitions for the x86 IO instructions @@ -188,6 +189,9 @@ static inline int log2f(int value) return r; } +#endif + +#ifdef __SIMPLE_DEVICE__ #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ @@ -339,7 +343,7 @@ void pnp_set_drq(simple_pnpdev_t dev, unsigned index, unsigned drq) pnp_write_config(dev, index, drq & 0xff); } -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ #endif diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h new file mode 100644 index 0000000..c569f8a --- /dev/null +++ b/src/arch/x86/include/arch/rules.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__SIMPLE_DEVICE__) || defined(__PRE_RAM__) || defined(__SMM__) +#undef __SIMPLE_DEVICE__ +#define __SIMPLE_DEVICE__ +#endif + +#if defined(__PRE_RAM__) || defined(__SMM__) +#include <arch/io.h> +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index bcfe03b..2413b30 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -1,14 +1,17 @@ #ifndef DEVICE_H #define DEVICE_H + #ifndef __SMM__ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/resource.h> #include <device/path.h> struct device; -#ifndef __PRE_RAM__ + +#ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; typedef unsigned int simple_pcidev_t; typedef unsigned int simple_pnpdev_t; @@ -47,7 +50,7 @@ struct device_operations { const struct pci_bus_operations *ops_pci_bus; const struct pnp_mode_ops *ops_pnp_mode; }; -#endif +#endif /* ! __SIMPLE_DEVICE__ */ struct bus { @@ -118,9 +121,10 @@ struct device { * static.c file and is generated by the config tool at compile time. */ extern ROMSTAGE_CONST struct device dev_root; -#ifndef __PRE_RAM__ -extern struct device *all_devices; /* list of all devices */ +#ifndef __SIMPLE_DEVICE__ + +extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; extern struct bus *free_links; @@ -224,13 +228,16 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); -#else + +#else /* vv __SIMPLE_DEVICE__ vv */ + ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); + #endif -#else /* __SMM__ */ -#include <arch/io.h> + #endif /* __SMM__ */ + #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index c4978ef..9c28c7b 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -17,10 +17,12 @@ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/pci_def.h> -#include <device/resource.h> #include <device/device.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) + +#ifndef __SIMPLE_DEVICE__ +#include <device/resource.h> #include <device/pci_ops.h> #include <device/pci_rom.h> @@ -107,5 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) return bops; } -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* PCI_H */ diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 434f0a4..a229edb 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,10 +2,12 @@ #define DEVICE_PNP_H #include <stdint.h> +#include <arch/rules.h> #include <device/device.h> #include <device/pnp_def.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) +#ifndef __SIMPLE_DEVICE__ + /* Primitive PNP resource manipulation */ void pnp_write_config(device_t dev, u8 reg, u8 value); u8 pnp_read_config(device_t dev, u8 reg); @@ -59,5 +61,5 @@ struct pnp_mode_ops { void pnp_enter_conf_mode(device_t dev); void pnp_exit_conf_mode(device_t dev); -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* DEVICE_PNP_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 8224843..3d1bd10 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -24,7 +24,7 @@ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif -#if !defined(__SMM__) && !defined(__PRE_RAM__) +#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #endif #include <delay.h> @@ -129,7 +129,7 @@ u32 uart_mem_init(void) /* Now find the UART base address and calculate the divisor */ #if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) device_t dev = dev_find_device(0x1415, 0xc158, NULL); if (!dev) dev = dev_find_device(0x1415, 0xc11b, NULL); diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 9e54c10..4590544 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index c73f709..a33a564 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index d6036dd..4879904 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0936516..1ef408b 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index ef4115e..3c993d1 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -18,7 +18,8 @@ */ #ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ +// Use simple device model for this file even in ramstage #endif #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c index bdea889..8b29b98 100644 --- a/src/southbridge/intel/i82801gx/usb_debug.c +++ b/src/southbridge/intel/i82801gx/usb_debug.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <console/console.h>

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coreboot-gerrit June 2013