Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3555
-gerrit
commit b7200995a6677255d6dbc94f65e87a3b4cc0b184
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Jun 25 23:17:43 2013 +0300
Add directive __SIMPLE_DEVICE__
The tests for __PRE_RAM__ or __SMM__ were repeatedly used
for detection if dev->ops in the devicetree are not available
and simple device model functions need be used.
If a source file build for ramstage had __PRE_RAM__ inserted
at the beginning, the struct device would no longer match the
allocation the object had taken. This problem is fixed by
replacing such cases with explicit __SIMPLE_DEVICE__.
Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/arch/x86/include/arch/cpu.h | 9 ++++---
src/arch/x86/include/arch/io.h | 6 ++++-
src/arch/x86/include/arch/rules.h | 39 ++++++++++++++++++++++++++++++
src/include/device/device.h | 21 ++++++++++------
src/include/device/pci.h | 8 +++---
src/include/device/pnp.h | 6 +++--
src/lib/uart8250mem.c | 4 +--
src/northbridge/intel/gm45/ram_calc.c | 6 ++---
src/northbridge/intel/sch/port_access.c | 6 ++---
src/southbridge/amd/agesa/hudson/reset.c | 6 ++---
src/southbridge/amd/cimx/sb700/reset.c | 6 ++---
src/southbridge/amd/cimx/sb800/reset.c | 6 ++---
src/southbridge/amd/cimx/sb900/early.c | 6 ++---
src/southbridge/amd/cimx/sb900/reset.c | 6 ++---
src/southbridge/amd/sb600/reset.c | 6 ++---
src/southbridge/amd/sb700/reset.c | 3 ++-
src/southbridge/amd/sb800/reset.c | 6 ++---
src/southbridge/intel/i82801gx/usb_debug.c | 6 ++---
18 files changed, 106 insertions(+), 50 deletions(-)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 7363132..04398db 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -2,6 +2,7 @@
#define ARCH_CPU_H
#include <stdint.h>
+#include <arch/rules.h>
/*
* EFLAGS bits
@@ -141,12 +142,14 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_ANY 0xfe
#define X86_VENDOR_UNKNOWN 0xff
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-#include <device/device.h>
+#include <arch/io.h>
int cpu_phys_address_size(void);
int cpu_have_cpuid(void);
+#ifndef __SIMPLE_DEVICE__
+#include <device/device.h>
+
struct cpu_device_id {
unsigned vendor;
unsigned device;
@@ -188,8 +191,6 @@ static inline unsigned long cpu_index(void)
ci = cpu_info();
return ci->index;
}
-#else
-#include <arch/io.h>
#endif
#ifndef __ROMCC__ // romcc is segfaulting in some cases
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index de4e1e3..b73137b 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -2,6 +2,7 @@
#define _ASM_IO_H
#include <stdint.h>
+#include <arch/rules.h>
/*
* This file contains the definitions for the x86 IO instructions
@@ -188,6 +189,9 @@ static inline int log2f(int value)
return r;
}
+#endif
+
+#ifdef __SIMPLE_DEVICE__
#define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \
(((SEGBUS) & 0xFFF) << 20) | \
@@ -339,7 +343,7 @@ void pnp_set_drq(simple_pnpdev_t dev, unsigned index, unsigned drq)
pnp_write_config(dev, index, drq & 0xff);
}
-#endif /* __PRE_RAM__ */
+#endif /* __SIMPLE_DEVICE__ */
#endif
diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h
new file mode 100644
index 0000000..c569f8a
--- /dev/null
+++ b/src/arch/x86/include/arch/rules.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _ARCH_RULES_H
+#define _ARCH_RULES_H
+
+/* For romstage and ramstage always build with simple device model, ie.
+ * PCI, PNP and CPU functions operate without use of devicetree.
+ *
+ * For ramstage individual source file may define __SIMPLE_DEVICE__
+ * before including any header files to force that particular source
+ * be built with simple device model.
+ */
+
+#if defined(__SIMPLE_DEVICE__) || defined(__PRE_RAM__) || defined(__SMM__)
+#undef __SIMPLE_DEVICE__
+#define __SIMPLE_DEVICE__
+#endif
+
+#if defined(__PRE_RAM__) || defined(__SMM__)
+#include <arch/io.h>
+#endif
+
+#endif /* _ARCH_RULES_H */
diff --git a/src/include/device/device.h b/src/include/device/device.h
index bcfe03b..2413b30 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -1,14 +1,17 @@
#ifndef DEVICE_H
#define DEVICE_H
+
#ifndef __SMM__
#include <stdint.h>
#include <stddef.h>
+#include <arch/rules.h>
#include <device/resource.h>
#include <device/path.h>
struct device;
-#ifndef __PRE_RAM__
+
+#ifndef __SIMPLE_DEVICE__
typedef struct device * device_t;
typedef unsigned int simple_pcidev_t;
typedef unsigned int simple_pnpdev_t;
@@ -47,7 +50,7 @@ struct device_operations {
const struct pci_bus_operations *ops_pci_bus;
const struct pnp_mode_ops *ops_pnp_mode;
};
-#endif
+#endif /* ! __SIMPLE_DEVICE__ */
struct bus {
@@ -118,9 +121,10 @@ struct device {
* static.c file and is generated by the config tool at compile time.
*/
extern ROMSTAGE_CONST struct device dev_root;
-#ifndef __PRE_RAM__
-extern struct device *all_devices; /* list of all devices */
+#ifndef __SIMPLE_DEVICE__
+
+extern struct device *all_devices; /* list of all devices */
extern struct resource *free_resources;
extern struct bus *free_links;
@@ -224,13 +228,16 @@ void fixed_mem_resource(device_t dev, unsigned long index,
void tolm_test(void *gp, struct device *dev, struct resource *new);
u32 find_pci_tolm(struct bus *bus);
-#else
+
+#else /* vv __SIMPLE_DEVICE__ vv */
+
ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus,
unsigned int devfn);
ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus,
unsigned int addr);
+
#endif
-#else /* __SMM__ */
-#include <arch/io.h>
+
#endif /* __SMM__ */
+
#endif /* DEVICE_H */
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index c4978ef..9c28c7b 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -17,10 +17,12 @@
#include <stdint.h>
#include <stddef.h>
+#include <arch/rules.h>
#include <device/pci_def.h>
-#include <device/resource.h>
#include <device/device.h>
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
+
+#ifndef __SIMPLE_DEVICE__
+#include <device/resource.h>
#include <device/pci_ops.h>
#include <device/pci_rom.h>
@@ -107,5 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus)
return bops;
}
-#endif
+#endif /* ! __SIMPLE_DEVICE__ */
#endif /* PCI_H */
diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h
index 434f0a4..a229edb 100644
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@@ -2,10 +2,12 @@
#define DEVICE_PNP_H
#include <stdint.h>
+#include <arch/rules.h>
#include <device/device.h>
#include <device/pnp_def.h>
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
+#ifndef __SIMPLE_DEVICE__
+
/* Primitive PNP resource manipulation */
void pnp_write_config(device_t dev, u8 reg, u8 value);
u8 pnp_read_config(device_t dev, u8 reg);
@@ -59,5 +61,5 @@ struct pnp_mode_ops {
void pnp_enter_conf_mode(device_t dev);
void pnp_exit_conf_mode(device_t dev);
-#endif
+#endif /* ! __SIMPLE_DEVICE__ */
#endif /* DEVICE_PNP_H */
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index 8224843..3d1bd10 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -24,7 +24,7 @@
#if CONFIG_USE_OPTION_TABLE
#include "option_table.h"
#endif
-#if !defined(__SMM__) && !defined(__PRE_RAM__)
+#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#endif
#include <delay.h>
@@ -129,7 +129,7 @@ u32 uart_mem_init(void)
/* Now find the UART base address and calculate the divisor */
#if CONFIG_DRIVERS_OXFORD_OXPCIE
-#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__)
+#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__)
device_t dev = dev_find_device(0x1415, 0xc158, NULL);
if (!dev)
dev = dev_find_device(0x1415, 0xc11b, NULL);
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 9e54c10..4590544 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -19,9 +19,9 @@
* MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_def.h>
diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c
index c73f709..a33a564 100644
--- a/src/northbridge/intel/sch/port_access.c
+++ b/src/northbridge/intel/sch/port_access.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <stdint.h>
#include <arch/io.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 315a065..79fd79e 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index 7a96aa4..36f96d3 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index 7a96aa4..36f96d3 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index d6036dd..4879904 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <stdint.h>
#include <device/pci_ids.h>
#include <arch/io.h>
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index 7a96aa4..36f96d3 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c
index 0936516..1ef408b 100644
--- a/src/southbridge/amd/sb600/reset.c
+++ b/src/southbridge/amd/sb600/reset.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index ef4115e..3c993d1 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -18,7 +18,8 @@
*/
#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+// Use simple device model for this file even in ramstage
#endif
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c
index 315a065..79fd79e 100644
--- a/src/southbridge/amd/sb800/reset.c
+++ b/src/southbridge/amd/sb800/reset.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index bdea889..8b29b98 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -17,9 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-#define __PRE_RAM__ // Use simple device model for this file even in ramstage
-#endif
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
#include <stdint.h>
#include <arch/io.h>
#include <console/console.h>
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502
-gerrit
commit 9a5164cef237c27c7b402041c738834af66872a9
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Jun 19 23:05:00 2013 +0300
Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.
Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/arch/x86/include/arch/io.h | 2 +
src/arch/x86/include/arch/pci_mmio_cfg.h | 96 +++++++++++++++++++++++++
src/mainboard/google/stout/mainboard_smi.c | 1 -
src/northbridge/intel/i945/early_init.c | 1 -
src/northbridge/intel/i945/pcie_config.c | 68 ------------------
src/northbridge/intel/sandybridge/early_init.c | 1 -
src/northbridge/intel/sandybridge/finalize.c | 1 -
src/northbridge/intel/sandybridge/pcie_config.c | 89 -----------------------
src/northbridge/intel/sch/pcie_config.c | 66 -----------------
src/southbridge/intel/bd82x6x/finalize.c | 1 -
src/southbridge/intel/bd82x6x/me.c | 2 +-
src/southbridge/intel/bd82x6x/me_8.x.c | 2 +-
src/southbridge/intel/bd82x6x/smihandler.c | 2 +-
src/southbridge/intel/bd82x6x/spi.c | 2 +-
src/southbridge/intel/i82801dx/smihandler.c | 6 --
src/southbridge/intel/i82801gx/smihandler.c | 2 +-
src/southbridge/intel/sch/smihandler.c | 7 --
17 files changed, 103 insertions(+), 246 deletions(-)
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 29c8339..49499b9 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -395,6 +395,8 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de
#endif
}
+#include <arch/pci_mmio_cfg.h>
+
static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value)
{
pci_write_config8(dev, where, pci_read_config8(dev, where) | value);
diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h
new file mode 100644
index 0000000..7fb322d
--- /dev/null
+++ b/src/arch/x86/include/arch/pci_mmio_cfg.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _PCI_MMIO_CFG_H
+#define _PCI_MMIO_CFG_H
+
+#if CONFIG_MMCONF_SUPPORT
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
+
+static inline __attribute__ ((always_inline))
+u8 pcie_read_config8(device_t dev, unsigned int where)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ return read8(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u16 pcie_read_config16(device_t dev, unsigned int where)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ return read16(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u32 pcie_read_config32(device_t dev, unsigned int where)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ return read32(addr);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ write8(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ write16(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+{
+ unsigned long addr;
+ addr = DEFAULT_PCIEXBAR | dev | where;
+ write32(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
+{
+ u8 value = pcie_read_config8(dev, where);
+ pcie_write_config8(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
+{
+ u16 value = pcie_read_config16(dev, where);
+ pcie_write_config16(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
+{
+ u32 value = pcie_read_config32(dev, where);
+ pcie_write_config32(dev, where, value | ormask);
+}
+
+#endif /* CONFIG_MMCONF_SUPPORT */
+#endif /* _PCI_MMIO_CFG_H */
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index 7981046..8b37da3 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -24,7 +24,6 @@
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/bd82x6x/me.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
#include <cpu/intel/model_206ax/model_206ax.h>
/* Include romstage serial for SIO helper functions */
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d91930f..435d64d 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,7 +23,6 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include "i945.h"
-#include "pcie_config.c"
int i945_silicon_revision(void)
{
diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c
deleted file mode 100644
index 0310d67..0000000
--- a/src/northbridge/intel/i945/pcie_config.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "i945.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write32(addr, value);
-}
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index c2d4909..4f2e038 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -25,7 +25,6 @@
#include <device/pci_def.h>
#include <elog.h>
#include "sandybridge.h"
-#include "pcie_config.c"
static void sandybridge_setup_bars(void)
{
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
index 0fa8d1a..9b41cfa 100644
--- a/src/northbridge/intel/sandybridge/finalize.c
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -20,7 +20,6 @@
#include <arch/io.h>
#include <stdlib.h>
-#include "pcie_config.c"
#include "sandybridge.h"
#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c
deleted file mode 100644
index 0677d76..0000000
--- a/src/northbridge/intel/sandybridge/pcie_config.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include "sandybridge.h"
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write32(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
-{
- u8 value = pcie_read_config8(dev, where);
- pcie_write_config8(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
-{
- u16 value = pcie_read_config16(dev, where);
- pcie_write_config16(dev, where, value | ormask);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
-{
- u32 value = pcie_read_config32(dev, where);
- pcie_write_config32(dev, where, value | ormask);
-}
diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c
deleted file mode 100644
index ad7d746..0000000
--- a/src/northbridge/intel/sch/pcie_config.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-static inline __attribute__ ((always_inline))
-u8 pcie_read_config8(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read8(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u16 pcie_read_config16(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read16(addr);
-}
-
-static inline __attribute__ ((always_inline))
-u32 pcie_read_config32(device_t dev, unsigned int where)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- return read32(addr);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config8(device_t dev, unsigned int where, u8 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write8(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config16(device_t dev, unsigned int where, u16 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write16(addr, value);
-}
-
-static inline __attribute__ ((always_inline))
-void pcie_write_config32(device_t dev, unsigned int where, u32 value)
-{
- unsigned long addr;
- addr = DEFAULT_PCIEXBAR | dev | where;
- write32(addr, value);
-}
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index bcc2f3d..b1d2d34 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,7 +20,6 @@
#include <arch/io.h>
#include <console/post_codes.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
#include "pch.h"
#include <spi-generic.h>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 7fdf926..626e61a 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -38,7 +38,7 @@
#include <elog.h>
#ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
#else
# include <device/device.h>
# include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f79adf5..72175d8 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -38,7 +38,7 @@
#include <elog.h>
#ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
#else
# include <device/device.h>
# include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 5913115..9588703 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -37,7 +37,7 @@
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 09169b1..c720afe 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -34,7 +34,7 @@
#define min(a, b) ((a)<(b)?(a):(b))
#ifdef __SMM__
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pcie_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 5470890..9b0c235 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n");
}
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-// #include "../../../northbridge/intel/i945/pcie_config.c"
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 2e29acd..e5bdfd8 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts)
* 1. the chipset can do it
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
-#include "../../../northbridge/intel/i945/pcie_config.c"
+#include <arch/pci_mmio_cfg.h>
int southbridge_io_trap_handler(int smif)
{
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 2ccbc7f..5074138 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts)
}
#endif
-
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-//#include "../../../northbridge/intel/i945/pcie_config.c"
-
int southbridge_io_trap_handler(int smif)
{
//global_nvs_t *gnvs = (global_nvs_t *)0xc00;
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3540
-gerrit
commit fcd472304e24e94613ccc02864c29fc1c0c7dd00
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Tue Jun 25 14:27:16 2013 -0600
amd/cimx/rd890/amd.h: Eliminate redefinition of NULL
This change replaces a redefinition of NULL with the standard
definition from <stddef.h> to eliminate a compiler redefinition
warning.
Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/northbridge/amd/cimx/rd890/amd.h | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h
index 1ceff80..e7a9ca9 100644
--- a/src/northbridge/amd/cimx/rd890/amd.h
+++ b/src/northbridge/amd/cimx/rd890/amd.h
@@ -32,10 +32,7 @@
// AGESA Types and Definitions
//
//
-#ifndef NULL
- #define NULL 0
-#endif
-
+#include <stddef.h>
#define LAST_ENTRY 0xFFFFFFFF
#define IOCF8 0xCF8
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3541
-gerrit
commit 9a59d74a7d8cc210f11f6a710f1acd26a501e849
Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
Date: Tue Jun 25 14:29:08 2013 -0600
amd/cimx/sb700/late.c: Add type cast to (UINT8)
This change inserts a type cast to eliminate a compiler warning.
Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5
Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com>
---
src/southbridge/amd/cimx/sb700/late.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index ede9fb3..b259a7b 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -254,7 +254,7 @@ static void sb700_enable(device_t dev)
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
- setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
+ setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS));
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(ioapic_base, 0);