coreboot-gerrit June 2013

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Patch set updated for coreboot: 6eaa399 AMD Dinar: Eliminate warnings (initializers/prototypes/unused var)
by Bruce Griffith 27 Jun '13

27 Jun '13

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3545 -gerrit commit 6eaa399c554fa52a4f6ce20f6a4151fde02e284c Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:02:41 2013 -0600 AMD Dinar: Eliminate warnings (initializers/prototypes/unused var) Fix a bunch of compiler-generated warning messages. These fixes are mainly braces for grouping initializers. These changes are not intended to change any code functionality. There are two changes where function prototypes are added, and two cases where unused variables are eliminated. Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/dinar/BiosCallOuts.c | 1 - src/mainboard/amd/dinar/agesawrapper.c | 19 +++-- src/mainboard/amd/dinar/agesawrapper.h | 4 +- src/mainboard/amd/dinar/buildOpts.c | 132 +++++++++++++++++++++++++-------- src/mainboard/amd/dinar/romstage.c | 2 + 5 files changed, 117 insertions(+), 41 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 4fb3c66..c9888b9 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -584,7 +584,6 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT32 GpioMmioAddr; UINT8 Data8; UINT16 Data16; - UINT8 TempData8; FcnData = Data; MemData = ConfigPtr; diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 4017adc..179822b 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -75,6 +75,8 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); +extern VOID OemCustomizeInitPost(IN AMD_POST_PARAMS *InitPost); /*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ /* @@ -88,6 +90,7 @@ Bits Buses Bits Buses 3h 8 8h 256 4h 16 Fh-9h Reserved */ +STATIC UINT8 GetEndBusNum ( VOID @@ -283,9 +286,12 @@ agesawrapper_amdinitreset ( ) { AGESA_STATUS status; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; +#endif +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -307,12 +313,13 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); -#endif - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); +#else + status = AGESA_SUCCESS; +#endif + return (UINT32)status; } @@ -432,8 +439,6 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; LibAmdMemFill (&AmdParamStruct, 0, @@ -574,11 +579,11 @@ agesawrapper_amdlaterunaptask ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AP_EXE_PARAMS AmdLateParams; LibAmdMemFill (&AmdLateParams, 0, - sizeof (AMD_LATE_PARAMS), + sizeof (AP_EXE_PARAMS), &(AmdLateParams.StdHeader)); AmdLateParams.StdHeader.AltImageBasePtr = 0; diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index 0b4a701..62fd277 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -126,11 +126,9 @@ UINT32 agesawrapper_amdinitenv (void); UINT32 agesawrapper_amdinitlate (void); UINT32 agesawrapper_amdinitpost (void); UINT32 agesawrapper_amdinitmid (void); -void sb_After_Pci_Init (void); -void sb_Mid_Post_Init (void); -void sb_Late_Post (void); UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Data, VOID *ConfigPtr); #endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 1d57d7a..41f5415 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -36,13 +36,39 @@ #include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - +//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE +/* AGESA will check the OEM configuration during preprocessing stage, + * coreboot enable -Wundef option, so we should make sure we have all contanstand defined + */ +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE */ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode /* Select the cpu family. */ /* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE #define INSTALL_S1G4_SOCKET_SUPPORT FALSE @@ -211,17 +237,41 @@ */ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - 0, 0, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + { //BUID Swap List + { //BUID Swaps + /* Each Non-coherent chain may have a list of device swaps, + * Each item specify a device will be swap from its current id to a new one + */ + /* FromID 0x00 is the chain with the southbridge */ + /* 'Move' device zero to device zero, All others are non applicable */ + {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + }, + + { //The ordered final BUIDs + /* Specify the final BUID to be zero, All others are non applicable */ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + } + } + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } }; #define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList @@ -236,20 +286,32 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, - HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_TERMINAL + { + /* On the reference platform, these settings apply to all coherent links */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + }, + + { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } }; #define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList // A performance-per-watt optimization. CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, - HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, - HT_LIST_TERMINAL, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF }, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF }, + { HT_LIST_TERMINAL } }; // uncomment the line below to make Perf-per-watt enabled by default. @@ -258,8 +320,18 @@ CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_TERMINAL + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, //Actually IO hub only support 2600M MAX + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } }; #define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList @@ -283,9 +355,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = { // Socket, Link, SecBus, SubBus - 0, 2, 0x00, 0xBF, // RD890 of Dinar - 1, 0, 0xC0, 0xFF, // HTX - HT_LIST_TERMINAL + { 0, 2, 0x00, 0xBF }, // RD890 of Dinar + { 1, 0, 0xC0, 0xFF }, // HTX + { (HT_LIST_TERMINAL) } }; #define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers @@ -295,7 +367,7 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, - 0xFF + { (0xFF) } }; #define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList @@ -314,9 +386,9 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = */ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, - HT_LIST_TERMINAL + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, 0 }, + { (HT_LIST_TERMINAL) } }; #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 77f73e2..e52b5f7 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -41,6 +41,8 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); u32 agesawrapper_amdinitearly (void);

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New patch to review for coreboot: b720099 Add directive __SIMPLE_DEVICE__
by Kyösti Mälkki 27 Jun '13

27 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3555 -gerrit commit b7200995a6677255d6dbc94f65e87a3b4cc0b184 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jun 25 23:17:43 2013 +0300 Add directive __SIMPLE_DEVICE__ The tests for __PRE_RAM__ or __SMM__ were repeatedly used for detection if dev->ops in the devicetree are not available and simple device model functions need be used. If a source file build for ramstage had __PRE_RAM__ inserted at the beginning, the struct device would no longer match the allocation the object had taken. This problem is fixed by replacing such cases with explicit __SIMPLE_DEVICE__. Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 9 ++++--- src/arch/x86/include/arch/io.h | 6 ++++- src/arch/x86/include/arch/rules.h | 39 ++++++++++++++++++++++++++++++ src/include/device/device.h | 21 ++++++++++------ src/include/device/pci.h | 8 +++--- src/include/device/pnp.h | 6 +++-- src/lib/uart8250mem.c | 4 +-- src/northbridge/intel/gm45/ram_calc.c | 6 ++--- src/northbridge/intel/sch/port_access.c | 6 ++--- src/southbridge/amd/agesa/hudson/reset.c | 6 ++--- src/southbridge/amd/cimx/sb700/reset.c | 6 ++--- src/southbridge/amd/cimx/sb800/reset.c | 6 ++--- src/southbridge/amd/cimx/sb900/early.c | 6 ++--- src/southbridge/amd/cimx/sb900/reset.c | 6 ++--- src/southbridge/amd/sb600/reset.c | 6 ++--- src/southbridge/amd/sb700/reset.c | 3 ++- src/southbridge/amd/sb800/reset.c | 6 ++--- src/southbridge/intel/i82801gx/usb_debug.c | 6 ++--- 18 files changed, 106 insertions(+), 50 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 7363132..04398db 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -2,6 +2,7 @@ #define ARCH_CPU_H #include <stdint.h> +#include <arch/rules.h> /* * EFLAGS bits @@ -141,12 +142,14 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> +#include <arch/io.h> int cpu_phys_address_size(void); int cpu_have_cpuid(void); +#ifndef __SIMPLE_DEVICE__ +#include <device/device.h> + struct cpu_device_id { unsigned vendor; unsigned device; @@ -188,8 +191,6 @@ static inline unsigned long cpu_index(void) ci = cpu_info(); return ci->index; } -#else -#include <arch/io.h> #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index de4e1e3..b73137b 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -2,6 +2,7 @@ #define _ASM_IO_H #include <stdint.h> +#include <arch/rules.h> /* * This file contains the definitions for the x86 IO instructions @@ -188,6 +189,9 @@ static inline int log2f(int value) return r; } +#endif + +#ifdef __SIMPLE_DEVICE__ #define PCI_ADDR(SEGBUS, DEV, FN, WHERE) ( \ (((SEGBUS) & 0xFFF) << 20) | \ @@ -339,7 +343,7 @@ void pnp_set_drq(simple_pnpdev_t dev, unsigned index, unsigned drq) pnp_write_config(dev, index, drq & 0xff); } -#endif /* __PRE_RAM__ */ +#endif /* __SIMPLE_DEVICE__ */ #endif diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h new file mode 100644 index 0000000..c569f8a --- /dev/null +++ b/src/arch/x86/include/arch/rules.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ARCH_RULES_H +#define _ARCH_RULES_H + +/* For romstage and ramstage always build with simple device model, ie. + * PCI, PNP and CPU functions operate without use of devicetree. + * + * For ramstage individual source file may define __SIMPLE_DEVICE__ + * before including any header files to force that particular source + * be built with simple device model. + */ + +#if defined(__SIMPLE_DEVICE__) || defined(__PRE_RAM__) || defined(__SMM__) +#undef __SIMPLE_DEVICE__ +#define __SIMPLE_DEVICE__ +#endif + +#if defined(__PRE_RAM__) || defined(__SMM__) +#include <arch/io.h> +#endif + +#endif /* _ARCH_RULES_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index bcfe03b..2413b30 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -1,14 +1,17 @@ #ifndef DEVICE_H #define DEVICE_H + #ifndef __SMM__ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/resource.h> #include <device/path.h> struct device; -#ifndef __PRE_RAM__ + +#ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; typedef unsigned int simple_pcidev_t; typedef unsigned int simple_pnpdev_t; @@ -47,7 +50,7 @@ struct device_operations { const struct pci_bus_operations *ops_pci_bus; const struct pnp_mode_ops *ops_pnp_mode; }; -#endif +#endif /* ! __SIMPLE_DEVICE__ */ struct bus { @@ -118,9 +121,10 @@ struct device { * static.c file and is generated by the config tool at compile time. */ extern ROMSTAGE_CONST struct device dev_root; -#ifndef __PRE_RAM__ -extern struct device *all_devices; /* list of all devices */ +#ifndef __SIMPLE_DEVICE__ + +extern struct device *all_devices; /* list of all devices */ extern struct resource *free_resources; extern struct bus *free_links; @@ -224,13 +228,16 @@ void fixed_mem_resource(device_t dev, unsigned long index, void tolm_test(void *gp, struct device *dev, struct resource *new); u32 find_pci_tolm(struct bus *bus); -#else + +#else /* vv __SIMPLE_DEVICE__ vv */ + ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus, unsigned int devfn); ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus, unsigned int addr); + #endif -#else /* __SMM__ */ -#include <arch/io.h> + #endif /* __SMM__ */ + #endif /* DEVICE_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index c4978ef..9c28c7b 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -17,10 +17,12 @@ #include <stdint.h> #include <stddef.h> +#include <arch/rules.h> #include <device/pci_def.h> -#include <device/resource.h> #include <device/device.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) + +#ifndef __SIMPLE_DEVICE__ +#include <device/resource.h> #include <device/pci_ops.h> #include <device/pci_rom.h> @@ -107,5 +109,5 @@ static inline const struct pci_bus_operations *ops_pci_bus(struct bus *bus) return bops; } -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* PCI_H */ diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 434f0a4..a229edb 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -2,10 +2,12 @@ #define DEVICE_PNP_H #include <stdint.h> +#include <arch/rules.h> #include <device/device.h> #include <device/pnp_def.h> -#if !defined(__PRE_RAM__) && !defined(__SMM__) +#ifndef __SIMPLE_DEVICE__ + /* Primitive PNP resource manipulation */ void pnp_write_config(device_t dev, u8 reg, u8 value); u8 pnp_read_config(device_t dev, u8 reg); @@ -59,5 +61,5 @@ struct pnp_mode_ops { void pnp_enter_conf_mode(device_t dev); void pnp_exit_conf_mode(device_t dev); -#endif +#endif /* ! __SIMPLE_DEVICE__ */ #endif /* DEVICE_PNP_H */ diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c index 8224843..3d1bd10 100644 --- a/src/lib/uart8250mem.c +++ b/src/lib/uart8250mem.c @@ -24,7 +24,7 @@ #if CONFIG_USE_OPTION_TABLE #include "option_table.h" #endif -#if !defined(__SMM__) && !defined(__PRE_RAM__) +#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #endif #include <delay.h> @@ -129,7 +129,7 @@ u32 uart_mem_init(void) /* Now find the UART base address and calculate the divisor */ #if CONFIG_DRIVERS_OXFORD_OXPCIE -#if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if defined(MORE_TESTING) && !defined(__SIMPLE_DEVICE__) device_t dev = dev_find_device(0x1415, 0xc158, NULL); if (!dev) dev = dev_find_device(0x1415, 0xc11b, NULL); diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 9e54c10..4590544 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sch/port_access.c b/src/northbridge/intel/sch/port_access.c index c73f709..a33a564 100644 --- a/src/northbridge/intel/sch/port_access.c +++ b/src/northbridge/intel/sch/port_access.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <device/pci_def.h> diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb700/reset.c +++ b/src/southbridge/amd/cimx/sb700/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ b/src/southbridge/amd/cimx/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index d6036dd..4879904 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <device/pci_ids.h> #include <arch/io.h> diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c index 7a96aa4..36f96d3 100644 --- a/src/southbridge/amd/cimx/sb900/reset.c +++ b/src/southbridge/amd/cimx/sb900/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb600/reset.c b/src/southbridge/amd/sb600/reset.c index 0936516..1ef408b 100644 --- a/src/southbridge/amd/sb600/reset.c +++ b/src/southbridge/amd/sb600/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index ef4115e..3c993d1 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -18,7 +18,8 @@ */ #ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ +// Use simple device model for this file even in ramstage #endif #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/amd/sb800/reset.c b/src/southbridge/amd/sb800/reset.c index 315a065..79fd79e 100644 --- a/src/southbridge/amd/sb800/reset.c +++ b/src/southbridge/amd/sb800/reset.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <reset.h> diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c index bdea889..8b29b98 100644 --- a/src/southbridge/intel/i82801gx/usb_debug.c +++ b/src/southbridge/intel/i82801gx/usb_debug.c @@ -17,9 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ -#define __PRE_RAM__ // Use simple device model for this file even in ramstage -#endif +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + #include <stdint.h> #include <arch/io.h> #include <console/console.h>

1 0

New patch to review for coreboot: 9de4759 Unify PCI configuration cycles
by Kyösti Mälkki 27 Jun '13

27 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3554 -gerrit commit 9de47592a250991359bc4c0512f4db2f0aabe8dc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 26 08:19:14 2013 +0300 Unify PCI configuration cycles Split PCI IO configuration and MMIO configuration cycles to separate files. Modern hardware does not use IO cycles for PCI configuration after initial setup in bootblock. Note that the pci_mmio_ and pcie_ functions were different in masking the alignment for register address. PCI standard requires that 16-bit and 32-bit configuration register writes do not cross boundaries. Change-Id: Ie6441283e1a033b4b395e972c18c31277f973897 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 183 +------------------------------ src/arch/x86/include/arch/pci_io_cfg.h | 109 ++++++++++++++++++ src/arch/x86/include/arch/pci_mmio_cfg.h | 26 ++++- 3 files changed, 133 insertions(+), 185 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 49499b9..82f83c8 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -213,187 +213,8 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha * Before that We need to use %gs, and leave %fs to other RAM access */ -static inline __attribute__((always_inline)) uint8_t pci_io_read_config8(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inb(0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - return read8(addr); -} -#endif -static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config8(dev, where); -#else - return pci_io_read_config8(dev, where); -#endif -} - -static inline __attribute__((always_inline)) uint16_t pci_io_read_config16(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inw(0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - return read16(addr); -} -#endif - -static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config16(dev, where); -#else - return pci_io_read_config16(dev, where); -#endif -} - - -static inline __attribute__((always_inline)) uint32_t pci_io_read_config32(device_t dev, unsigned where) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - return read32(addr); -} -#endif - -static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - return pci_mmio_read_config32(dev, where); -#else - return pci_io_read_config32(dev, where); -#endif -} - -static inline __attribute__((always_inline)) void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | where; - write8(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config8(dev, where, value); -#else - pci_io_write_config8(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outw(value, 0xCFC + (addr & 2)); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~1); - write16(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config16(dev, where, value); -#else - pci_io_write_config16(dev, where, value); -#endif -} - - -static inline __attribute__((always_inline)) void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; -#if !CONFIG_PCI_IO_CFG_EXT - addr = (dev>>4) | where; -#else - addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); -#endif - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -#if CONFIG_MMCONF_SUPPORT -static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value) -{ - unsigned addr; - addr = CONFIG_MMCONF_BASE_ADDRESS | dev | (where & ~3); - write32(addr, value); -} -#endif - -static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value) -{ -#if CONFIG_MMCONF_SUPPORT_DEFAULT - pci_mmio_write_config32(dev, where, value); -#else - pci_io_write_config32(dev, where, value); -#endif -} +#include <arch/pci_io_cfg.h> +#include <arch/pci_mmio_cfg.h> #include <arch/pci_mmio_cfg.h> diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h new file mode 100644 index 0000000..63e6a07 --- /dev/null +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PCI_IO_CFG_H +#define _PCI_IO_CFG_H + +static inline __attribute__((always_inline)) +uint8_t pci_io_read_config8(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); //seg == 0 +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inb(0xCFC + (addr & 3)); +} + +static inline __attribute__((always_inline)) +uint16_t pci_io_read_config16(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inw(0xCFC + (addr & 2)); +} + +static inline __attribute__((always_inline)) +uint32_t pci_io_read_config32(device_t dev, unsigned where) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +static inline __attribute__((always_inline)) +void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static inline __attribute__((always_inline)) +void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outw(value, 0xCFC + (addr & 2)); +} + +static inline __attribute__((always_inline)) +void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +{ + unsigned addr; +#if !CONFIG_PCI_IO_CFG_EXT + addr = (dev>>4) | where; +#else + addr = (dev>>4) | (where & 0xff) | ((where & 0xf00)<<16); +#endif + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#define pci_read_config8 pci_io_read_config8 +#define pci_read_config16 pci_io_read_config16 +#define pci_read_config32 pci_io_read_config32 + +#define pci_write_config8 pci_io_write_config8 +#define pci_write_config16 pci_io_write_config16 +#define pci_write_config32 pci_io_write_config32 +#endif + +#endif /* _PCI_IO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 7fb322d..ea59670 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -35,7 +35,7 @@ static inline __attribute__ ((always_inline)) u16 pcie_read_config16(device_t dev, unsigned int where) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~1); return read16(addr); } @@ -43,7 +43,7 @@ static inline __attribute__ ((always_inline)) u32 pcie_read_config32(device_t dev, unsigned int where) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~3); return read32(addr); } @@ -59,7 +59,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config16(device_t dev, unsigned int where, u16 value) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~1); write16(addr, value); } @@ -67,7 +67,7 @@ static inline __attribute__ ((always_inline)) void pcie_write_config32(device_t dev, unsigned int where, u32 value) { unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; + addr = DEFAULT_PCIEXBAR | dev | (where & ~3); write32(addr, value); } @@ -92,5 +92,23 @@ void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) pcie_write_config32(dev, where, value | ormask); } +#define pci_mmio_read_config8 pcie_read_config8 +#define pci_mmio_read_config16 pcie_read_config16 +#define pci_mmio_read_config32 pcie_read_config32 + +#define pci_mmio_write_config8 pcie_write_config8 +#define pci_mmio_write_config16 pcie_write_config16 +#define pci_mmio_write_config32 pcie_write_config32 + +#if CONFIG_MMCONF_SUPPORT_DEFAULT +#define pci_read_config8 pcie_read_config8 +#define pci_read_config16 pcie_read_config16 +#define pci_read_config32 pcie_read_config32 + +#define pci_write_config8 pcie_write_config8 +#define pci_write_config16 pcie_write_config16 +#define pci_write_config32 pcie_write_config32 +#endif + #endif /* CONFIG_MMCONF_SUPPORT */ #endif /* _PCI_MMIO_CFG_H */

1 0

Patch set updated for coreboot: 9a5164c Drop some duplicates of PCI-e config functions
by Kyösti Mälkki 27 Jun '13

27 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3502 -gerrit commit 9a5164cef237c27c7b402041c738834af66872a9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 19 23:05:00 2013 +0300 Drop some duplicates of PCI-e config functions These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 2 + src/arch/x86/include/arch/pci_mmio_cfg.h | 96 +++++++++++++++++++++++++ src/mainboard/google/stout/mainboard_smi.c | 1 - src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/i945/pcie_config.c | 68 ------------------ src/northbridge/intel/sandybridge/early_init.c | 1 - src/northbridge/intel/sandybridge/finalize.c | 1 - src/northbridge/intel/sandybridge/pcie_config.c | 89 ----------------------- src/northbridge/intel/sch/pcie_config.c | 66 ----------------- src/southbridge/intel/bd82x6x/finalize.c | 1 - src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/bd82x6x/spi.c | 2 +- src/southbridge/intel/i82801dx/smihandler.c | 6 -- src/southbridge/intel/i82801gx/smihandler.c | 2 +- src/southbridge/intel/sch/smihandler.c | 7 -- 17 files changed, 103 insertions(+), 246 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 29c8339..49499b9 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -395,6 +395,8 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de #endif } +#include <arch/pci_mmio_cfg.h> + static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) { pci_write_config8(dev, where, pci_read_config8(dev, where) | value); diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h new file mode 100644 index 0000000..7fb322d --- /dev/null +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PCI_MMIO_CFG_H +#define _PCI_MMIO_CFG_H + +#if CONFIG_MMCONF_SUPPORT +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pcie_read_config8(dev, where); + pcie_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pcie_read_config16(dev, where); + pcie_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pcie_read_config32(dev, where); + pcie_write_config32(dev, where, value | ormask); +} + +#endif /* CONFIG_MMCONF_SUPPORT */ +#endif /* _PCI_MMIO_CFG_H */ diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c index 7981046..8b37da3 100644 --- a/src/mainboard/google/stout/mainboard_smi.c +++ b/src/mainboard/google/stout/mainboard_smi.c @@ -24,7 +24,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> #include <cpu/intel/model_206ax/model_206ax.h> /* Include romstage serial for SIO helper functions */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930f..435d64d 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -23,7 +23,6 @@ #include <arch/io.h> #include <device/pci_def.h> #include "i945.h" -#include "pcie_config.c" int i945_silicon_revision(void) { diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c deleted file mode 100644 index 0310d67..0000000 --- a/src/northbridge/intel/i945/pcie_config.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "i945.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index c2d4909..4f2e038 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -25,7 +25,6 @@ #include <device/pci_def.h> #include <elog.h> #include "sandybridge.h" -#include "pcie_config.c" static void sandybridge_setup_bars(void) { diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 0fa8d1a..9b41cfa 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <stdlib.h> -#include "pcie_config.c" #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c deleted file mode 100644 index 0677d76..0000000 --- a/src/northbridge/intel/sandybridge/pcie_config.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include "sandybridge.h" - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} diff --git a/src/northbridge/intel/sch/pcie_config.c b/src/northbridge/intel/sch/pcie_config.c deleted file mode 100644 index ad7d746..0000000 --- a/src/northbridge/intel/sch/pcie_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read8(addr); -} - -static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read16(addr); -} - -static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - return read32(addr); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write8(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write16(addr, value); -} - -static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) -{ - unsigned long addr; - addr = DEFAULT_PCIEXBAR | dev | where; - write32(addr, value); -} diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index bcc2f3d..b1d2d34 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <console/post_codes.h> -#include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" #include <spi-generic.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 7fdf926..626e61a 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index f79adf5..72175d8 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,7 @@ #include <elog.h> #ifdef __SMM__ -# include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5913115..9588703 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -37,7 +37,7 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/sandybridge/sandybridge.h> -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 09169b1..c720afe 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,7 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <northbridge/intel/sandybridge/pcie_config.c> +#include <arch/pci_mmio_cfg.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 5470890..9b0c235 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -// #include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 2e29acd..e5bdfd8 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -206,7 +206,7 @@ static void dump_tco_status(u32 tco_sts) * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "../../../northbridge/intel/i945/pcie_config.c" +#include <arch/pci_mmio_cfg.h> int southbridge_io_trap_handler(int smif) { diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f..5074138 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00;

1 0

Patch set updated for coreboot: 6ffa11d Add simple_pcidev_t and simple_pnpdev_t
by Kyösti Mälkki 27 Jun '13

27 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3508 -gerrit commit 6ffa11dc84592cd368f6bc7d689f00de38f70f50 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 20 20:25:21 2013 +0300 Add simple_pcidev_t and simple_pnpdev_t Declare the functions that may be used in both romstage and ramstage to use simple_device_t instead. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 50 ++++++++++++++++++++------------ src/arch/x86/include/arch/pci_io_cfg.h | 12 ++++---- src/arch/x86/include/arch/pci_mmio_cfg.h | 18 ++++++------ src/include/device/device.h | 2 ++ 4 files changed, 48 insertions(+), 34 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 82f83c8..de4e1e3 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -206,7 +206,11 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) -typedef unsigned device_t; /* pci and pci_mmio need to have different ways to have dev */ +typedef unsigned int simple_pcidev_t; +typedef unsigned int simple_pnpdev_t; + +/* FIXME: Sources for devices need still use device_t. */ +typedef unsigned int device_t; /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore @@ -216,25 +220,26 @@ typedef unsigned device_t; /* pci and pci_mmio need to have different ways to ha #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> -#include <arch/pci_mmio_cfg.h> - -static inline __attribute__((always_inline)) void pci_or_config8(device_t dev, unsigned where, uint8_t value) +static inline __attribute__((always_inline)) +void pci_or_config8(simple_pcidev_t dev, unsigned where, uint8_t value) { pci_write_config8(dev, where, pci_read_config8(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config16(device_t dev, unsigned where, uint16_t value) +static inline __attribute__((always_inline)) +void pci_or_config16(simple_pcidev_t dev, unsigned where, uint16_t value) { pci_write_config16(dev, where, pci_read_config16(dev, where) | value); } -static inline __attribute__((always_inline)) void pci_or_config32(device_t dev, unsigned where, uint32_t value) +static inline __attribute__((always_inline)) +void pci_or_config32(simple_pcidev_t dev, unsigned where, uint32_t value) { pci_write_config32(dev, where, pci_read_config32(dev, where) | value); } #define PCI_DEV_INVALID (0xffffffffU) -static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) +static inline simple_pcidev_t pci_io_locate_device(unsigned pci_id, simple_pcidev_t dev) { for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -246,7 +251,7 @@ static inline device_t pci_io_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device(unsigned pci_id, device_t dev) +static inline simple_pcidev_t pci_locate_device(unsigned pci_id, simple_pcidev_t dev) { for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) { unsigned int id; @@ -258,9 +263,9 @@ static inline device_t pci_locate_device(unsigned pci_id, device_t dev) return PCI_DEV_INVALID; } -static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) +static inline simple_pcidev_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) { - device_t dev, last; + simple_pcidev_t dev, last; dev = PCI_DEV(bus, 0, 0); last = PCI_DEV(bus, 31, 7); @@ -276,53 +281,60 @@ static inline device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus) } /* Generic functions for pnp devices */ -static inline __attribute__((always_inline)) void pnp_write_config(device_t dev, uint8_t reg, uint8_t value) +static inline __attribute__((always_inline)) void pnp_write_config(simple_pnpdev_t dev, uint8_t reg, uint8_t value) { unsigned port = dev >> 8; outb(reg, port ); outb(value, port +1); } -static inline __attribute__((always_inline)) uint8_t pnp_read_config(device_t dev, uint8_t reg) +static inline __attribute__((always_inline)) uint8_t pnp_read_config(simple_pnpdev_t dev, uint8_t reg) { unsigned port = dev >> 8; outb(reg, port); return inb(port +1); } -static inline __attribute__((always_inline)) void pnp_set_logical_device(device_t dev) +static inline __attribute__((always_inline)) +void pnp_set_logical_device(simple_pnpdev_t dev) { unsigned device = dev & 0xff; pnp_write_config(dev, 0x07, device); } -static inline __attribute__((always_inline)) void pnp_set_enable(device_t dev, int enable) +static inline __attribute__((always_inline)) +void pnp_set_enable(simple_pnpdev_t dev, int enable) { pnp_write_config(dev, 0x30, enable?0x1:0x0); } -static inline __attribute__((always_inline)) int pnp_read_enable(device_t dev) +static inline __attribute__((always_inline)) +int pnp_read_enable(simple_pnpdev_t dev) { return !!pnp_read_config(dev, 0x30); } -static inline __attribute__((always_inline)) void pnp_set_iobase(device_t dev, unsigned index, unsigned iobase) +static inline __attribute__((always_inline)) +void pnp_set_iobase(simple_pnpdev_t dev, unsigned index, unsigned iobase) { pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); pnp_write_config(dev, index + 1, iobase & 0xff); } -static inline __attribute__((always_inline)) uint16_t pnp_read_iobase(device_t dev, unsigned index) +static inline __attribute__((always_inline)) +uint16_t pnp_read_iobase(simple_pnpdev_t dev, unsigned index) { return ((uint16_t)(pnp_read_config(dev, index)) << 8) | pnp_read_config(dev, index + 1); } -static inline __attribute__((always_inline)) void pnp_set_irq(device_t dev, unsigned index, unsigned irq) +static inline __attribute__((always_inline)) +void pnp_set_irq(simple_pnpdev_t dev, unsigned index, unsigned irq) { pnp_write_config(dev, index, irq); } -static inline __attribute__((always_inline)) void pnp_set_drq(device_t dev, unsigned index, unsigned drq) +static inline __attribute__((always_inline)) +void pnp_set_drq(simple_pnpdev_t dev, unsigned index, unsigned drq) { pnp_write_config(dev, index, drq & 0xff); } diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index 63e6a07..b863bc7 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -19,7 +19,7 @@ #define _PCI_IO_CFG_H static inline __attribute__((always_inline)) -uint8_t pci_io_read_config8(device_t dev, unsigned where) +uint8_t pci_io_read_config8(simple_pcidev_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -32,7 +32,7 @@ uint8_t pci_io_read_config8(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -uint16_t pci_io_read_config16(device_t dev, unsigned where) +uint16_t pci_io_read_config16(simple_pcidev_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -45,7 +45,7 @@ uint16_t pci_io_read_config16(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -uint32_t pci_io_read_config32(device_t dev, unsigned where) +uint32_t pci_io_read_config32(simple_pcidev_t dev, unsigned where) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -58,7 +58,7 @@ uint32_t pci_io_read_config32(device_t dev, unsigned where) } static inline __attribute__((always_inline)) -void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) +void pci_io_write_config8(simple_pcidev_t dev, unsigned where, uint8_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -71,7 +71,7 @@ void pci_io_write_config8(device_t dev, unsigned where, uint8_t value) } static inline __attribute__((always_inline)) -void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) +void pci_io_write_config16(simple_pcidev_t dev, unsigned where, uint16_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT @@ -84,7 +84,7 @@ void pci_io_write_config16(device_t dev, unsigned where, uint16_t value) } static inline __attribute__((always_inline)) -void pci_io_write_config32(device_t dev, unsigned where, uint32_t value) +void pci_io_write_config32(simple_pcidev_t dev, unsigned where, uint32_t value) { unsigned addr; #if !CONFIG_PCI_IO_CFG_EXT diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index ea59670..e5c1fc6 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -24,7 +24,7 @@ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(device_t dev, unsigned int where) +u8 pcie_read_config8(simple_pcidev_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -32,7 +32,7 @@ u8 pcie_read_config8(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(device_t dev, unsigned int where) +u16 pcie_read_config16(simple_pcidev_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~1); @@ -40,7 +40,7 @@ u16 pcie_read_config16(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(device_t dev, unsigned int where) +u32 pcie_read_config32(simple_pcidev_t dev, unsigned int where) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~3); @@ -48,7 +48,7 @@ u32 pcie_read_config32(device_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(device_t dev, unsigned int where, u8 value) +void pcie_write_config8(simple_pcidev_t dev, unsigned int where, u8 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | where; @@ -56,7 +56,7 @@ void pcie_write_config8(device_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(device_t dev, unsigned int where, u16 value) +void pcie_write_config16(simple_pcidev_t dev, unsigned int where, u16 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~1); @@ -64,7 +64,7 @@ void pcie_write_config16(device_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(device_t dev, unsigned int where, u32 value) +void pcie_write_config32(simple_pcidev_t dev, unsigned int where, u32 value) { unsigned long addr; addr = DEFAULT_PCIEXBAR | dev | (where & ~3); @@ -72,21 +72,21 @@ void pcie_write_config32(device_t dev, unsigned int where, u32 value) } static inline __attribute__ ((always_inline)) -void pcie_or_config8(device_t dev, unsigned int where, u8 ormask) +void pcie_or_config8(simple_pcidev_t dev, unsigned int where, u8 ormask) { u8 value = pcie_read_config8(dev, where); pcie_write_config8(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config16(device_t dev, unsigned int where, u16 ormask) +void pcie_or_config16(simple_pcidev_t dev, unsigned int where, u16 ormask) { u16 value = pcie_read_config16(dev, where); pcie_write_config16(dev, where, value | ormask); } static inline __attribute__ ((always_inline)) -void pcie_or_config32(device_t dev, unsigned int where, u32 ormask) +void pcie_or_config32(simple_pcidev_t dev, unsigned int where, u32 ormask) { u32 value = pcie_read_config32(dev, where); pcie_write_config32(dev, where, value | ormask); diff --git a/src/include/device/device.h b/src/include/device/device.h index 9defb19..bcfe03b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -10,6 +10,8 @@ struct device; #ifndef __PRE_RAM__ typedef struct device * device_t; +typedef unsigned int simple_pcidev_t; +typedef unsigned int simple_pnpdev_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations;

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Patch set updated for coreboot: b690c78 Add test to match struct device with simple_pcidev_t
by Kyösti Mälkki 27 Jun '13

27 Jun '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3474 -gerrit commit b690c78a405ebc96943a954ce09ab0bcc3a273df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 15 17:16:56 2013 +0300 Add test to match struct device with simple_pcidev_t Add a function to test if simple_pcidev_t matches with a device instance of struct device, by comparing bus:dev.fn. Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_device.c | 13 +++++++++++++ src/include/device/pci.h | 1 + src/include/device/pci_def.h | 4 ++++ 3 files changed, 18 insertions(+) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4c5a814..5164896 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1054,6 +1054,19 @@ device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn) } /** + * Test for match between romstage and ramstage device instance. + * + * @param dev Pointer to the device structure. + * @param sdev Simple device model identifier, created with PCI_DEV(). + * @return Non-zero if bus:dev.fn of device matches. + */ +unsigned int pci_match_simple_dev(device_t dev, simple_pcidev_t sdev) +{ + return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); +} + +/** * Scan a PCI bus. * * Determine the existence of devices and bridges on a PCI bus. If there are diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 1f47daf..c4978ef 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -77,6 +77,7 @@ unsigned pci_find_capability(device_t dev, unsigned cap); struct resource *pci_get_resource(struct device *dev, unsigned long index); void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); +unsigned int pci_match_simple_dev(device_t dev, simple_pcidev_t sdev); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 58a7321..c24c445 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -474,4 +474,8 @@ #define PCI_FUNC(devfn) ((devfn) & 0x07) #define PCI_BDF(bus,dev,func) ((bus) << 16 | (dev) << 11 | (func) << 8) +/* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ +#define PCI_DEV2DEVFN(sdev) ((sdev>>12)&0xff) +#define PCI_DEV2SEGBUS(sdev) ((sdev>>20)&0xfff) + #endif /* PCI_DEF_H */

1 0

Patch set updated for coreboot: c9c7e40 amd/dinar: Eliminate compiler warnings from build
by Paul Menzel 27 Jun '13

27 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3545 -gerrit commit c9c7e406d69b93532b5d1a944a43adfe92c068a8 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:02:41 2013 -0600 amd/dinar: Eliminate compiler warnings from build Fix a bunch of compiler-generated warning messages. These fixes are mainly copied into AMD Family 15 server boards from similar code in AMD Family 15tn (Trinity) boards. Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/dinar/BiosCallOuts.c | 1 - src/mainboard/amd/dinar/agesawrapper.c | 19 +++-- src/mainboard/amd/dinar/agesawrapper.h | 4 +- src/mainboard/amd/dinar/buildOpts.c | 132 +++++++++++++++++++++++++-------- src/mainboard/amd/dinar/romstage.c | 2 + 5 files changed, 117 insertions(+), 41 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 4fb3c66..c9888b9 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -584,7 +584,6 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT32 GpioMmioAddr; UINT8 Data8; UINT16 Data16; - UINT8 TempData8; FcnData = Data; MemData = ConfigPtr; diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 4017adc..179822b 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -75,6 +75,8 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); +extern VOID OemCustomizeInitPost(IN AMD_POST_PARAMS *InitPost); /*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ /* @@ -88,6 +90,7 @@ Bits Buses Bits Buses 3h 8 8h 256 4h 16 Fh-9h Reserved */ +STATIC UINT8 GetEndBusNum ( VOID @@ -283,9 +286,12 @@ agesawrapper_amdinitreset ( ) { AGESA_STATUS status; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; +#endif +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -307,12 +313,13 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); -#endif - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); +#else + status = AGESA_SUCCESS; +#endif + return (UINT32)status; } @@ -432,8 +439,6 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue; LibAmdMemFill (&AmdParamStruct, 0, @@ -574,11 +579,11 @@ agesawrapper_amdlaterunaptask ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AP_EXE_PARAMS AmdLateParams; LibAmdMemFill (&AmdLateParams, 0, - sizeof (AMD_LATE_PARAMS), + sizeof (AP_EXE_PARAMS), &(AmdLateParams.StdHeader)); AmdLateParams.StdHeader.AltImageBasePtr = 0; diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index 0b4a701..62fd277 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -126,11 +126,9 @@ UINT32 agesawrapper_amdinitenv (void); UINT32 agesawrapper_amdinitlate (void); UINT32 agesawrapper_amdinitpost (void); UINT32 agesawrapper_amdinitmid (void); -void sb_After_Pci_Init (void); -void sb_Mid_Post_Init (void); -void sb_Late_Post (void); UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Data, VOID *ConfigPtr); #endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 1d57d7a..41f5415 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -36,13 +36,39 @@ #include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - +//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE +/* AGESA will check the OEM configuration during preprocessing stage, + * coreboot enable -Wundef option, so we should make sure we have all contanstand defined + */ +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE */ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode /* Select the cpu family. */ /* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE #define INSTALL_S1G4_SOCKET_SUPPORT FALSE @@ -211,17 +237,41 @@ */ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - 0, 0, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + { //BUID Swap List + { //BUID Swaps + /* Each Non-coherent chain may have a list of device swaps, + * Each item specify a device will be swap from its current id to a new one + */ + /* FromID 0x00 is the chain with the southbridge */ + /* 'Move' device zero to device zero, All others are non applicable */ + {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + }, + + { //The ordered final BUIDs + /* Specify the final BUID to be zero, All others are non applicable */ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + } + } + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } }; #define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList @@ -236,20 +286,32 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, - HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_TERMINAL + { + /* On the reference platform, these settings apply to all coherent links */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + }, + + { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } }; #define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList // A performance-per-watt optimization. CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, - HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, - HT_LIST_TERMINAL, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF }, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF }, + { HT_LIST_TERMINAL } }; // uncomment the line below to make Perf-per-watt enabled by default. @@ -258,8 +320,18 @@ CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_TERMINAL + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, //Actually IO hub only support 2600M MAX + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } }; #define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList @@ -283,9 +355,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = { // Socket, Link, SecBus, SubBus - 0, 2, 0x00, 0xBF, // RD890 of Dinar - 1, 0, 0xC0, 0xFF, // HTX - HT_LIST_TERMINAL + { 0, 2, 0x00, 0xBF }, // RD890 of Dinar + { 1, 0, 0xC0, 0xFF }, // HTX + { (HT_LIST_TERMINAL) } }; #define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers @@ -295,7 +367,7 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, - 0xFF + { (0xFF) } }; #define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList @@ -314,9 +386,9 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = */ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, - HT_LIST_TERMINAL + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, 0 }, + { (HT_LIST_TERMINAL) } }; #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 77f73e2..e52b5f7 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -41,6 +41,8 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); u32 agesawrapper_amdinitearly (void);

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Patch set updated for coreboot: 4d03347 AMD SB700 boards: Set Azalia configuration flags
by Paul Menzel 27 Jun '13

27 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3544 -gerrit commit 4d0334704bb3ba1f7f8b63967efd9ce7c0ec97a2 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:01:21 2013 -0600 AMD SB700 boards: Set Azalia configuration flags The existing code for setting Azalia configuration assumes that the configuration bits are contiguous within a single byte and can be set using a byte copy addressed into the lowest 2-bit subfield. The fix in Family 14 defines a union that can be addressed as a byte to overlay the bit fields. Since the offset of the four subfields is not necessarily fixed, change the code to initialize each of the four subfields individually. Change-Id: I1dff20bb8bd3e1bcd8b4e6b0537e20779d2a3521 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/dinar/sb700_cfg.c | 5 ++++- src/mainboard/amd/dinar/sb700_cfg.h | 6 +++++- src/mainboard/supermicro/h8qgi/sb700_cfg.c | 5 ++++- src/mainboard/supermicro/h8qgi/sb700_cfg.h | 6 +++++- src/mainboard/supermicro/h8scm/sb700_cfg.c | 5 ++++- src/mainboard/supermicro/h8scm/sb700_cfg.h | 6 +++++- 6 files changed, 27 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 94e4b40..c9a0949 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -126,7 +126,10 @@ void sb700_cimx_config(AMDSBCFG *sb_config) /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; + sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; + sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; + sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; sb_config->pAzaliaOemCodecTablePtr = NULL; #ifndef __PRE_RAM__ diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 371c7ce..216c264 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -192,7 +192,11 @@ */ #ifndef AZALIA_SDIN_PIN //#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif /** diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.c b/src/mainboard/supermicro/h8qgi/sb700_cfg.c index 54c139a..ff2334f 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.c +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.c @@ -126,7 +126,10 @@ void sb700_cimx_config(AMDSBCFG *sb_config) /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; + sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; + sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; + sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; sb_config->pAzaliaOemCodecTablePtr = NULL; #ifndef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8qgi/sb700_cfg.h b/src/mainboard/supermicro/h8qgi/sb700_cfg.h index a3e5a38..1df3fc5 100644 --- a/src/mainboard/supermicro/h8qgi/sb700_cfg.h +++ b/src/mainboard/supermicro/h8qgi/sb700_cfg.h @@ -192,7 +192,11 @@ */ #ifndef AZALIA_SDIN_PIN //#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif /** diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.c b/src/mainboard/supermicro/h8scm/sb700_cfg.c index 12169e6..c03a501 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.c +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.c @@ -126,7 +126,10 @@ void sb700_cimx_config(AMDSBCFG *sb_config) /* Azalia HDA */ sb_config->AzaliaController = AZALIA_CONTROLLER; sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN_0; + sb_config->AzaliaSdin1 = AZALIA_SDIN_PIN_1; + sb_config->AzaliaSdin2 = AZALIA_SDIN_PIN_2; + sb_config->AzaliaSdin3 = AZALIA_SDIN_PIN_3; sb_config->pAzaliaOemCodecTablePtr = NULL; #ifndef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h index eca355f..40c89fa 100644 --- a/src/mainboard/supermicro/h8scm/sb700_cfg.h +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -192,7 +192,11 @@ */ #ifndef AZALIA_SDIN_PIN //#define AZALIA_SDIN_PIN 0xAA -#define AZALIA_SDIN_PIN 0x2A +#define AZALIA_SDIN_PIN +#define AZALIA_SDIN_PIN_0 0x2 +#define AZALIA_SDIN_PIN_1 0x2 +#define AZALIA_SDIN_PIN_2 0x2 +#define AZALIA_SDIN_PIN_3 0x0 #endif /**

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Patch set updated for coreboot: 1cf9b41 Supermicro H8SCM/H8QGI: Increase size of bus variable to meet API
by Paul Menzel 27 Jun '13

27 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3546 -gerrit commit 1cf9b41e64234c3d26e914a23ca2aa05411be28f Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 19:13:28 2013 -0600 Supermicro H8SCM/H8QGI: Increase size of bus variable to meet API Users of mptable_write_buses() pass two pass-by-reference parameters reflecting a maximum bus number and a search bus number. These bus numbers are expected to be held in "int" variables and are updated by the function. Both of the Supermicro boards define the search bus number as a byte value in mptable.c. For now, change the two Supermicro boards to use "int" to hold the search bus index. Change-Id: Ie71850719c1fa3cda0ac9c8773bb80650de95c70 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/supermicro/h8qgi/mptable.c | 2 +- src/mainboard/supermicro/h8scm/mptable.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 2c112ce..c10a219 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -33,7 +33,7 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; -extern u8 bus_isa; +extern int bus_isa; static void *smp_write_config_table(void *v) diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 2c112ce..c10a219 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -33,7 +33,7 @@ extern u8 bus_sp5100[2]; extern u32 bus_type[256]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; -extern u8 bus_isa; +extern int bus_isa; static void *smp_write_config_table(void *v)

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Patch set updated for coreboot: 9a59d74 amd/cimx/sb700/late.c: Add type cast to (UINT8)
by Paul Menzel 27 Jun '13

27 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3541 -gerrit commit 9a59d74a7d8cc210f11f6a710f1acd26a501e849 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:29:08 2013 -0600 amd/cimx/sb700/late.c: Add type cast to (UINT8) This change inserts a type cast to eliminate a compiler warning. Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/southbridge/amd/cimx/sb700/late.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index ede9fb3..b259a7b 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -254,7 +254,7 @@ static void sb700_enable(device_t dev) /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1) /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); + setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS)); #elif (CONFIG_APIC_ID_OFFSET > 0) /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ setup_ioapic(ioapic_base, 0);

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coreboot-gerrit June 2013