June 2013 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: fc68519 amd/agesa/f15/Proc/CPU: Add length modifier to eliminate compiler warnings
by Paul Menzel June 26, 2013

June 26, 2013

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3538 -gerrit commit fc68519b50c859595be5594311d0a269e31ebb59 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:53:24 2013 -0600 amd/agesa/f15/Proc/CPU: Add length modifier to eliminate compiler warnings This change adds length modifiers to constant values to eliminate compiler warning messages. Change-Id: I032cb37cec788e2b5f79f5bbf9efc19a7892dc14 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- .../amd/agesa/f15/Proc/CPU/cpuApicUtilities.c | 10 +- .../amd/agesa/f15/Proc/CPU/cpuRegisters.h | 192 +++++++++++---------- 2 files changed, 102 insertions(+), 100 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c index 7d1355c..f6d452e 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c @@ -68,11 +68,11 @@ RDATA_GROUP (G2_PEI) *---------------------------------------------------------------------------------------- */ /* ApFlags bits */ -#define AP_TASK_HAS_INPUT 0x00000001 -#define AP_TASK_HAS_OUTPUT 0x00000002 -#define AP_RETURN_PARAMS 0x00000004 -#define AP_END_AT_HLT 0x00000008 -#define AP_PASS_EARLY_PARAMS 0x00000010 +#define AP_TASK_HAS_INPUT 0x00000001ul +#define AP_TASK_HAS_OUTPUT 0x00000002ul +#define AP_RETURN_PARAMS 0x00000004ul +#define AP_END_AT_HLT 0x00000008ul +#define AP_PASS_EARLY_PARAMS 0x00000010ul #define XFER_ELEMENT_SIZE sizeof (UINT32) diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h index e81ded3..e0959fc 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuRegisters.h @@ -129,10 +129,10 @@ #define BIT63 0x8000000000000000ull /// CPUID related registers -#define AMD_CPUID_FMF 0x80000001 // Family Model Features information -#define AMD_CPUID_APICID_LPC_BID 0x00000001 // Local APIC ID, Logical Processor Count, Brand ID -#define AMD_CPUID_TLB_L1Cache 0x80000005 -#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006 +#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID +#define AMD_CPUID_TLB_L1Cache 0x80000005ul +#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul #define CPUID_ASSOCIATIVITY_2_WAY 0x02 #define CPUID_ASSOCIATIVITY_4_WAY 0x04 #define CPUID_ASSOCIATIVITY_8_WAY 0x06 @@ -142,10 +142,10 @@ #define CPUID_ASSOCIATIVITY_64_WAY 0x0C #define CPUID_ASSOCIATIVITY_96_WAY 0x0D #define CPUID_ASSOCIATIVITY_128_WAY 0x0E -#define AMD_CPUID_APM 0x80000007 +#define AMD_CPUID_APM 0x80000007ul #define LOCAL_APIC_ID 24 #define LOGICAL_PROCESSOR_COUNT 16 -#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008 // Address Size, Physical Core Count +#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count /// CPU Logical ID Transfer typedef struct { @@ -161,20 +161,20 @@ typedef struct { // MSRs // ------------------------ -#define MCG_CTL_P 0x00000100 // bit 8 for MCG_CTL_P under MSRR -#define MSR_MCG_CAP 0x00000179 -#define MSR_MC0_CTL 0x00000400 +#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR +#define MSR_MCG_CAP 0x00000179ul +#define MSR_MC0_CTL 0x00000400ul -#define MSR_APIC_BAR 0x0000001B -#define MSR_PATCH_LEVEL 0x0000008B +#define MSR_APIC_BAR 0x0000001Bul +#define MSR_PATCH_LEVEL 0x0000008Bul -#define CPUID_LONG_MODE_ADDR 0x80000008 -#define AMD_CPUID_FMF 0x80000001 +#define CPUID_LONG_MODE_ADDR 0x80000008ul +#define AMD_CPUID_FMF 0x80000001ul -#define MSR_EXTENDED_FEATURE_EN 0xC0000080 -#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408 -#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409 -#define MSR_PATCH_LOADER 0xC0010020 +#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul +#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul +#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul +#define MSR_PATCH_LOADER 0xC0010020ul /// Patch Loader Register typedef struct { @@ -182,49 +182,49 @@ typedef struct { UINT64 SBZ:32; ///< Should be zero } PATCH_LOADER_MSR; -#define MSR_SYS_CFG 0xC0010010 // SYSCFG - F15 Shared -#define MSR_TOM2 0xC001001D // TOP_MEM2 - F15 Shared -#define MSR_MC0_CTL_MASK 0xC0010044 // MC0 Control Mask -#define MSR_MC1_CTL_MASK 0xC0010045 // MC1 Control Mask -#define MSR_MC2_CTL_MASK 0xC0010046 // MC2 Control Mask -#define MSR_MC4_CTL_MASK 0xC0010048 // MC4 Control Mask - -#define MSR_CPUID_FEATS 0xC0011004 // CPUID Features -#define MSR_CPUID_EXT_FEATS 0xC0011005 // CPUID Extended Features -#define MSR_HWCR 0xC0010015 -#define MSR_NB_CFG 0xC001001F // NB Config -#define ENABLE_CF8_EXT_CFG 0x00004000 // [46] -#define INIT_APIC_CPUID_LO 0x00400000 // [54] -#define MSR_LS_CFG 0xC0011020 -#define MSR_IC_CFG 0xC0011021 // ICache Config - F15 Shared -#define MSR_DC_CFG 0xC0011022 -#define MSR_ME_CFG 0xC0011029 -#define MSR_BU_CFG 0xC0011023 -#define MSR_CU_CFG 0xC0011023 // F15 Shared -#define MSR_DE_CFG 0xC0011029 // F15 Shared -#define MSR_BU_CFG2 0xC001102A -#define MSR_CU_CFG2 0xC001102A // F15 Shared -#define MSR_BU_CFG3 0xC001102B -#define MSR_CU_CFG3 0xC001102B // F15 Shared -#define MSR_LS_CFG2 0xC001102D -#define MSR_IBS_OP_DATA3 0xC0011037 -#define MSR_C001_1070 0xC0011070 // F15 Shared - - -#define MSR_CPUID_NAME_STRING0 0xC0010030 // First CPUID namestring register -#define MSR_CPUID_NAME_STRING1 0xC0010031 -#define MSR_CPUID_NAME_STRING2 0XC0010032 -#define MSR_CPUID_NAME_STRING3 0xC0010033 -#define MSR_CPUID_NAME_STRING4 0xC0010034 -#define MSR_CPUID_NAME_STRING5 0xC0010035 // Last CPUID namestring register -#define MSR_MMIO_Cfg_Base 0xC0010058 // MMIO Configuration Base Address Register -#define MSR_BIST 0xC0010060 // BIST Results register -#define MSR_OSVW_ID_Length 0xC0010140 -#define MSR_OSVW_Status 0xC0010141 -#define MSR_PERF_CONTROL3 0xC0010003 // Perfromance control register number 3 -#define MSR_PERF_COUNTER3 0xC0010007 // Performance counter register number 3 -#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFF // Mask of the Performance control Reserve bits -#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2 // Configure the controller to capture the +#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared +#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared +#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask +#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask +#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask +#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask + +#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features +#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features +#define MSR_HWCR 0xC0010015ul +#define MSR_NB_CFG 0xC001001Ful // NB Config +#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46] +#define INIT_APIC_CPUID_LO 0x00400000ul // [54] +#define MSR_LS_CFG 0xC0011020ul +#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared +#define MSR_DC_CFG 0xC0011022ul +#define MSR_ME_CFG 0xC0011029ul +#define MSR_BU_CFG 0xC0011023ul +#define MSR_CU_CFG 0xC0011023ul // F15 Shared +#define MSR_DE_CFG 0xC0011029ul // F15 Shared +#define MSR_BU_CFG2 0xC001102Aul +#define MSR_CU_CFG2 0xC001102Aul // F15 Shared +#define MSR_BU_CFG3 0xC001102Bul +#define MSR_CU_CFG3 0xC001102Bul // F15 Shared +#define MSR_LS_CFG2 0xC001102Dul +#define MSR_IBS_OP_DATA3 0xC0011037ul +#define MSR_C001_1070 0xC0011070ul // F15 Shared + + +#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register +#define MSR_CPUID_NAME_STRING1 0xC0010031ul +#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING3 0xC0010033ul +#define MSR_CPUID_NAME_STRING4 0xC0010034ul +#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register +#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register +#define MSR_BIST 0xC0010060ul // BIST Results register +#define MSR_OSVW_ID_Length 0xC0010140ul +#define MSR_OSVW_Status 0xC0010141ul +#define MSR_PERF_CONTROL3 0xC0010003ul // Perfromance control register number 3 +#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3 +#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits +#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ull // Configure the controller to capture the // CAR Corruption // FUNC_0 registers // ---------------- @@ -243,26 +243,26 @@ typedef struct { #define HT_INIT_BIOS_RST_DET_2 BIT10 #define HT_INIT_BIOS_RST_DET BIT9 | BIT10 #define HT_TRANS_CTRL 0x68 -#define HT_TRANS_CTRL_CPU1_EN 0x00000020 // [5] = CPU1 Enable +#define HT_TRANS_CTRL_CPU1_EN 0x00000020ul // [5] = CPU1 Enable #define HT_LINK_CONTROL_0 0x84 #define HT_LINK_FREQ_0 0x88 // Link HT Frequency #define EXTENDED_NODE_ID 0x160 #define ECS_HT_TRANS_CTRL 0x168 -#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001 // [0] = CPU2 Enable -#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002 // [1] = CPU3 Enable -#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004 // [2] = CPU4 Enable -#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008 // [3] = CPU5 Enable +#define ECS_HT_TRANS_CTRL_CPU2_EN 0x00000001ul // [0] = CPU2 Enable +#define ECS_HT_TRANS_CTRL_CPU3_EN 0x00000002ul // [1] = CPU3 Enable +#define ECS_HT_TRANS_CTRL_CPU4_EN 0x00000004ul // [2] = CPU4 Enable +#define ECS_HT_TRANS_CTRL_CPU5_EN 0x00000008ul // [3] = CPU5 Enable #define CORE_CTRL 0x1DC -#define CORE_CTRL_CORE1_EN 0x00000002 -#define CORE_CTRL_CORE2_EN 0x00000004 -#define CORE_CTRL_CORE3_EN 0x00000008 -#define CORE_CTRL_CORE4_EN 0x00000010 -#define CORE_CTRL_CORE5_EN 0x00000020 -#define CORE_CTRL_CORE6_EN 0x00000040 -#define CORE_CTRL_CORE7_EN 0x00000080 -#define CORE_CTRL_CORE8_EN 0x00000100 -#define CORE_CTRL_CORE9_EN 0x00000200 +#define CORE_CTRL_CORE1_EN 0x00000002ul +#define CORE_CTRL_CORE2_EN 0x00000004ul +#define CORE_CTRL_CORE3_EN 0x00000008ul +#define CORE_CTRL_CORE4_EN 0x00000010ul +#define CORE_CTRL_CORE5_EN 0x00000020ul +#define CORE_CTRL_CORE6_EN 0x00000040ul +#define CORE_CTRL_CORE7_EN 0x00000080ul +#define CORE_CTRL_CORE8_EN 0x00000100ul +#define CORE_CTRL_CORE9_EN 0x00000200ul // FUNC_3 registers // ---------------- @@ -284,11 +284,11 @@ typedef struct { #define REG_HT4_PHY_OFFSET_BASE_4X180 0x180 #define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184 -#define HTPHY_OFFSET_MASK 0xE00001FF -#define HTPHY_WRITE_CMD 0x40000000 -#define HTPHY_IS_COMPLETE_MASK 0x80000000 -#define HTPHY_DIRECT_MAP 0x20000000 -#define HTPHY_DIRECT_OFFSET_MASK 0x6000FFFF +#define HTPHY_OFFSET_MASK 0xE00001FFul +#define HTPHY_WRITE_CMD 0x40000000ul +#define HTPHY_IS_COMPLETE_MASK 0x80000000ul +#define HTPHY_DIRECT_MAP 0x20000000ul +#define HTPHY_DIRECT_OFFSET_MASK 0x6000FFFFul // FUNC_5 registers // ---------------- @@ -338,10 +338,12 @@ typedef struct { #define KM_SOCKET_C2012 5 #define SOCKET_IGNORE 0xF -#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000 -#define APIC_EXT_BRDCST_MASK 0x000E0000 -#define APIC_ENABLE_BIT 0x00000800 -#define LOCAL_APIC_ADDR 0xFEE00000 +#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull +#define APIC_EXT_BRDCST_MASK 0x000E0000ul +#define APIC_ENABLE_BIT 0x00000800ul +#ifndef LOCAL_APIC_ADDR +#define LOCAL_APIC_ADDR 0xFEE00000ul +#endif #define INT_CMD_REG_LO 0x300 #define INT_CMD_REG_HI 0x310 #define REMOTE_MSG_REG 0x380 @@ -357,20 +359,20 @@ typedef struct { * Default definitions *------------------------- */ -#define DOWNCORE_MASK_SINGLE 0xFFFFFFFE -#define DOWNCORE_MASK_DUAL 0xFFFFFFFC -#define DOWNCORE_MASK_TRI 0xFFFFFFF8 -#define DOWNCORE_MASK_FOUR 0xFFFFFFF0 -#define DOWNCORE_MASK_FIVE 0xFFFFFFE0 -#define DOWNCORE_MASK_SIX 0xFFFFFFC0 -#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFA -#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEA -#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAA +#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul +#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul +#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul +#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul +#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul +#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul +#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul +#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul +#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul #define DELIVERY_STATUS BIT13 -#define REMOTE_READ_STAT_MASK 0x00030000 -#define REMOTE_DELIVERY_PENDING 0x00010000 -#define REMOTE_DELIVERY_DONE 0x00020000 +#define REMOTE_READ_STAT_MASK 0x00030000ul +#define REMOTE_DELIVERY_PENDING 0x00010000ul +#define REMOTE_DELIVERY_DONE 0x00020000ul /* * --------------------------------------------------------------------------------------

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Patch set updated for coreboot: fbfc243 supermicro/h8scm: Add a type cast for printk to correct a warning message
by Paul Menzel June 26, 2013

June 26, 2013

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3543 -gerrit commit fbfc243c390243a31378c00ad6081459e564ddb5 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 13:59:36 2013 -0600 supermicro/h8scm: Add a type cast for printk to correct a warning message Copy a type cast from the other cases of the same switch statement to eliminate compiler warning messages. Change-Id: I8d0a88892f6a5f8e43227ab5f830041894b07f6a Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/supermicro/h8scm/agesawrapper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index 729b669..49abe25 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -736,9 +736,9 @@ static void agesa_warning(EVENT_PARAMS *event) case HT_EVENT_OPT_REQUIRED_CAP_RETRY: printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %x Link %x Depth %x\n", - event->DataParam1, - event->DataParam2, - event->DataParam3); + (unsigned int)event->DataParam1, + (unsigned int)event->DataParam2, + (unsigned int)event->DataParam3); break; case HT_EVENT_OPT_REQUIRED_CAP_GEN3:

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Patch set updated for coreboot: 40e3907 /amd/agesa/family15/northbridge.c: Delete unused variable
by Paul Menzel June 26, 2013

June 26, 2013

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3526 -gerrit commit 40e3907d566f50be9e51a3a3f3fb6ac08a86204d Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:21:44 2013 -0600 /amd/agesa/family15/northbridge.c: Delete unused variable This change eliminates an unused variable that causes a build warning. Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 6134830..9e5538d 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1060,7 +1060,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); for (j = 0; j <= siblings; j++ ) { - extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration; u32 lapicid_start = 0; /*

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Patch set updated for coreboot: 42aeec7 amd/cimx/rd890/amd.h: Eliminate redefinition of NULL
by Paul Menzel June 26, 2013

June 26, 2013

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3540 -gerrit commit 42aeec7507809d53ddcc3fc606147aeb17c03631 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 14:27:16 2013 -0600 amd/cimx/rd890/amd.h: Eliminate redefinition of NULL This change replaces a redefinition of NULL with the standard definition from <stddef.h> to eliminate a compiler redefinition warning. Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/northbridge/amd/cimx/rd890/amd.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index 1ceff80..e7a9ca9 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -32,10 +32,7 @@ // AGESA Types and Definitions // // -#ifndef NULL - #define NULL 0 -#endif - +#include <stddef.h> #define LAST_ENTRY 0xFFFFFFFF #define IOCF8 0xCF8

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Patch set updated for coreboot: 54a3301 Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf()
by Paul Menzel June 26, 2013

June 26, 2013

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3542 -gerrit commit 54a33012b549cb2be0dc20087f960b855622a5a1 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Tue Jun 25 19:27:17 2013 -0600 Dinar, H8SCM, H8QGI: Add prototype of get_bus_conf() On Dinar, H8SCM, and H8QGI, add <cpu/amd/amdfam15.h> as an include to pick up the prototype definition of get_bus_conf(). Change-Id: Ie4887670ac52aa194745881362df19cd1d75773e Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/dinar/acpi_tables.c | 1 + src/mainboard/amd/dinar/irq_tables.c | 3 +-- src/mainboard/amd/dinar/mptable.c | 1 + src/mainboard/supermicro/h8qgi/get_bus_conf.c | 1 + src/mainboard/supermicro/h8scm/get_bus_conf.c | 1 + 5 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c index a3aa213..c4a42dc 100644 --- a/src/mainboard/amd/dinar/acpi_tables.c +++ b/src/mainboard/amd/dinar/acpi_tables.c @@ -29,6 +29,7 @@ #include <cpu/amd/mtrr.h> #include "agesawrapper.h" +#include <cpu/amd/amdfam15.h> #define DUMP_ACPI_TABLES 0 diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c index b67f89f..0bf66bb 100644 --- a/src/mainboard/amd/dinar/irq_tables.c +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -23,8 +23,7 @@ #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> - - +#include <cpu/amd/amdfam15.h> static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 42b43bb..60779f8 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -26,6 +26,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> +#include <cpu/amd/amdfam15.h> extern u8 bus_rd890[14]; extern u8 bus_sb700[2]; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 7682eec..ffaa81b 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <stdlib.h> #include "agesawrapper.h" +#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 3dc8471..eff9504 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -24,6 +24,7 @@ #include <stdint.h> #include <stdlib.h> #include "agesawrapper.h" +#include <cpu/amd/amdfam10_sysconf.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif

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Patch merged into coreboot/master: 714212a Revert "Add support to enable/disable builtin GbE"
by gerrit＠coreboot.org June 26, 2013

June 26, 2013

the following patch was just integrated into master: commit 714212a42115b205b132a901bf86b8876d6aa3f0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 26 23:20:13 2013 +0200 Revert "Add support to enable/disable builtin GbE" This reverts commit d358a506c4230950e34d783bd0187cd200d60691 http://review.coreboot.org/#/c/3514/ comments: The pei_data version changed to 6, so new binaries are needed. However, demand for new binary blob is not referenced with this commit nor is git submodules hash updated. Also the new binary blob almost doubles its size and no longer fits in the allocation sandybridge defines. Change-Id: I84eb70517d5b9278c611fdfa587a71f6ca0f657f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/3553 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3553 for details. -gerrit

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New patch to review for coreboot: 9fe563d Revert "Add support to enable/disable builtin GbE"
by Kyösti Mälkki June 26, 2013

June 26, 2013

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3553 -gerrit commit 9fe563db87bf6a2bc20c018b310ac9c0c82d679b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 26 23:20:13 2013 +0200 Revert "Add support to enable/disable builtin GbE" This reverts commit d358a506c4230950e34d783bd0187cd200d60691 http://review.coreboot.org/#/c/3514/ comments: The pei_data version changed to 6, so new binaries are needed. However, demand for new binary blob is not referenced with this commit nor is git submodules hash updated. Also the new binary blob almost doubles its size and no longer fits in the allocation sandybridge defines. Change-Id: I84eb70517d5b9278c611fdfa587a71f6ca0f657f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/haswell/pei_data.h | 3 +-- src/northbridge/intel/sandybridge/pei_data.h | 3 +-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 7c10e41..280c73b 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -31,7 +31,7 @@ #define PEI_DATA_H typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 11 +#define PEI_VERSION 10 struct pei_data { @@ -53,7 +53,6 @@ struct pei_data uint8_t spd_addresses[4]; int boot_mode; int ec_present; - int gbe_enable; // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index d317515..fb56873 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -38,7 +38,7 @@ typedef struct { } pch_usb3_controller_settings; typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 6 +#define PEI_VERSION 5 struct pei_data { @@ -61,7 +61,6 @@ struct pei_data uint8_t ts_addresses[4]; int boot_mode; int ec_present; - int gbe_enable; // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel

1 0

New patch to review for coreboot: 361f727 ELOG: Fix warning to fix the compilation.
by Denis Carikli June 26, 2013

June 26, 2013

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3551 -gerrit commit 361f72705bae7a0edc2c390cc18af53f69bee9b7 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 26 20:04:49 2013 +0200 ELOG: Fix warning to fix the compilation. Without that fix we have: src/drivers/elog/elog.c: In function 'elog_is_header_valid': src/drivers/elog/elog.c:213:3: error: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'long unsigned int' [-Werror=format] Change-Id: I71b80a94c03a04eedb688ae107d92c05a878315e Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/drivers/elog/elog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 1a794d9..102dc37 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -210,7 +210,7 @@ static int elog_is_header_valid(struct elog_header *header) return 0; } if (header->header_size != sizeof(*header)) { - printk(BIOS_ERR, "ELOG: header size mismatch %u != %u\n", + printk(BIOS_ERR, "ELOG: header size mismatch %u != %lu\n", header->header_size, sizeof(*header)); return 0; }

1 0

New patch to review for coreboot: 0959c88 Add an alternative bootblock implementation.
by Denis Carikli June 26, 2013

June 26, 2013

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit 0959c88ac7136d42fd82fba42c68a470dce2c778 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add an alternative bootblock implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 ++++++ src/arch/x86/include/arch/cbfs.h | 8 ++++ src/arch/x86/init/bootblock_failboot.c | 53 ++++++++++++++++++++++ src/cpu/amd/agesa/cache_as_ram.inc | 9 +++- src/cpu/amd/car/cache_as_ram.inc | 9 +++- src/cpu/amd/geode_gx2/cache_as_ram.inc | 11 +++++ src/cpu/amd/geode_lx/cache_as_ram.inc | 11 +++++ src/cpu/intel/car/cache_as_ram.inc | 9 ++++ src/cpu/intel/car/cache_as_ram_ht.inc | 12 +++++ src/cpu/intel/haswell/cache_as_ram.inc | 11 +++++ src/cpu/intel/model_2065x/cache_as_ram.inc | 9 ++++ src/cpu/intel/model_206ax/cache_as_ram.inc | 9 ++++ src/cpu/intel/model_6ex/cache_as_ram.inc | 9 ++++ src/cpu/via/car/cache_as_ram.inc | 8 ++++ src/cpu/x86/16bit/entry16.inc | 8 ++++ src/cpu/x86/32bit/entry32.inc | 10 +++- src/cpu/x86/fpu_enable.inc | 9 +++- src/cpu/x86/sse_enable.inc | 9 +++- src/drivers/pc80/mc146818rtc_early.c | 11 +++++ .../emulation/qemu-i440fx/cache_as_ram.inc | 10 ++++ src/northbridge/intel/i5000/halt_second_bsp.S | 9 ++++ 21 files changed, 241 insertions(+), 6 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..8942a66 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failling to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting(like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_failboot.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h index 8a61d6e..b6df10b 100644 --- a/src/arch/x86/include/arch/cbfs.h +++ b/src/arch/x86/include/arch/cbfs.h @@ -45,4 +45,12 @@ static inline void call(unsigned long addr, unsigned long bist) { asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist)); } + +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline void call_cmos_stage(unsigned long addr, unsigned long bist, int normal) +{ + asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist),"b" (normal)); +} +#endif + #endif diff --git a/src/arch/x86/init/bootblock_failboot.c b/src/arch/x86/init/bootblock_failboot.c new file mode 100644 index 0000000..17e5ee3 --- /dev/null +++ b/src/arch/x86/init/bootblock_failboot.c @@ -0,0 +1,53 @@ +#include <bootblock_common.h> +#include <pc80/mc146818rtc.h> + +static const char *get_fallback(const char *stagelist) { + while (*stagelist) stagelist++; + return ++stagelist; +} + +static void main(unsigned long bist) +{ + unsigned long entry; + int boot_mode; + const char *default_filenames = "normal/romstage\0fallback/romstage"; + + if (boot_cpu()) { + bootblock_mainboard_init(); + +#if CONFIG_USE_OPTION_TABLE + sanitize_cmos(); +#endif + boot_mode = last_boot_normal(); + } else { + + /* Questionable single byte read from CMOS. + * Do not add any other CMOS access in the + * bootblock for AP CPUs. + */ + boot_mode = last_boot_normal(); + } + + char *filenames = (char *)walkcbfs("coreboot-stages"); + if (!filenames) { + filenames = default_filenames; + } + char *normal_candidate = filenames; + + if (boot_mode) + entry = findstage(normal_candidate); + else + entry = findstage(get_fallback(normal_candidate)); + + /* reset nvram to fallback */ + set_boot_fallback(); + + if (entry) call_cmos_stage(entry, bist, boot_mode); + + /* run fallback if normal can't be found */ + entry = findstage(get_fallback(normal_candidate)); + if (entry) call_cmos_stage(entry, bist, boot_mode); + + /* duh. we're stuck */ + asm volatile ("1:\n\thlt\n\tjmp 1b\n\t"); +} diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc index c645a1e..780add6 100755 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ b/src/cpu/amd/agesa/cache_as_ram.inc @@ -57,7 +57,10 @@ cache_as_ram_setup: /* Save the BIST result */ cvtsi2sd %ebp, %xmm0 - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Not implemented for AGESA" +#endif /* for normal part %ebx already contain cpu_init_detected from fallback call */ /* Save the cpu_init_detected */ @@ -70,6 +73,10 @@ cache_as_ram_setup: /* Restore the BIST result */ cvtsd2si %xmm0, %edx +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Not implemented for AGESA" +#endif /* Restore the cpu_init_detected */ cvtsd2si %xmm1, %ebx diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7070cf9..c8d6177 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -45,6 +45,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* * For normal part %ebx already contain cpu_init_detected @@ -408,7 +412,10 @@ CAR_FAM10_ap_out: /* Restore the BIST result. */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp pushl %ebx /* Init detected. */ diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc index 6a107fe..28c3f16 100644 --- a/src/cpu/amd/geode_gx2/cache_as_ram.inc +++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc @@ -38,6 +38,11 @@ /** /***************************************************************************/ DCacheSetup: +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode GX2" + //movl %ebx, ??? +#endif /* Save the BIST result */ movl %eax, %ebx @@ -154,6 +159,12 @@ DCacheSetupGood: /* Restore the BIST result */ movl %ebx, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode GX2" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc index 45fd166..16a19e0 100644 --- a/src/cpu/amd/geode_lx/cache_as_ram.inc +++ b/src/cpu/amd/geode_lx/cache_as_ram.inc @@ -35,6 +35,11 @@ /** /***************************************************************************/ DCacheSetup: +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for Geode LX" + //movl %ebx, %??? +#endif /* Save the BIST result */ movl %eax, %ebx @@ -180,6 +185,12 @@ DCacheSetupGood: /* Restore the BIST result */ movl %ebx, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for Geode LX" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8..a3a9c29 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -32,6 +32,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %ebp +#endif CacheAsRam: /* Check whether the processor has HT capability. */ @@ -319,10 +323,15 @@ clear_fixed_var_mtrr_out: lout: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp pushl %eax /* BIST */ + // pushl %ebx /* nvram's boot_option */ ??? No ebp used after that... call main /* We don't need CAR from now on. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 8a845e9..954114f 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -35,6 +35,12 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available in src/cpu/intel/car/cache_as_ram_ht.inc" + //movl %ebx, %??? /* %esp and %ebx are used later... */ +#endif + cache_as_ram: post_code(0x20) @@ -343,6 +349,12 @@ no_msr_11e: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers for Geode src/cpu/intel/car/cache_as_ram_ht.inc" + //movl ??? , %ebx ??? +#endif + movl %esp, %ebp pushl %eax diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 8601f46..7688a50 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -43,6 +43,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for haswell" + //movl %ebx, ??? /* %esp and %ebx are used later... */ +#endif cache_as_ram: post_code(0x20) @@ -170,6 +175,12 @@ clear_mtrrs: andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + #error "CONFIG_X86_BOOTBLOCK_FAILBOOT Fixme: Not enough registers available for haswell" + //movl ??? , %ebx ??? +#endif + /* Setup the stack. */ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index db0eaae..2893ea7 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -38,6 +38,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -174,6 +179,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif before_romstage: post_code(0x29) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 2652cb7..d9fb482 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -38,6 +38,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -174,6 +179,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif before_romstage: post_code(0x29) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 50fab35..ed25ef8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -30,6 +30,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %esp is used and %ebx not */ + /* Do not clobber %ebx */ +#endif cache_as_ram: post_code(0x20) @@ -138,6 +143,10 @@ clear_mtrrs: movl %ebp, %eax movl %esp, %ebp pushl %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* should I push %ebx in the stack? */ +#endif post_code(0x23) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b83..eea0b93 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -35,6 +35,10 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif CacheAsRam: @@ -204,6 +208,10 @@ testok: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* We need to set EBP? No need. */ movl %esp, %ebp diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index e4613bf..b7f90c2 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,6 +36,10 @@ _start: cli /* Save the BIST result */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif post_code(POST_RESET_VECTOR_CORRECT) @@ -114,6 +118,10 @@ _start: /* Restore BIST to %eax */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif /* Now that we are in protected mode jump to a 32 bit code segment. */ data32 ljmp $ROM_CODE_SEG, $__protected_start diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index f74e1b8..9299316 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -51,7 +51,10 @@ protected_start: __protected_start: /* Save the BIST value */ movl %eax, %ebp - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif post_code(POST_ENTER_PROTECTED_MODE) movw $ROM_DATA_SEG, %ax @@ -63,4 +66,7 @@ __protected_start: /* Restore the BIST value to %eax */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/cpu/x86/fpu_enable.inc b/src/cpu/x86/fpu_enable.inc index c08e8a0..2d43b34 100644 --- a/src/cpu/x86/fpu_enable.inc +++ b/src/cpu/x86/fpu_enable.inc @@ -20,7 +20,10 @@ __fpu_start: /* Preserve BIST. */ movl %eax, %ebp - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* * Clear the CR0[2] bit (the "Emulation" flag, EM). * @@ -37,3 +40,7 @@ __fpu_start: /* Restore BIST. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc index 09dea02..1e1ed49 100644 --- a/src/cpu/x86/sse_enable.inc +++ b/src/cpu/x86/sse_enable.inc @@ -19,6 +19,10 @@ /* Preserve BIST. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + movl %ebx, %esp +#endif /* Enable SSE instructions. */ movl %cr4, %eax @@ -27,4 +31,7 @@ /* Restore BIST. */ movl %ebp, %eax - +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + movl %esp, %ebx +#endif diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..df8215a 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,17 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline void set_boot_fallback(void) +{ + unsigned char byte; + byte = cmos_read(RTC_BOOT_BYTE); + /* set it back to Fallback */ + byte &= ~(1<<0); + cmos_write(byte, RTC_BOOT_BYTE); +} +#endif + static inline int do_normal_boot(void) { unsigned char byte; diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 11ac91d..deb7b65 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -31,6 +31,11 @@ /* Save the BIST result. */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #warning "CONFIG_X86_BOOTBLOCK_FAILBOOT is used, the build may fail" + movl %ebx, %esp +#endif cache_as_ram: post_code(0x20) @@ -49,6 +54,11 @@ cache_as_ram: /* Restore the BIST result. */ movl %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + #warning "CONFIG_X86_BOOTBLOCK_FAILBOOT is used, the build may fail" + movl %esp, %ebx +#endif movl %esp, %ebp pushl %eax diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S index 041807e..f21e23d 100644 --- a/src/northbridge/intel/i5000/halt_second_bsp.S +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -1,6 +1,11 @@ /* Save BIST result */ movl %eax, %ebp +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Preserve the nvram's boot_option parameter */ + /* Nothing to do, since %ebx is not used */ + /* Do not clobber %ebx */ +#endif /* check if SPAD0 is cleared. If yes, it means this was a hard reset */ movl $0x800080d0, %eax @@ -56,3 +61,7 @@ loop: hlt /* Restore BIST */ mov %ebp, %eax +#if CONFIG_X86_BOOTBLOCK_FAILBOOT + /* Restore nvram's saved boot_option parameter */ + /* Nothing to do, since %ebx is not used */ +#endif

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New patch to review for coreboot: b6c40a9 i82801gx: Enable CONFIG_SPI_FLASH
by Denis Carikli June 26, 2013

June 26, 2013

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3550 -gerrit commit b6c40a933c89e8099e8e8c9db2fbebcfaa812569 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Jun 26 19:55:21 2013 +0200 i82801gx: Enable CONFIG_SPI_FLASH Change-Id: I306d79697c730ba03730590554aeb540c0a1b5ed Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/southbridge/intel/i82801gx/Kconfig | 1 + src/southbridge/intel/i82801gx/Makefile.inc | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index a991f60..716c5c7 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -24,6 +24,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER + select SPI_FLASH if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index c21b684..ad9a66e 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -33,6 +33,8 @@ ramstage-y += usb_ehci.c ramstage-y += reset.c ramstage-y += watchdog.c +ramstage-y += ../bd82x6x/spi.c + ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

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