coreboot-gerrit June 2013

coreboot-gerrit@coreboot.org

1 participants
744 discussions

New patch to review for coreboot: 88a3ece cpu/amd/agesa/s3_resume.c: Remove unused variable
by Paul Menzel 30 Jun '13

30 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3575 -gerrit commit 88a3ece87a407a718c55ec5b302596336cab6365 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jun 29 19:55:34 2013 +0200 cpu/amd/agesa/s3_resume.c: Remove unused variable Change-Id: Ic0a41499e53a48ceec5c52dec155b7d6759bf2f0 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/s3_resume.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 6ba9212..16d5383 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -240,7 +240,6 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 data; u32 nvram_pos; struct spi_flash *flash; @@ -270,11 +269,10 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) nvram_pos = 0; flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); - for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { - data = *(u32 *) (Data + nvram_pos); - flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); - } - flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); + for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) + flash->write(flash, nvram_pos + pos + sizeof(DataSize), CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); + + flash->write(flash, nvram_pos + pos + sizeof(DataSize), DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos)); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi);

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Patch set updated for coreboot: f3c57b9 am335x: Fix the address of the pinmux registers.
by Paul Menzel 30 Jun '13

30 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3574 -gerrit commit f3c57b9dd63cb15ff56e2ecc9f0828b8804c6d2a Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 22:55:15 2013 -0700 am335x: Fix the address of the pinmux registers. The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the control module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/pinmux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 69c1459..1b488e8 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -54,7 +54,7 @@ void am335x_pinmux_mii1(void); void am335x_pinmux_nand(void); -#define AM335X_PINMUX_REG_ADDR 0x44e10000 +#define AM335X_PINMUX_REG_ADDR 0x44e10800 struct am335x_pinmux_regs { uint32_t gpmc_ad0;

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Patch set updated for coreboot: ce93a9b am335x: Implement support for the Uart.
by Paul Menzel 30 Jun '13

30 Jun '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3490 -gerrit commit ce93a9b706d8401047a212057647b6efa01ae530 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Jun 11 21:58:18 2013 -0400 am335x: Implement support for the Uart. This patch was started by Dave Hendricks and implements the procedure for setting up the UART as described in the manual. Some unused code was removed. Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/uart.c | 175 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 125 insertions(+), 50 deletions(-) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index fdf5c05..87ee86a 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,9 +1,5 @@ /* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * based on drivers/serial/s3c64xx.c + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ +#include <config.h> #include <types.h> #include <uart.h> #include <arch/io.h> @@ -29,9 +25,14 @@ #include <cpu/ti/am335x/uart.h> -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) +#define EFR_ENHANCED_EN (1 << 4) +#define FCR_FIFO_EN (1 << 0) +#define MCR_TCR_TLR (1 << 6) +#define SYSC_SOFTRESET (1 << 1) +#define SYSS_RESETDONE (1 << 0) + +#define LSR_RXFIFOE (1 << 0) +#define LSR_TXFIFOE (1 << 5) /* * Initialise the serial port with the given baudrate. The settings @@ -39,28 +40,116 @@ */ static void am335x_uart_init_dev(void) { + struct am335x_uart *uart = (struct am335x_uart *) + CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + uint16_t lcr_orig, efr_orig, mcr_orig; + /* FIXME: implement this * ref: section 19.4.1.1.1 for reset * ref: section 19.4.1.1.2 for FIFO, skip DMA * ref: section 19.4.1.1.3 for baud rate, skip * interrupts and protocol stuff. - * */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - - /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); - - serial_setbrg_dev(); -#endif + */ + + /* reset the UART */ + write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + while (!(read16(&uart->syss) & SYSS_RESETDONE)) + ; + + /* 1. switch to register config mode B */ + lcr_orig = read16(&uart->lcr); + write16(0xbf, &uart->lcr); + + /* + * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must + * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. + */ + efr_orig = read16(&uart->efr); + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 3. Switch to register config mode A */ + write16(0x80, &uart->lcr); + + /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ + mcr_orig = read16(&uart->mcr); + write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + + /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ + write16(FCR_FIFO_EN, &uart->fcr); + + /* 6. Switch to configuration mode B */ + write16(0xbf, &uart->lcr); + /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ + + /* 9. Restore original EFR value */ + write16(efr_orig, &uart->efr); + + /* 10. Switch to config mode A */ + write16(0x80, &uart->lcr); + + /* 11. Restore original MCR value */ + write16(mcr_orig, &uart->mcr); + + /* 12. Restore original LCR value */ + write16(lcr_orig, &uart->lcr); + + /* Protocol, baud rate and interrupt settings */ + + /* 1. Disable UART access to DLL and DLH registers */ + write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + + /* 2. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 3. Enable access to IER[7:4] */ + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 4. Switch to operational mode */ + write16(0x0, &uart->lcr); + + /* 5. Clear IER */ + write16(0x0, &uart->ier); + + /* 6. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 7. Set dll and dlh to the desired values (table 19-25) */ + if (CONFIG_CONSOLE_SERIAL_9600) { + write16(0x01, &uart->dlh); + write16(0x38, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_19200) { + write16(0x00, &uart->dlh); + write16(0x9c, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_38400) { + write16(0x00, &uart->dlh); + write16(0x4e, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_57600) { + write16(0x00, &uart->dlh); + write16(0x34, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_115200) { + write16(0x00, &uart->dlh); + write16(0x1a, &uart->dll); + } else { + /* Unrecognized baud rate? */ + } + + /* 8. Switch to operational mode to access ier */ + write16(0x0, &uart->lcr); + + /* 9. Clear ier to disable all interrupts */ + write16(0x0, &uart->ier); + + /* 10. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 11. Restore efr */ + write16(efr_orig, &uart->efr); + + /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ + write16(0x3, &uart->lcr); + + /* 13. Load the new UART mode */ + write16(0x0, &uart->mdr1); } /* @@ -70,20 +159,12 @@ static void am335x_uart_init_dev(void) */ static unsigned char am335x_uart_rx_byte(void) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) - return 0; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - return readb(&uart->urxh) & 0xff; -#endif - return 0xaa; + while (!(read16(&uart->lsr) & LSR_RXFIFOE)); + + return read8(&uart->rhr); } /* @@ -91,18 +172,12 @@ static unsigned char am335x_uart_rx_byte(void) */ static void am335x_uart_tx_byte(unsigned char data) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) - return; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - writeb(data, &uart->utxh); -#endif + while (!(read16(&uart->lsr) & LSR_TXFIFOE)); + + return write8(data, &uart->thr); } uint32_t uartmem_getbaseaddr(void)

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New patch to review for coreboot: 6ebf6b4 am335x: Fix the address of the pinmux registers.
by Gabe Black 30 Jun '13

30 Jun '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3574 -gerrit commit 6ebf6b43eae273555db13a7684dae82d616a76d4 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 22:55:15 2013 -0700 am335x: Fix the address of the pinmux registers. The pinmux register data structure describes a subset of the control module registers, but the address which pointed to the base of the pinmux registers was actually being set to the beginning of all the cotrnol module registers, not just those having to do with the pinmux. With this address fixed, the UART now works on the beaglebone black. Change-Id: I7c99b6f37d7da359af074127cd0c1a86fda2d9a0 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/pinmux.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/ti/am335x/pinmux.h b/src/cpu/ti/am335x/pinmux.h index 69c1459..1b488e8 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/cpu/ti/am335x/pinmux.h @@ -54,7 +54,7 @@ void am335x_pinmux_mii1(void); void am335x_pinmux_nand(void); -#define AM335X_PINMUX_REG_ADDR 0x44e10000 +#define AM335X_PINMUX_REG_ADDR 0x44e10800 struct am335x_pinmux_regs { uint32_t gpmc_ad0;

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New patch to review for coreboot: 1b94072 beaglebone: Enable the clocks and pins for the configured UART.
by Gabe Black 30 Jun '13

30 Jun '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3573 -gerrit commit 1b940726e0b8eff3d90e2c9a2e7724f0495cdfc3 Author: Gabe Black <gabeblack(a)chromium.org> Date: Sat Jun 29 23:20:14 2013 -0700 beaglebone: Enable the clocks and pins for the configured UART. Set up the pinmux to enable the pins and the clocks for whichever UART is currently configured. Change-Id: Iac13f16d9d84320555b99734ea83eafd0a2803fe Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/ti/beaglebone/bootblock.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index fbe73ea..6c7d132 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -21,10 +21,13 @@ #include <types.h> #include <uart.h> #include <console/console.h> +#include <cpu/ti/am335x/pinmux.h> void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + void *uart_clock_ctrl = NULL; + /* Enable the GPIO module */ writel((0x2 << 0) | (1 << 18), (uint32_t *)(0x44e00000 + 0xac)); @@ -38,6 +41,29 @@ void bootblock_mainboard_init(void) clrbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0xf << 21); setbits_le32((uint32_t *)(0x4804c000 + 0x13c), 0x5 << 21); + /* Set up the UART we're going to use */ + if (CONFIG_CONSOLE_SERIAL_UART0) { + am335x_pinmux_uart0(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00400 + 0xb4); + } else if (CONFIG_CONSOLE_SERIAL_UART1) { + am335x_pinmux_uart1(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x6c); + } else if (CONFIG_CONSOLE_SERIAL_UART2) { + am335x_pinmux_uart2(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x70); + } else if (CONFIG_CONSOLE_SERIAL_UART3) { + am335x_pinmux_uart3(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x74); + } else if (CONFIG_CONSOLE_SERIAL_UART4) { + am335x_pinmux_uart4(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x78); + } else if (CONFIG_CONSOLE_SERIAL_UART5) { + am335x_pinmux_uart5(); + uart_clock_ctrl = (void *)(uintptr_t)(0x44e00000 + 0x38); + } + if (uart_clock_ctrl) + writel(0x2, uart_clock_ctrl); + /* Start monotonic timer */ //rtc_start();

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Patch set updated for coreboot: 4ca66de am335x: Implment support for the Uart.
by Gabe Black 30 Jun '13

30 Jun '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3490 -gerrit commit 4ca66de71133646b17d53991c614b841a9b66df7 Author: Gabe Black <gabeblack(a)chromium.org> Date: Tue Jun 11 21:58:18 2013 -0400 am335x: Implment support for the Uart. This patch was started by Dave Hendricks and implements the procedure for setting up the UART as described in the manual. Some unused code was removed. Change-Id: If26a424cac401ef3eafaec081147f41184fbcee9 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/ti/am335x/uart.c | 175 +++++++++++++++++++++++++++++++++-------------- 1 file changed, 125 insertions(+), 50 deletions(-) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index fdf5c05..87ee86a 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -1,9 +1,5 @@ /* - * (C) Copyright 2009 SAMSUNG Electronics - * Minkyu Kang <mk7.kang(a)samsung.com> - * Heungjun Kim <riverful.kim(a)samsung.com> - * - * based on drivers/serial/s3c64xx.c + * Copyright 2013 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * */ +#include <config.h> #include <types.h> #include <uart.h> #include <arch/io.h> @@ -29,9 +25,14 @@ #include <cpu/ti/am335x/uart.h> -#define RX_FIFO_COUNT_MASK 0xff -#define RX_FIFO_FULL_MASK (1 << 8) -#define TX_FIFO_FULL_MASK (1 << 24) +#define EFR_ENHANCED_EN (1 << 4) +#define FCR_FIFO_EN (1 << 0) +#define MCR_TCR_TLR (1 << 6) +#define SYSC_SOFTRESET (1 << 1) +#define SYSS_RESETDONE (1 << 0) + +#define LSR_RXFIFOE (1 << 0) +#define LSR_TXFIFOE (1 << 5) /* * Initialise the serial port with the given baudrate. The settings @@ -39,28 +40,116 @@ */ static void am335x_uart_init_dev(void) { + struct am335x_uart *uart = (struct am335x_uart *) + CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + uint16_t lcr_orig, efr_orig, mcr_orig; + /* FIXME: implement this * ref: section 19.4.1.1.1 for reset * ref: section 19.4.1.1.2 for FIFO, skip DMA * ref: section 19.4.1.1.3 for baud rate, skip * interrupts and protocol stuff. - * */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - // TODO initialize with correct peripheral id by base_port. - exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); - - /* enable FIFOs */ - writel(0x1, &uart->ufcon); - writel(0, &uart->umcon); - /* 8N1 */ - writel(0x3, &uart->ulcon); - /* No interrupts, no DMA, pure polling */ - writel(0x245, &uart->ucon); - - serial_setbrg_dev(); -#endif + */ + + /* reset the UART */ + write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc); + while (!(read16(&uart->syss) & SYSS_RESETDONE)) + ; + + /* 1. switch to register config mode B */ + lcr_orig = read16(&uart->lcr); + write16(0xbf, &uart->lcr); + + /* + * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must + * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1. + */ + efr_orig = read16(&uart->efr); + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 3. Switch to register config mode A */ + write16(0x80, &uart->lcr); + + /* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */ + mcr_orig = read16(&uart->mcr); + write16(mcr_orig | MCR_TCR_TLR, &uart->mcr); + + /* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */ + write16(FCR_FIFO_EN, &uart->fcr); + + /* 6. Switch to configuration mode B */ + write16(0xbf, &uart->lcr); + /* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */ + + /* 9. Restore original EFR value */ + write16(efr_orig, &uart->efr); + + /* 10. Switch to config mode A */ + write16(0x80, &uart->lcr); + + /* 11. Restore original MCR value */ + write16(mcr_orig, &uart->mcr); + + /* 12. Restore original LCR value */ + write16(lcr_orig, &uart->lcr); + + /* Protocol, baud rate and interrupt settings */ + + /* 1. Disable UART access to DLL and DLH registers */ + write16(read16(&uart->mdr1) | 0x7, &uart->mdr1); + + /* 2. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 3. Enable access to IER[7:4] */ + write16(efr_orig | EFR_ENHANCED_EN, &uart->efr); + + /* 4. Switch to operational mode */ + write16(0x0, &uart->lcr); + + /* 5. Clear IER */ + write16(0x0, &uart->ier); + + /* 6. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 7. Set dll and dlh to the desired values (table 19-25) */ + if (CONFIG_CONSOLE_SERIAL_9600) { + write16(0x01, &uart->dlh); + write16(0x38, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_19200) { + write16(0x00, &uart->dlh); + write16(0x9c, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_38400) { + write16(0x00, &uart->dlh); + write16(0x4e, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_57600) { + write16(0x00, &uart->dlh); + write16(0x34, &uart->dll); + } else if (CONFIG_CONSOLE_SERIAL_115200) { + write16(0x00, &uart->dlh); + write16(0x1a, &uart->dll); + } else { + /* Unrecognized baud rate? */ + } + + /* 8. Switch to operational mode to access ier */ + write16(0x0, &uart->lcr); + + /* 9. Clear ier to disable all interrupts */ + write16(0x0, &uart->ier); + + /* 10. Switch to config mode B */ + write16(0xbf, &uart->lcr); + + /* 11. Restore efr */ + write16(efr_orig, &uart->efr); + + /* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */ + write16(0x3, &uart->lcr); + + /* 13. Load the new UART mode */ + write16(0x0, &uart->mdr1); } /* @@ -70,20 +159,12 @@ static void am335x_uart_init_dev(void) */ static unsigned char am335x_uart_rx_byte(void) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for character to arrive */ - while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | - RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) - return 0; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - return readb(&uart->urxh) & 0xff; -#endif - return 0xaa; + while (!(read16(&uart->lsr) & LSR_RXFIFOE)); + + return read8(&uart->rhr); } /* @@ -91,18 +172,12 @@ static unsigned char am335x_uart_rx_byte(void) */ static void am335x_uart_tx_byte(unsigned char data) { - /* FIXME: stub */ -#if 0 - struct s5p_uart *uart = (struct s5p_uart *)base_port; - - /* wait for room in the tx FIFO */ - while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) - return; - } + struct am335x_uart *uart = + (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - writeb(data, &uart->utxh); -#endif + while (!(read16(&uart->lsr) & LSR_TXFIFOE)); + + return write8(data, &uart->thr); } uint32_t uartmem_getbaseaddr(void)

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Patch set updated for coreboot: c3ffab4 cbmem: Fix makefile
by Stefan Tauner 30 Jun '13

30 Jun '13

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3548 -gerrit commit c3ffab4e87ee8474b267f7aefcfb5887e5e01e8e Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sun Jun 30 01:05:30 2013 +0200 cbmem: Fix makefile The .dependencies rule did not use the CPPFLAGS variable which led to funny behavior: a spurious termination message the first time (after checkout/make distclean) one executes make. Afterwards the (wrongly) empty .dependencies file hides the problem and the binary is created anyway. $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make make: Nothing to be done for `all'. $ make clean rm -f cbmem *.o *~ $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem $ make distclean rm -f cbmem *.o *~ rm -f .dependencies $ make cbmem.c:37:34: fatal error: boot/coreboot_tables.h: No such file or directory compilation terminated. cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cc cbmem.o -o cbmem I fixed that by adding the CPPFLAGS variable to the .dependencies recipe, just like Stefan Reinauer did in Chromium (Ia9d2e10a3ef122f30d681d16c2291eb108ead835), hence the split sign-off for this tiny change. :) Change-Id: Icd11b146ad762cbdf9774630b950f70e1253a072 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- util/cbmem/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index c93863a..51ee927 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -37,7 +37,7 @@ distclean: clean rm -f .dependencies .dependencies: - @$(CC) $(CFLAGS) -MM *.c > .dependencies + @$(CC) $(CFLAGS) $(CPPFLAGS) -MM *.c > .dependencies .PHONY: all clean distclean

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Patch set updated for coreboot: 0d29d46 Add a new and safer bootblock implementation.
by Denis Carikli 30 Jun '13

30 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit 0d29d467883c52c2ebf3a7db467bd8a2cddac3e2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add a new and safer bootblock implementation. The drawback is that it requires cooperation from something that is run after coreboot (like the OS or the payload). To understand how to use it, refer to the Kconfig help of that option. Thanks a lot to kmalkki on #coreboot Freenode IRC channel for pointers on how to simplify the implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 +++++++++++++ src/drivers/pc80/mc146818rtc_early.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..3bb6547 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_normal.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..4cda097 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,33 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int do_normal_boot(void) +{ + unsigned char old_byte, write_byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* There are no impossible values, no checksums so just + * trust whatever value we have in the the cmos, + * but clear the fallback bit. + */ + write_byte = cmos_read(RTC_BOOT_BYTE); + write_byte &= 0x0c; + cmos_write(write_byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + write_byte = old_byte = cmos_read(RTC_BOOT_BYTE); + + /* Reset boot_option to Fallback */ + write_byte &= ~(1<<0); + + /* Save the boot byte */ + cmos_write(write_byte, RTC_BOOT_BYTE); + + return (old_byte & (1<<0)); +} +#else static inline int do_normal_boot(void) { unsigned char byte; @@ -91,6 +118,7 @@ static inline int do_normal_boot(void) return (byte & (1<<1)); } +#endif unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) {

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Patch set updated for coreboot: cce1321 Add a new and safer bootblock implementation.
by Denis Carikli 30 Jun '13

30 Jun '13

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3549 -gerrit commit cce13217ffd5580bc9dfe3396f17f155cbb5f291 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 21 23:32:19 2013 +0200 Add a new and safer bootblock implementation. The drawback is that it requires cooperation from something that is run after coreboot (like the OS or the payload). To understand how to use it, refer to the Kconfig help of that option. Thanks a lot to kmalkki on #coreboot Freenode IRC channel for pointers on how to simplify the implementation. Change-Id: I1109c49c7c84461bb056b36ee5d07391c2392176 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/arch/x86/Kconfig | 13 +++++++++++++ src/drivers/pc80/mc146818rtc_early.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 69cdc8a..3bb6547 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -54,12 +54,25 @@ config X86_BOOTBLOCK_SIMPLE config X86_BOOTBLOCK_NORMAL bool "Switch to normal if CMOS says so" +config X86_BOOTBLOCK_FAILBOOT + bool "Switch to Fallback if it fails to boot" + help + Switch to Fallback after failing to boot. + Coreboot will reset boot_option to Fallback + as early as possible, If the user has + a Fallback and a Normal image in cbfs, + and wants to boot on the Normal image, + he must reset the boot_option to Normal + after successfully booting (like trough the OS + boot scripts that would run something like: + "nvramtool -w boot_option=Normal". endchoice config BOOTBLOCK_SOURCE string default "bootblock_simple.c" if X86_BOOTBLOCK_SIMPLE default "bootblock_normal.c" if X86_BOOTBLOCK_NORMAL + default "bootblock_normal.c" if X86_BOOTBLOCK_FAILBOOT config UPDATE_IMAGE bool "Update existing coreboot.rom image" diff --git a/src/drivers/pc80/mc146818rtc_early.c b/src/drivers/pc80/mc146818rtc_early.c index 0652f27..020c766 100644 --- a/src/drivers/pc80/mc146818rtc_early.c +++ b/src/drivers/pc80/mc146818rtc_early.c @@ -49,6 +49,33 @@ static inline int last_boot_normal(void) return (byte & (1 << 1)); } +#if CONFIG_X86_BOOTBLOCK_FAILBOOT +static inline int do_normal_boot(void) +{ + unsigned char old_byte, write_byte; + + if (cmos_error() || !cmos_chksum_valid()) { + /* There are no impossible values, no checksums so just + * trust whatever value we have in the the cmos, + * but clear the fallback bit. + */ + write_byte = cmos_read(RTC_BOOT_BYTE); + write_byte &= 0x0c; + cmos_write(write_byte, RTC_BOOT_BYTE); + } + + /* The RTC_BOOT_BYTE is now o.k. see where to go. */ + write_byte = old_byte = cmos_read(RTC_BOOT_BYTE); + + /* Reset boot_option to Fallback */ + write_byte &= ~(1<<0); + + /* Save the boot byte */ + cmos_write(write_byte, RTC_BOOT_BYTE); + + return (old_byte & (1<<1)); +} +#else static inline int do_normal_boot(void) { unsigned char byte; @@ -91,6 +118,7 @@ static inline int do_normal_boot(void) return (byte & (1<<1)); } +#endif unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def) {

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Patch merged into coreboot/master: 0d8d482 AMD S3 resume: Add framwork to write bigger data
by gerrit＠coreboot.org 29 Jun '13

29 Jun '13

the following patch was just integrated into master: commit 0d8d482f6316885d7e553d9aeb538ce5bbd2fbba Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Sat Jun 8 10:25:06 2013 +0800 AMD S3 resume: Add framwork to write bigger data This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1] Some AMD south bridge can write bigger data when saving S3 info. In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size. AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig' and then can be overridden in the Kconfig for specific southbridges that support larger size. I have tested on AMD Parmer and Thatcher. We will release a new board whose south bridge can transfer more than 4 bytes each time. [1] http://review.coreboot.org/#/c/2306/ Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/3413 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3413 for details. -gerrit

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coreboot-gerrit June 2013