coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: f7142b4 Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2
by Paul Menzel 16 Apr '13

16 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3100 -gerrit commit f7142b464d4dfa6b0e41ea2f4139f0b9edc7ba9e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Mar 12 15:53:44 2013 +0100 Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2 Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same value, instead makes it clear, that the APIC ID is 2. [1] http://review.coreboot.org/853 Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df37ddc..7bcadc9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -52,7 +52,7 @@ static void pch_enable_apic(struct device *dev) pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; - *ioapic_data = (1 << 25); + *ioapic_data = (2 << 24); /* affirm full set of redirection table entries ("write once") */ *ioapic_index = 1; @@ -63,7 +63,7 @@ static void pch_enable_apic(struct device *dev) *ioapic_index = 0; reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) + if (reg32 != (2 << 24)) die("APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n");

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Patch set updated for coreboot: 6ca7687 cbmem: map_memory: Use length modifier `j` and cast for an `off_t` argument
by Paul Menzel 16 Apr '13

16 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3083 -gerrit commit 6ca7687466e28f8903c6ea8f8f65ebdcb04ee456 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 13 18:25:56 2013 +0200 cbmem: map_memory: Use length modifier `j` and cast for an `off_t` argument cbmem currently fails to build due to `-Werror` and the following warning. $ make cc -O2 -Wall -Werror -iquote ../../src/include -iquote ../../src/src/arch/x86 -c -o cbmem.o cbmem.c cbmem.c: In function ‘map_memory’: cbmem.c:87:2: error: format ‘%zx’ expects argument of type ‘size_t’, but argument 2 has type ‘off_t’ [-Werror=format] […] Casting the argument of type `off_t` to `intmax_t` and using the length modifier `j` $ man 3 printf […] j A following integer conversion corresponds to an intmax_t or uintmax_t argument. […] instead of `z` as suggested in [1] and confirmed by stefanct and segher in #coreboot on <irc.freenode.net>, gets rid of this warning and should work an 32-bit and 64-bit systems, as an `off_t` fits into `intmax_t`. [1] http://www.pixelbeat.org/programming/gcc/int_types/ Change-Id: I1360abbc47aa1662e1edfbe337cf7911695c532f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbmem/cbmem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f3f5add..3cebfef 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -84,7 +84,7 @@ static void *map_memory(u64 physical) /* Mapped memory must be aligned to page size */ p = physical & ~(page - 1); - debug("Mapping 1MB of physical memory at 0x%zx.\n", p); + debug("Mapping 1MB of physical memory at 0x%jx.\n", (intmax_t)p); v = mmap(NULL, MAP_BYTES, PROT_READ, MAP_SHARED, fd, p);

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Patch merged into coreboot/master: 8a2bc62 snow: Return 0 from get_recovery_mode_from_vbnv.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit 8a2bc62d4ce86689353021843b2377c8bb8fab56 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 20:36:01 2013 -0700 snow: Return 0 from get_recovery_mode_from_vbnv. This function isn't yet used for much, or perhaps anything, but where it appears in the code it's ored with other values. Since we're not actually retrieving anything, it might be best to return 0 so that the other values that are being ored in can be expressed and this function can stay dormant until it actually has something to do. Change-Id: I6edc222a5c2d00ece2ecfad5191a615331eeaf16 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3098 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 16 10:44:06 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Apr 16 06:38:55 2013, giving +2 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Tue Apr 16 10:13:04 2013, giving +1 See http://review.coreboot.org/3098 for details. -gerrit

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Patch merged into coreboot/master: 5cda308 snow: Report the state of the power button GPIO in the coreboot tables.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit 5cda30845c370d079a1ba2ff27628d76342da08d Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 19:59:10 2013 -0700 snow: Report the state of the power button GPIO in the coreboot tables. Change-Id: Ia7ce2b7342e186c565b92211e3ac15d80ce24b38 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3097 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 16 09:56:45 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Apr 16 06:35:50 2013, giving +2 See http://review.coreboot.org/3097 for details. -gerrit

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Patch merged into coreboot/master: e2b20f2 snow: Configure the power button as an input GPIO.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit e2b20f2d5ad6b061d7645528c45a4bfc4beb1f29 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 19:47:40 2013 -0700 snow: Configure the power button as an input GPIO. We need to read it to report its value to the payload. The kernel will reconfigure it as an external interrupt, but we'll make it a regular input for now. Change-Id: I019bd2c2731144d3b7bb53fad0c2c903874f616c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3096 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Build-Tested: build bot (Jenkins) at Tue Apr 16 10:20:22 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Apr 16 06:34:33 2013, giving +2 Reviewed-By: Paul Menzel <paulepanter(a)users.sourceforge.net> at Tue Apr 16 10:22:36 2013, giving +1 See http://review.coreboot.org/3096 for details. -gerrit

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Patch merged into coreboot/master: acb9d44 snow: Fix the name of some constants in romstage.c.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit acb9d4459973627f3b082dafb3f184a56a5d4219 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 19:45:10 2013 -0700 snow: Fix the name of some constants in romstage.c. These names were inherited from chromeos.c where they've already been fixed. Change-Id: I7ad57b979b7b8f42f6bd68d1ecf887caba3fa3f1 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3095 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 16 11:08:45 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Apr 16 06:33:50 2013, giving +2 See http://review.coreboot.org/3095 for details. -gerrit

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Patch set updated for coreboot: 44964af AMD Parmer: remove unused macros and turn off unused pcie port
by Siyuan Wang 16 Apr '13

16 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3099 -gerrit commit 44964afc4c389c130c5c1bf120b1d7de436481e0 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Apr 16 13:59:37 2013 +0800 AMD Parmer: remove unused macros and turn off unused pcie port 1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. This is based on >AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h< [1]. 2) Disable unused PCIE port in devicetree.cb. PCIE port 3 is not used in Parmer. This is based on item 3 of >AMD Thatcher: Fix PCIE link issues< [2]. [1] http://review.coreboot.org/#/c/3087/ [2] http://review.coreboot.org/#/c/3011/ Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/PlatformGnbPcie.c | 8 ++--- src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 40 ----------------------- src/mainboard/amd/parmer/devicetree.cb | 2 +- 3 files changed, 5 insertions(+), 45 deletions(-) diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 51dd9fd..f38ad13 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -27,13 +27,13 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), @@ -54,7 +54,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 */ + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), @@ -68,7 +68,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h index 3f14805..b3c69cf 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h @@ -24,46 +24,6 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 9bbbcf7..62b37e1 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 on end # PCIE SLOT0 x16 + device pci 3.0 off end device pci 4.0 on end # PCIE MINI0 device pci 5.0 on end # PCIE MINI1 device pci 6.0 on end # PCIE Slot1 x1

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Patch merged into coreboot/master: 88beef0 snow: Get rid of the oprom loaded GPIO.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit 88beef0a8e58c1b0404f2f91707fcdba7b113471 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 19:07:10 2013 -0700 snow: Get rid of the oprom loaded GPIO. ARM doesn't use option ROMs, so this value doesn't make sense. Change-Id: I1a0f0854e1dd4b9594ca0c147e590337520436da Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3094 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 16 07:56:27 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Apr 16 06:19:43 2013, giving +2 See http://review.coreboot.org/3094 for details. -gerrit

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New patch to review for coreboot: 36ae8c6 AMD Parmer: remov unused macros and turn off unused pcie port
by Siyuan Wang 16 Apr '13

16 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3099 -gerrit commit 36ae8c6d00410f61eeb3d7c964dff843634f52a4 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Tue Apr 16 13:59:37 2013 +0800 AMD Parmer: remov unused macros and turn off unused pcie port 1) The macros GNB_GPP_PORTx_PORT_PRESENT, GNB_GPP_PORTx_SPEED_MODE, GNB_GPP_PORTx_LINK_ASPM and GNB_GPP_PORTx_CHANNEL_TYPE are not used. This is based on >>AMD Thatcher: remove unused macros in PlatformGnbPcieComplex.h<< [1]. 2) Disable unused PCIE port in devicetree.cb. PCIE port 3 is not used in Parmer. This is based on item 3 of >>AMD Thatcher: Fix PCIE link issues<< [2]. [1] http://review.coreboot.org/#/c/3087/ [2] http://review.coreboot.org/#/c/3011/ Change-Id: Id6f00d5e77ce5133d9ef3db07f95ad03a59e061a Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/PlatformGnbPcie.c | 8 ++--- src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 40 ----------------------- src/mainboard/amd/parmer/devicetree.cb | 2 +- 3 files changed, 5 insertions(+), 45 deletions(-) diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 51dd9fd..f38ad13 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -27,13 +27,13 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE PCIe_PORT_DESCRIPTOR PortList [] = { - /* PCIe port, Lanes 8:23, PCI Device Number 2 */ + /* PCIe port, Lanes 8:23, PCI Device Number 2, PCIE SLOT0 x16 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 16:23, PCI Device Number 3 */ + /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23), @@ -54,7 +54,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 */ + /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ { 0, /* Descriptor flags */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), @@ -68,7 +68,7 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, - /* Initialize Port descriptor (PCIe port, Lanes ?, PCI Device Number 8, ...) */ + /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags !!!IMPORTANT!!! Terminate last element of array */ PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h index 3f14805..b3c69cf 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h @@ -24,46 +24,6 @@ #include "AGESA.h" #include "amdlib.h" -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - VOID OemCustomizeInitEarly ( IN OUT AMD_EARLY_PARAMS *InitEarly diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 9bbbcf7..62b37e1 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -33,7 +33,7 @@ chip northbridge/amd/agesa/family15tn/root_complex device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 on end # PCIE SLOT0 x16 + device pci 3.0 off end device pci 4.0 on end # PCIE MINI0 device pci 5.0 on end # PCIE MINI1 device pci 6.0 on end # PCIE Slot1 x1

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Patch merged into coreboot/master: a5d914e snow: Tidy up chromeos.c.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit a5d914e47c84bf66f7a91264f431cad3e8d54f2f Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 18:22:11 2013 -0700 snow: Tidy up chromeos.c. Got rid of a lot of #defines, some of which were converted to enums and the rest which were eliminated entirely. Got rid of cruft in get_developer_mode_switch and started using it for the dev mode GPIO. Instead of a macro defining how many GPIOs are expected, now the code actually counts the GPIOs as they're added. Change-Id: I97b6b9f52a72d1276eb3cf36d7f9dd7b335b4d19 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3093 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Tue Apr 16 07:32:08 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Tue Apr 16 06:19:11 2013, giving +2 See http://review.coreboot.org/3093 for details. -gerrit

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coreboot-gerrit April 2013