coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 6ceed09 libpayload: Don't sneak in compiler includes
by gerrit＠coreboot.org 18 Apr '13

18 Apr '13

the following patch was just integrated into master: commit 6ceed0929d1e11c9d8807427750bb6e4f14806fd Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 8 16:55:47 2013 -0700 libpayload: Don't sneak in compiler includes The way we got to include the compiler includes was kind of whacky. Instead of mixing in potentially problematic headers, make libpayload self-contained by adding some missing header files. Also clean up conflicting definitions of size_t throughout the tree. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I0ad1194de1a00b7133c5477c00eb167d63a2ee85 Reviewed-on: https://gerrit.chromium.org/gerrit/47608 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3058 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 17 22:09:40 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Apr 18 02:50:28 2013, giving +2 See http://review.coreboot.org/3058 for details. -gerrit

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Patch merged into coreboot/master: ba7ed4b AMD Fam14: Split out the AMD Fam14 DSDT
by gerrit＠coreboot.org 18 Apr '13

18 Apr '13

the following patch was just integrated into master: commit ba7ed4b6a1965692057710d61eacde14b2b58424 Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Fri Mar 29 13:33:39 2013 -0600 AMD Fam14: Split out the AMD Fam14 DSDT Same splitting as done on Persimmon and ASRock. Moving common DSDT code to common areas and adding new files as necessary. Boards updated are: Inagua Union-Station South-Station Change-Id: I8c9eea62996b41cea23a9c16858c4249197f6216 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3051 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 17 00:15:55 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Apr 18 02:49:49 2013, giving +2 See http://review.coreboot.org/3051 for details. -gerrit

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Patch merged into coreboot/master: 4b213a8 Intel i945: ACPI: Add _OSC method
by gerrit＠coreboot.org 18 Apr '13

18 Apr '13

the following patch was just integrated into master: commit 4b213a8d1fd02061c1e879ff98167bcb47f13bd2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Thu Mar 28 14:24:39 2013 +0100 Intel i945: ACPI: Add _OSC method Add the ACPI Operating System Capabilities Method and let the operation system control everything. Commit »AMD Fam14 DSDT: Add OSC method« (00a0e76b) [1] is used as a template. The Lenovo X60 [2] running the Parabola GNU/Linux distribution [3] is used for testing. Before that change: $ dmesg | egrep -e OSC -e ASPM [ 0.108036] pci_root PNP0A08:00: ACPI _OSC support notification failed, disabling PCIe ASPM [ 0.108040] pci_root PNP0A08:00: Unable to request _OSC control (_OSC support mask: 0x08) [ 0.118089] ACPI _OSC control for PCIe not granted, disabling ASPM [ 16.874569] e1000e 0000:01:00.0: Disabling ASPM L0s L1 With that change: $ dmesg | egrep -e OSC -e ASPM [ 0.107962] pci_root PNP0A08:00: Requesting ACPI _OSC control (0x1d) [ 0.108003] pci_root PNP0A08:00: ACPI _OSC control (0x1d) granted [ 0.111052] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' [ 17.537970] e1000e 0000:01:00.0: Disabling ASPM L0s L1 [1] http://review.coreboot.org/2738 [2] http://www.coreboot.org/Lenovo_x60x [3] https://parabolagnulinux.org/ Change-Id: I1caffa44eea447d553c01caaf431f2db241ea5ea Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2938 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 10 13:48:07 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Apr 18 02:48:01 2013, giving +2 See http://review.coreboot.org/2938 for details. -gerrit

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Patch merged into coreboot/master: ab34852 ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT
by gerrit＠coreboot.org 18 Apr '13

18 Apr '13

the following patch was just integrated into master: commit ab348528b58e987994eb783a7622404515a18cd8 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 8 16:43:25 2013 -0700 ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT This used to contain the path for the EC include files, but those files are included in coreboot now. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369 Reviewed-on: https://gerrit.chromium.org/gerrit/47606 Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/3057 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 17 21:43:39 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Apr 18 02:47:22 2013, giving +2 See http://review.coreboot.org/3057 for details. -gerrit

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New patch to review for coreboot: 30ce0db AMD/SB800: Define the GPP PCIe lane distribution
by Dave Frodin 18 Apr '13

18 Apr '13

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3104 -gerrit commit 30ce0db66c861bdfc85ab9af8c7c21280764fe48 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Apr 17 18:21:09 2013 -0600 AMD/SB800: Define the GPP PCIe lane distribution Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports. This fix was verified by openvoid on a AsRock E350M1 motherboard. Change-Id: I0116c5f518e0d000be609013446e53da4112f586 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/southbridge/amd/cimx/sb800/late.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index cfdf9f2..74b2d08 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -368,13 +368,13 @@ static void sb800_enable(device_t dev) /* the first sb800 device */ switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ case GPP_CFGMODE_X2200: - abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ + abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ break; case GPP_CFGMODE_X2110: - abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ + abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ break; case GPP_CFGMODE_X1111: - abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ + abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ break; case GPP_CFGMODE_X4000: default:

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Patch merged into coreboot/master: 1fb11d1 armv7/exynos5250: Deprecate sdelay in favor of udelay
by gerrit＠coreboot.org 17 Apr '13

17 Apr '13

the following patch was just integrated into master: commit 1fb11d105b4cc0d424884a08814f65e73d36504a Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 15:11:05 2013 -0700 armv7/exynos5250: Deprecate sdelay in favor of udelay This gets rid of the clock-tick based sdelay in favor of udelay(). udelay() is more consistent and easier to work with, and this allows us to carry one less variation of timers (and headers and sources...). Every 1 unit in the sdelay() argument was assumed to cause a delay of 2 clock ticks (@1.7GHz). So the conversion factor is roughly: sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6) = udelay((N * 2) / (1.7 * 10^3)) The sdelay() periods used were: sdelay(100) --> udelay(1) sdelay(0x10000) --> udelay(78) (rounded up to udelay(100)) There was one instance of sdelay(10000), which looked like sort of a typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should approximate to about 12us, so we'll stick with that for now and leave a note. Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3079 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Apr 16 19:43:32 2013, giving +1 Reviewed-By: David Hendricks <dhendrix(a)chromium.org> at Wed Apr 17 00:19:13 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Apr 17 23:06:40 2013, giving +2 See http://review.coreboot.org/3079 for details. -gerrit

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Patch set updated for coreboot: 136770e libpayload: Don't sneak in compiler includes
by Stefan Reinauer 17 Apr '13

17 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3058 -gerrit commit 136770e03c77eba07bf4b8f39c018e0b51b217b9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 8 16:55:47 2013 -0700 libpayload: Don't sneak in compiler includes The way we got to include the compiler includes was kind of whacky. Instead of mixing in potentially problematic headers, make libpayload self-contained by adding some missing header files. Also clean up conflicting definitions of size_t throughout the tree. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I0ad1194de1a00b7133c5477c00eb167d63a2ee85 Reviewed-on: https://gerrit.chromium.org/gerrit/47608 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/Makefile.inc | 4 +--- payloads/libpayload/include/armv7/arch/types.h | 3 --- payloads/libpayload/include/stdarg.h | 13 +++++++++++++ payloads/libpayload/include/stddef.h | 11 +++++++++++ payloads/libpayload/include/unistd.h | 2 -- payloads/libpayload/include/x86/arch/types.h | 3 --- 6 files changed, 25 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 9e6dc75..7f8889e 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -53,9 +53,7 @@ subdirs-$(CONFIG_CURSES) += curses subdirs-$(CONFIG_CBFS) += libcbfs subdirs-$(CONFIG_LZMA) += liblzma -CC_INCLUDE = $(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include - -INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -I$(CC_INCLUDE) +INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs diff --git a/payloads/libpayload/include/armv7/arch/types.h b/payloads/libpayload/include/armv7/arch/types.h index bb40257..1bd815b 100644 --- a/payloads/libpayload/include/armv7/arch/types.h +++ b/payloads/libpayload/include/armv7/arch/types.h @@ -53,9 +53,6 @@ typedef signed long long s64; typedef long time_t; typedef long suseconds_t; -typedef unsigned long size_t; -typedef long ssize_t; - #ifndef NULL #define NULL ((void *)0) #endif diff --git a/payloads/libpayload/include/stdarg.h b/payloads/libpayload/include/stdarg.h index 077645f..1d7ac05 100644 --- a/payloads/libpayload/include/stdarg.h +++ b/payloads/libpayload/include/stdarg.h @@ -31,7 +31,20 @@ #define _LIBPAYLOAD_STDARG_H #include <stddef.h> + +/* With GCC we use -nostdinc -ffreestanding to keep out system includes. + * Unfortunately this also gets us rid of the _compiler_ includes, like + * stdarg.h. To work around the issue, we define varargs directly here. + * On LLVM we can still just include stdarg.h. + */ +#ifdef __GNUC__ +#define va_start(v,l) __builtin_va_start(v,l) +#define va_end(v) __builtin_va_end(v) +#define va_arg(v,l) __builtin_va_arg(v,l) +typedef __builtin_va_list va_list; +#else #include_next <stdarg.h> +#endif /** * @defgroup vprintf Varargs print functions diff --git a/payloads/libpayload/include/stddef.h b/payloads/libpayload/include/stddef.h new file mode 100644 index 0000000..91ae782 --- /dev/null +++ b/payloads/libpayload/include/stddef.h @@ -0,0 +1,11 @@ + +#include <arch/types.h> + +#ifndef __SIZE_TYPE__ +#define __SIZE_TYPE__ unsigned long +#endif +typedef __SIZE_TYPE__ size_t; +typedef long ssize_t; + +#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *) 0)->MEMBER) + diff --git a/payloads/libpayload/include/unistd.h b/payloads/libpayload/include/unistd.h index 1e39aeb..6b4dcf4 100644 --- a/payloads/libpayload/include/unistd.h +++ b/payloads/libpayload/include/unistd.h @@ -32,8 +32,6 @@ #include <stddef.h> -typedef ptrdiff_t ssize_t; - int getpagesize(void); #endif diff --git a/payloads/libpayload/include/x86/arch/types.h b/payloads/libpayload/include/x86/arch/types.h index bb40257..1bd815b 100644 --- a/payloads/libpayload/include/x86/arch/types.h +++ b/payloads/libpayload/include/x86/arch/types.h @@ -53,9 +53,6 @@ typedef signed long long s64; typedef long time_t; typedef long suseconds_t; -typedef unsigned long size_t; -typedef long ssize_t; - #ifndef NULL #define NULL ((void *)0) #endif

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Patch set updated for coreboot: 1e9fa64 ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT
by Stefan Reinauer 17 Apr '13

17 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3057 -gerrit commit 1e9fa64463dbeb7fcf15975bcd4cc8c062a1f92c Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 8 16:43:25 2013 -0700 ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOT This used to contain the path for the EC include files, but those files are included in coreboot now. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369 Reviewed-on: https://gerrit.chromium.org/gerrit/47606 Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/ec/google/chromeec/Kconfig | 7 ------- src/ec/google/chromeec/Makefile.inc | 2 -- 2 files changed, 9 deletions(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index c3f0499..773f294 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -3,13 +3,6 @@ config EC_GOOGLE_CHROMEEC help Google's Chrome EC -config EC_GOOGLE_API_ROOT - depends on EC_GOOGLE_CHROMEEC - string "Path to the EC API include file" - default "/usr/include" - help - Path to the ec API file (ec/ec_commands.h). - config EC_GOOGLE_CHROMEEC_I2C depends on EC_GOOGLE_CHROMEEC && !EC_GOOGLE_CHROMEEC_LPC bool diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 5bc9268..922c1fe 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -7,5 +7,3 @@ smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-y += ec.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c - -CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT))

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Patch set updated for coreboot: f0e347f Rename mainboard vendor Google to GOOGLE
by Stefan Reinauer 17 Apr '13

17 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3056 -gerrit commit f0e347f0cc684746fec90e6e37541655b1a38ab6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 8 16:48:10 2013 -0700 Rename mainboard vendor Google to GOOGLE This is what was built into all our products, so make sure that no utilities get confused by a difference in spelling. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Icef8a5a6f976f9f87cb7e065284541ecaa213c1b Reviewed-on: https://gerrit.chromium.org/gerrit/47607 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/google/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index e389b59..4061f17 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -47,6 +47,6 @@ source "src/mainboard/google/stout/Kconfig" config MAINBOARD_VENDOR string - default "Google" + default "GOOGLE" endif # VENDOR_GOOGLE

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Patch merged into coreboot/master: 1a0b5e1 google/snow: enable 32KHz sleep clock
by gerrit＠coreboot.org 17 Apr '13

17 Apr '13

the following patch was just integrated into master: commit 1a0b5e1c0594cb1bfe5094ad0c6eb183c9f3a593 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 11 12:58:25 2013 -0700 google/snow: enable 32KHz sleep clock Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3075 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 17 07:06:07 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Wed Apr 17 17:56:04 2013, giving +2 See http://review.coreboot.org/3075 for details. -gerrit

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coreboot-gerrit April 2013