coreboot-gerrit April 2013

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Patch set updated for coreboot: c960192 GOOGLE/SNOW: get graphics working
by Ronald G. Minnich 19 Apr '13

19 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit c96019261665d2212a660b73132ef6ee1bb33475 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working draft patch, needs cleanup, but we've got a blue screen of life. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 76 ++++++++++++++++++++++++----- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 6 +++ src/cpu/samsung/exynos5250/cpu.c | 1 + src/mainboard/google/snow/ramstage.c | 7 ++- 4 files changed, 76 insertions(+), 14 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 11d666b..1bb97a7 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,24 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* useful information. Here is the rough outline of how we bring up the display. + *1. Upon power-on Sink generates a hot plug detection pulse thru HPD + *2. Source determines video mode by reading DPCD receiver capability field (DPCD 00000h to + * 0000Dh) including eDP CP capability register (DPCD 0000Dh) + *3. Sink replies DPCD receiver capability field. + *4. Source starts EDID read thru I2C-over-AUX + *5. Sink replies EDID thru I2C-over-AUX + *6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication method + * to use and writes DPCD link configuration field (DPCD 00100h to 0010Ah) including eDP + * configuration set (DPCD 0010Ah). + *7. Source starts link training. Sink does clock recovery and equalization + *8. Source reads DPCD link status field (DPCD 00200h to 0020Bh) + *9. Sink replies DPCD link status field. If main link is not stable, Source repeats Step 7. + *10. Source sends MSA (Main Stream Attribute) data. Sink extracts video parameters and + * recovers stream clock. + *11. Source sends video data + */ /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -83,7 +102,6 @@ int lcd_line_length; int lcd_color_fg; int lcd_color_bg; -void *lcd_base; /* Start of framebuffer memory */ void *lcd_console_address; /* Start of console buffer */ short console_col; @@ -127,38 +145,51 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = + struct exynos5_fimd *fimd = //14400000 samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = + struct exynos5_disp_ctrl *disp_ctrl = //14420000 samsung_get_base_disp_ctrl(); + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); - writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)lcdbase, &fimd->vidw00add0b0); + writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); - writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)fbsize, &fimd->vidw00add1b0); + writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -166,6 +197,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -192,7 +224,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -207,16 +239,17 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %d microseconds waiting\n", timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -256,7 +289,7 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - + /* let's not do this and see if it gets better */ if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -409,23 +442,25 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: start\n", __func__); /* Stop Video */ clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "un"); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -449,6 +484,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -471,21 +509,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -498,6 +542,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -534,12 +580,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -554,7 +602,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..49fe1cb 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,7 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -351,11 +352,13 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: sys_ctl_1 is %p\n", __func__, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); writel(reg, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); + printk(BIOS_SPEW, "%s: sys_ctl_1 is %08x, DET_STA is 0x%x\n", __func__, reg, DET_STA); if (!(reg & DET_STA)) return -1; @@ -364,6 +367,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_2); + printk(BIOS_SPEW, "%s: sys_ctl_2 is %08x, CHA_STA is 0x%x\n", __func__, reg, CHA_STA); if (reg & CHA_STA) { printk(BIOS_DEBUG, "Input stream clk is changing\n"); return -1; @@ -452,6 +456,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: Start\n", __func__); reg = readl(&base->func_en_1); reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); reg |= MASTER_VID_FUNC_EN_N; @@ -474,6 +479,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; writel(reg, &base->soc_general_ctl); + printk(BIOS_SPEW, "%s: Done\n", __func__); } void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..88cd90c 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -71,6 +71,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + memset((void *)lcdbase, 0x55, 0x100000); ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 962c79b..ec98e9e 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -217,12 +217,17 @@ static void mainboard_init(device_t dev) i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_init(7, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + clock_gate(); + snow_lcd_vdd(); do { udelay(50); } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); + snow_backlight_vdd(); + snow_backlight_pwm(); + snow_backlight_en(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { @@ -231,7 +236,7 @@ static void mainboard_init(device_t dev) } if (dp_controller_init(&dp_device)) - continue; + break; // continue; udelay(LCD_T3_DELAY_MS * 1000);

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New patch to review for coreboot: 016ac7e GOOGLE/SNOW: get graphics working
by Ronald G. Minnich 19 Apr '13

19 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3116 -gerrit commit 016ac7ea675428e72cc18f17327a63aa5c8f8a60 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 18:09:24 2013 -0700 GOOGLE/SNOW: get graphics working draft patch, needs cleanup, but we've got a blue screen of life. Change-Id: I16e711c97e9d02c916824f621e2313297448732b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 76 ++++++++++++++++++++++++----- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 6 +++ src/cpu/samsung/exynos5250/cpu.c | 1 + src/mainboard/google/snow/ramstage.c | 7 ++- 4 files changed, 76 insertions(+), 14 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 11d666b..1bb97a7 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -41,6 +42,24 @@ #include "cpu/samsung/exynos5250/s5p-dp.h" #include "s5p-dp-core.h" +/* useful information. Here is the rough outline of how we bring up the display. + *1. Upon power-on Sink generates a hot plug detection pulse thru HPD + *2. Source determines video mode by reading DPCD receiver capability field (DPCD 00000h to + * 0000Dh) including eDP CP capability register (DPCD 0000Dh) + *3. Sink replies DPCD receiver capability field. + *4. Source starts EDID read thru I2C-over-AUX + *5. Sink replies EDID thru I2C-over-AUX + *6. Source determines link configuration, such as MAX_LINK_RATE and + * MAX_LANE_COUNT. Source also determines which type of eDP Authentication method + * to use and writes DPCD link configuration field (DPCD 00100h to 0010Ah) including eDP + * configuration set (DPCD 0010Ah). + *7. Source starts link training. Sink does clock recovery and equalization + *8. Source reads DPCD link status field (DPCD 00200h to 0020Bh) + *9. Sink replies DPCD link status field. If main link is not stable, Source repeats Step 7. + *10. Source sends MSA (Main Stream Attribute) data. Sink extracts video parameters and + * recovers stream clock. + *11. Source sends video data + */ /* To help debug any init errors here, define a list of possible errors */ enum { ERR_PLL_NOT_UNLOCKED = 2, @@ -83,7 +102,6 @@ int lcd_line_length; int lcd_color_fg; int lcd_color_bg; -void *lcd_base; /* Start of framebuffer memory */ void *lcd_console_address; /* Start of console buffer */ short console_col; @@ -127,38 +145,51 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, { unsigned int val; u32 fbsize; - struct exynos5_fimd *fimd = + struct exynos5_fimd *fimd = //14400000 samsung_get_base_fimd(); - struct exynos5_disp_ctrl *disp_ctrl = + struct exynos5_disp_ctrl *disp_ctrl = //14420000 samsung_get_base_disp_ctrl(); + printk(BIOS_SPEW, "%s: fimd %p disp_ctrl %p\n", __func__, fimd, disp_ctrl); + printk(BIOS_SPEW, "pd %p\n", pd); + printk(BIOS_SPEW, "lcdbase %p\n", lcdbase); + printk(BIOS_SPEW, "pd->xres %d pd->yres %d\n", pd->xres, pd->yres); + printk(BIOS_SPEW, "Write %08x to %p\n", pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1); val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to fimd->vidcon0\n", val); writel(val, &fimd->vidcon0); val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) | (pd->lower_margin << V_FRONT_PORCH_OFFSET) | (pd->upper_margin << V_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon0); writel(val, &disp_ctrl->vidtcon0); val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) | (pd->right_margin << H_FRONT_PORCH_OFFSET) | (pd->left_margin << H_BACK_PORCH_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon1); writel(val, &disp_ctrl->vidtcon1); val = ((pd->xres - 1) << HOZVAL_OFFSET) | ((pd->yres - 1) << LINEVAL_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &disp_ctrl->vidtcon2); writel(val, &disp_ctrl->vidtcon2); - writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)lcdbase, &fimd->vidw00add0b0); + writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); - writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)fbsize, &fimd->vidw00add1b0); + writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); + printk(BIOS_SPEW, "Write %08x to %p\n", (unsigned int)pd->xres*2, &fimd->vidw00add0b0); writel(pd->xres * 2, &fimd->vidw00add2); val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET); val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET); + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->vidosd0b); writel(val, &fimd->vidosd0b); writel(pd->xres * pd->yres, &fimd->vidosd0c); @@ -166,6 +197,7 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET; val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN; + printk(BIOS_SPEW, "Write %08x to %p\n", val, &fimd->wincon0); writel(val, &fimd->wincon0); /* DPCLKCON_ENABLE */ @@ -192,7 +224,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, struct video_info *video_info) { int timeout = 0; - u32 start; + u32 start, end; struct exynos5_dp *base = dp->base; s5p_dp_config_video_slave_mode(dp, video_info); @@ -207,16 +239,17 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } - start = get_timer(0); + start = timer_us(); + end = start + STREAM_ON_TIMEOUT*1000; do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { timeout++; break; } - } while (get_timer(start) <= STREAM_ON_TIMEOUT); + } while (timer_us() < end); if (!timeout) { - printk(BIOS_DEBUG, "Video Clock Not ok\n"); + printk(BIOS_DEBUG, "Video Clock Not ok after %d microseconds waiting\n", timer_us() - start); return -ERR_VIDEO_CLOCK_BAD; } @@ -256,7 +289,7 @@ static int s5p_dp_enable_rx_to_enhanced_mode(struct s5p_dp_device *dp) printk(BIOS_DEBUG, "DPCD read error\n"); return -ERR_DPCD_READ_ERROR1; } - + /* let's not do this and see if it gets better */ if (s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, DPCD_ENHANCED_FRAME_EN | (data & DPCD_LANE_COUNT_SET_MASK))) { @@ -409,23 +442,25 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, unsigned int max_lane, unsigned int max_rate) { + int pll_is_locked = 0; u32 data; u32 start; int lane; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: start\n", __func__); /* Stop Video */ clrbits_le32(&base->video_ctl_1, VIDEO_EN); start = get_timer(0); - while (s5p_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + while ((pll_is_locked = s5p_dp_get_pll_lock_status(dp)) == PLL_UNLOCKED) { if (get_timer(start) > PLL_LOCK_TIMEOUT) { /* Ignore this error, and try to continue */ printk(BIOS_ERR, "PLL is not locked yet.\n"); break; } } - + printk(BIOS_SPEW, "PLL is %slocked\n", pll_is_locked == PLL_LOCKED ? "": "un"); /* Reset Macro */ setbits_le32(&base->dp_phy_test, MACRO_RST); @@ -449,6 +484,9 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, s5p_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); s5p_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); + printk(BIOS_SPEW, "%s: rate 0x%x, lane_count %d\n", __func__, + dp->link_train.link_rate, dp->link_train.lane_count); + if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { printk(BIOS_DEBUG, "Rx Max Link Rate is abnormal :%x !\n", @@ -471,21 +509,27 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, dp->link_train.link_rate = max_rate; /* Set link rate and count as you want to establish*/ + printk(BIOS_SPEW, "Set link rate and count\n"); writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); /* Set sink to D0 (Sink Not Ready) mode. */ + printk(BIOS_SPEW, "Set sink rate to D0\n"); s5p_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); /* Start HW link training */ + printk(BIOS_SPEW, "Start Link hardware training\n"); writel(HW_TRAINING_EN, &base->dp_hw_link_training); - /* Wait unitl HW link training done */ + /* Wait until HW link training done */ + printk(BIOS_SPEW, "Wait until HW link training done\n"); s5p_dp_wait_hw_link_training_done(dp); + printk(BIOS_SPEW, "HW link training done\n"); /* Get hardware link training status */ data = readl(&base->dp_hw_link_training); + printk(BIOS_SPEW, "hardware link training status: 0x%08x\n", data); if (data != 0) { printk(BIOS_DEBUG, " H/W link training failure: 0x%x\n", data); return -ERR_LINK_TRAINING_FAILURE; @@ -498,6 +542,8 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, data = readl(&base->lane_count_set); dp->link_train.lane_count = data; + printk(BIOS_SPEW, "Done training: Link bandwidth: 0x%x, lane_count: %d\n", + dp->link_train.link_rate, data); return 0; } @@ -534,12 +580,14 @@ int dp_controller_init(struct s5p_dp_device *dp_device) /* Minimum delay after H/w Link training */ udelay(1000); + printk(BIOS_DEBUG, "call s5p_dp_enable_scramble\n"); ret = s5p_dp_enable_scramble(dp); if (ret) { printk(BIOS_DEBUG, "unable to set scramble mode\n"); return ret; } + printk(BIOS_DEBUG, "call s5p_dp_enable_rx_to_enhanced_mode\n"); ret = s5p_dp_enable_rx_to_enhanced_mode(dp); if (ret) { printk(BIOS_DEBUG, "unable to set enhanced mode\n"); @@ -554,7 +602,9 @@ int dp_controller_init(struct s5p_dp_device *dp_device) writel(dp->link_train.lane_count, &base->lane_count_set); writel(dp->link_train.link_rate, &base->link_bw_set); + printk(BIOS_DEBUG, "call s5p_dp_init_video\n"); s5p_dp_init_video(dp); + printk(BIOS_DEBUG, "call s5p_dp_config_video\n"); ret = s5p_dp_config_video(dp, dp->video_info); if (ret) { printk(BIOS_DEBUG, "unable to config video\n"); diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..49fe1cb 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -102,6 +102,7 @@ unsigned int s5p_dp_get_pll_lock_status(struct s5p_dp_device *dp) u32 reg; reg = readl(&dp->base->dp_debug_ctl); + printk(BIOS_SPEW, "%s: reg is 0x%x, PLL_LOCK is 0x%x\n", __func__, reg, PLL_LOCK); if (reg & PLL_LOCK) return PLL_LOCKED; else @@ -351,11 +352,13 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: sys_ctl_1 is %p\n", __func__, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); writel(reg, &base->sys_ctl_1); reg = readl(&base->sys_ctl_1); + printk(BIOS_SPEW, "%s: sys_ctl_1 is %08x, DET_STA is 0x%x\n", __func__, reg, DET_STA); if (!(reg & DET_STA)) return -1; @@ -364,6 +367,7 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_2); + printk(BIOS_SPEW, "%s: sys_ctl_2 is %08x, CHA_STA is 0x%x\n", __func__, reg, CHA_STA); if (reg & CHA_STA) { printk(BIOS_DEBUG, "Input stream clk is changing\n"); return -1; @@ -452,6 +456,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, u32 reg; struct exynos5_dp *base = dp->base; + printk(BIOS_SPEW, "%s: Start\n", __func__); reg = readl(&base->func_en_1); reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); reg |= MASTER_VID_FUNC_EN_N; @@ -474,6 +479,7 @@ void s5p_dp_config_video_slave_mode(struct s5p_dp_device *dp, reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; writel(reg, &base->soc_general_ctl); + printk(BIOS_SPEW, "%s: Done\n", __func__); } void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 09b670e..88cd90c 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -71,6 +71,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, fb_size + (KiB-1)/KiB); printk(BIOS_DEBUG, "Initializing exynos VGA, base %p\n",(void *)lcdbase); + memset((void *)lcdbase, 0x55, 0x100000); ret = lcd_ctrl_init(&vi, &panel, (void *)lcdbase); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 962c79b..ec98e9e 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -217,12 +217,17 @@ static void mainboard_init(device_t dev) i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); i2c_init(7, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + clock_gate(); + snow_lcd_vdd(); do { udelay(50); } while (!exynos_dp_hotplug()); exynos_dp_bridge_setup(); + snow_backlight_vdd(); + snow_backlight_pwm(); + snow_backlight_en(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { @@ -231,7 +236,7 @@ static void mainboard_init(device_t dev) } if (dp_controller_init(&dp_device)) - continue; + break; // continue; udelay(LCD_T3_DELAY_MS * 1000);

1 0

Patch set updated for coreboot: a3d7da4 Eliminate use of pointers in coreboot table
by Stefan Reinauer 19 Apr '13

19 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3115 -gerrit commit a3d7da4d1ec532f77828a621924b32881c2e8a95 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Apr 18 18:01:34 2013 -0700 Eliminate use of pointers in coreboot table Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/coreboot_tables.h | 6 +++--- src/include/boot/coreboot_tables.h | 4 ++-- src/lib/coreboot_table.c | 2 +- src/vendorcode/google/chromeos/gnvs.c | 4 ++-- src/vendorcode/google/chromeos/gnvs.h | 2 +- util/cbmem/cbmem.c | 26 +++++++++++++++++++++++--- 6 files changed, 32 insertions(+), 12 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 02c9449..3889ede 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -188,7 +188,7 @@ struct cb_gpios { struct cb_vdat { uint32_t tag; uint32_t size; /* size of the entire entry */ - void *vdat_addr; + uint64_t vdat_addr; uint32_t vdat_size; }; @@ -198,7 +198,7 @@ struct cb_vdat { struct cb_cbmem_tab { uint32_t tag; uint32_t size; - void *cbmem_tab; + uint64_t cbmem_tab; }; #define CB_TAG_VBNV 0x0019 @@ -213,7 +213,7 @@ struct cb_vbnv { struct cb_vboot_handoff { uint32_t tag; uint32_t size; - void *vboot_handoff_addr; + uint64_t vboot_handoff_addr; uint32_t vboot_handoff_size; }; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index a7e4ab0..ee1c29f 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -218,7 +218,7 @@ struct lb_vdat { uint32_t tag; uint32_t size; - void *vdat_addr; + uint64_t vdat_addr; uint32_t vdat_size; }; @@ -246,7 +246,7 @@ struct lb_vboot_handoff { uint32_t tag; uint32_t size; - void *vboot_handoff_addr; + uint64_t vboot_handoff_addr; uint32_t vboot_handoff_size; }; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 765c510..d25b59d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -232,7 +232,7 @@ static void lb_vboot_handoff(struct lb_header *header) vbho = (struct lb_vboot_handoff *)lb_new_record(header); vbho->tag = LB_TAB_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); - vbho->vboot_handoff_addr = addr; + vbho->vboot_handoff_addr = (intptr_t)addr; vbho->vboot_handoff_size = size; } #else diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 0d40950..5ee3665 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -79,8 +79,8 @@ void chromeos_set_me_hash(u32 *hash, int len) memcpy(me_hash_saved, hash, len*sizeof(u32)); } -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) +void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size) { - *vdat_addr = vboot_data; + *vdat_addr = (intptr_t)vboot_data; *vdat_size = sizeof(*vboot_data); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 4067494..00fe443 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -64,6 +64,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); void chromeos_set_me_hash(u32*, int); -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); +void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size); #endif diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..44d936d 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -21,6 +21,7 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> +#include <inttypes.h> #include <getopt.h> #include <errno.h> #include <fcntl.h> @@ -127,12 +128,31 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_memory_range cbmem; +/* This is a work-around for a nasty problem introduced by initially having + * pointer sized entries in the lb_cbmem_ref structures. This caused problems + * on 64bit x86 systems because coreboot is 32bit on those systems. + * When the problem was found, it was corrected, but there are a lot of systems + * out there with a firmware that does not produce the right lb_cbmem_ref structure. + * Hence we try to autocorrect this issue here. + */ +static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref) +{ + static struct lb_cbmem_ref ret; + + ret = *cbmem_ref; + + if (cbmem_ref->size < sizeof(*cbmem_ref)) + ret.cbmem_addr &= 0xffffffff; + + return ret; +} + static int parse_cbtable(u64 address) { int i, found = 0; void *buf; - debug("Looking for coreboot table at %llx\n", address); + debug("Looking for coreboot table at %" PRIx64 "\n", address); buf = map_memory(address); /* look at every 16 bytes within 4K of the base */ @@ -183,12 +203,12 @@ static int parse_cbtable(u64 address) } case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = *(struct lb_cbmem_ref *) lbr_p; + timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = *(struct lb_cbmem_ref *) lbr_p; + console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_FORWARD: {

1 0

New patch to review for coreboot: 2da8f93 Eliminate use of pointers in coreboot table
by Stefan Reinauer 19 Apr '13

19 Apr '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3115 -gerrit commit 2da8f938da797e023929df864efd1093e89a365a Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Apr 18 18:01:34 2013 -0700 Eliminate use of pointers in coreboot table Because pointers can be 32bit or 64bit big, using them in the coreboot table requires the OS and the firmware to operate in the same mode which is not always the case. Hence, use 64bit for all pointers stored in the coreboot table. Guess we'll have to fix this up once we port to the first 128bit machines. Change-Id: I46fc1dad530e5230986f7aa5740595428ede4f93 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- payloads/libpayload/include/coreboot_tables.h | 6 +++--- src/include/boot/coreboot_tables.h | 4 ++-- src/lib/coreboot_table.c | 2 +- src/vendorcode/google/chromeos/gnvs.c | 4 ++-- src/vendorcode/google/chromeos/gnvs.h | 2 +- util/cbmem/cbmem.c | 23 +++++++++++++++++++++-- 6 files changed, 30 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 02c9449..3889ede 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -188,7 +188,7 @@ struct cb_gpios { struct cb_vdat { uint32_t tag; uint32_t size; /* size of the entire entry */ - void *vdat_addr; + uint64_t vdat_addr; uint32_t vdat_size; }; @@ -198,7 +198,7 @@ struct cb_vdat { struct cb_cbmem_tab { uint32_t tag; uint32_t size; - void *cbmem_tab; + uint64_t cbmem_tab; }; #define CB_TAG_VBNV 0x0019 @@ -213,7 +213,7 @@ struct cb_vbnv { struct cb_vboot_handoff { uint32_t tag; uint32_t size; - void *vboot_handoff_addr; + uint64_t vboot_handoff_addr; uint32_t vboot_handoff_size; }; diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index a7e4ab0..ee1c29f 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -218,7 +218,7 @@ struct lb_vdat { uint32_t tag; uint32_t size; - void *vdat_addr; + uint64_t vdat_addr; uint32_t vdat_size; }; @@ -246,7 +246,7 @@ struct lb_vboot_handoff { uint32_t tag; uint32_t size; - void *vboot_handoff_addr; + uint64_t vboot_handoff_addr; uint32_t vboot_handoff_size; }; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 765c510..d25b59d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -232,7 +232,7 @@ static void lb_vboot_handoff(struct lb_header *header) vbho = (struct lb_vboot_handoff *)lb_new_record(header); vbho->tag = LB_TAB_VBOOT_HANDOFF; vbho->size = sizeof(*vbho); - vbho->vboot_handoff_addr = addr; + vbho->vboot_handoff_addr = (intptr_t)addr; vbho->vboot_handoff_size = size; } #else diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 0d40950..5ee3665 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -79,8 +79,8 @@ void chromeos_set_me_hash(u32 *hash, int len) memcpy(me_hash_saved, hash, len*sizeof(u32)); } -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size) +void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size) { - *vdat_addr = vboot_data; + *vdat_addr = (intptr_t)vboot_data; *vdat_size = sizeof(*vboot_data); } diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 4067494..00fe443 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -64,6 +64,6 @@ typedef struct { extern chromeos_acpi_t *vboot_data; void chromeos_init_vboot(chromeos_acpi_t *chromeos); void chromeos_set_me_hash(u32*, int); -void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size); +void acpi_get_vdat_info(uint64_t *vdat_addr, uint32_t *vdat_size); #endif diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 1ff9a08..7ed5d94 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -127,6 +127,25 @@ static struct lb_cbmem_ref timestamps; static struct lb_cbmem_ref console; static struct lb_memory_range cbmem; +/* This is a work-around for a nasty problem introduced by initially having + * pointer sized entries in the lb_cbmem_ref structures. This caused problems + * on 64bit x86 systems because coreboot is 32bit on those systems. + * When the problem was found, it was corrected, but there are a lot of systems + * out there with a firmware that does not produce the right lb_cbmem_ref structure. + * Hence we try to autocorrect this issue here. + */ +static struct lb_cbmem_ref parse_cbmem_ref(struct lb_cbmem_ref *cbmem_ref) +{ + static struct lb_cbmem_ref ret; + + ret = *cbmem_ref; + + if (cbmem_ref->size < sizeof(*cbmem_ref)) + ret->addr &= 0xffffffff; + + return ret; +} + static int parse_cbtable(u64 address) { int i, found = 0; @@ -183,12 +202,12 @@ static int parse_cbtable(u64 address) } case LB_TAG_TIMESTAMPS: { debug(" Found timestamp table.\n"); - timestamps = *(struct lb_cbmem_ref *) lbr_p; + timestamps = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_CBMEM_CONSOLE: { debug(" Found cbmem console.\n"); - console = *(struct lb_cbmem_ref *) lbr_p; + console = parse_cbmem_ref((struct lb_cbmem_ref *) lbr_p); continue; } case LB_TAG_FORWARD: {

1 0

New patch to review for coreboot: 3d5d6bd exynos5: eliminate lcd_base variable
by David Hendricks 19 Apr '13

19 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3114 -gerrit commit 3d5d6bd86958616c0e9f6bb9f5b027ddbae680f4 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 18 17:27:07 2013 -0700 exynos5: eliminate lcd_base variable The original imported code used "lcdbase" and "lcd_base" which quite predictably caused confusion and bugs. Let's put an end to this little bit of insanity. Change-Id: I4f995482cfbff5f23bb296a1e6d35beccf5f8a91 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index 11d666b..54a2d7a 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -83,7 +83,6 @@ int lcd_line_length; int lcd_color_fg; int lcd_color_bg; -void *lcd_base; /* Start of framebuffer memory */ void *lcd_console_address; /* Start of console buffer */ short console_col; @@ -150,10 +149,10 @@ void fb_init(vidinfo_t *panel_info, void *lcdbase, ((pd->yres - 1) << LINEVAL_OFFSET); writel(val, &disp_ctrl->vidtcon2); - writel((unsigned int)lcd_base, &fimd->vidw00add0b0); + writel((unsigned int)lcdbase, &fimd->vidw00add0b0); fbsize = calc_fbsize(panel_info); - writel((unsigned int)lcd_base + fbsize, &fimd->vidw00add1b0); + writel((unsigned int)lcdbase + fbsize, &fimd->vidw00add1b0); writel(pd->xres * 2, &fimd->vidw00add2);

1 0

New patch to review for coreboot: 5bf5c5a google/snow: Minor clean-ups for display setup code in ramstage
by David Hendricks 19 Apr '13

19 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3113 -gerrit commit 5bf5c5aa127a1edbcc5f53fce5e243dd271a5ccd Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 18 16:45:47 2013 -0700 google/snow: Minor clean-ups for display setup code in ramstage This just cleans up a few areas: - Removed an unnecessary delay from exynos_dp_bridge_setup() - The delay at the end of exynos_dp_bridge_init() is necessary, so removed the comment suggesting that it might not be. - Simplified exynos_dp_hotplug Change-Id: I44150f5ef3958e333985440c1022b4f1544a93aa Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/ramstage.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 962c79b..1b01758 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -98,8 +98,6 @@ static void exynos_dp_bridge_setup(void) gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE); udelay(10); gpio_set_value(dp_rst_l, 1); - - udelay(90000); /* FIXME: this might be unnecessary */ } static void exynos_dp_bridge_init(void) @@ -116,19 +114,13 @@ static void exynos_dp_bridge_init(void) * roughly 50ms after PD is de-asserted. The phantom high * makes it hard for us to know when the NXP chip is up. */ - udelay(90000); /* FIXME: this might be unnecessary */ + udelay(90000); } static int exynos_dp_hotplug(void) { - int x = gpio_get_value(dp_hpd); /* Check HPD. If it's high, we're all good. */ -// if (gpio_get_value(dp_hpd)) -// return 0; - printk(BIOS_DEBUG, "%s: dp_hpd: 0x%02x\n", __func__, x); - if (x) - return 0; - return -1; + return gpio_get_value(dp_hpd) ? 0 : 1; } static void exynos_dp_reset(void)

1 0

Patch set updated for coreboot: 80475ac crossgcc: update to gcc 4.7.3
by Idwer Vollering 19 Apr '13

19 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3112 -gerrit commit 80475accf822d1e05bfc645498e9775426c8f4d6 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, under certain circumstances this version can't (cross-)compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/patches/gcc-4.7.2_armv7a.patch | 12 ---- util/crossgcc/patches/gcc-4.7.2_texinfo.patch | 98 --------------------------- util/crossgcc/patches/gcc-4.7.3_armv7a.patch | 12 ++++ 4 files changed, 13 insertions(+), 111 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 34518a8..dc9b979 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.1 MPC_VERSION=1.0.1 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.7.2 +GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.23 GDB_VERSION=7.5 diff --git a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch b/util/crossgcc/patches/gcc-4.7.2_armv7a.patch deleted file mode 100644 index 82e6609..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur gcc-4.7.2/config.sub gcc-4.7.2/config.sub ---- gcc-4.7.2/config.sub 2012-08-06 07:34:27.000000000 -0700 -+++ gcc-4.7.2/config.sub 2012-12-04 15:03:30.813137430 -0800 -@@ -250,7 +250,7 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ - | be32 | be64 \ - | bfin \ - | c4x | clipper \ diff --git a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch b/util/crossgcc/patches/gcc-4.7.2_texinfo.patch deleted file mode 100644 index 34c6a68..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -diff -urp gcc-4.7.2/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi ---- gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:41:01.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:55:05.000000000 +0100 -@@ -803,7 +803,7 @@ Replacement: [ ] @{ @} - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff -urp gcc-4.7.2/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi ---- gcc-4.7.2/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/generic.texi 2013-03-28 14:01:19.000000000 +0100 -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff -urp gcc-4.7.2/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi ---- gcc-4.7.2/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200 -+++ gcc-4.7.2/gcc/doc/invoke.texi 2013-03-28 13:55:57.000000000 +0100 -@@ -5179,7 +5179,7 @@ thus dbg_cnt() returns true always unles - e.g. With -fdbg-cnt=dce:10,tail_call:0 - dbg_cnt(dce) will return true only for first 10 invocations - --@itemx -fenable-@var{kind}-@var{pass} -+@item -fenable-@var{kind}-@var{pass} - @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list} - @opindex fdisable- - @opindex fenable- -@@ -5327,11 +5327,11 @@ Dump after duplicating the computed goto - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5342,11 +5342,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5391,7 +5391,7 @@ Dump after the initialization of the reg - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5421,7 +5421,7 @@ Dump after removing redundant mode switc - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5433,7 +5433,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function prologues and epilogues. - diff --git a/util/crossgcc/patches/gcc-4.7.3_armv7a.patch b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch new file mode 100644 index 0000000..ccbc01e --- /dev/null +++ b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch @@ -0,0 +1,12 @@ +diff -ur gcc-4.7.3/config.sub gcc-4.7.3-patched/config.sub +--- gcc-4.7.3/config.sub 2012-08-06 16:34:27.000000000 +0200 ++++ gcc-4.7.3-patched/config.sub 2013-04-19 00:25:16.401391381 +0200 +@@ -250,7 +250,7 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | clipper \

1 0

Patch set updated for coreboot: 543d9be crossgcc: update to gcc 4.7.3
by Idwer Vollering 19 Apr '13

19 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3112 -gerrit commit 543d9bec0e0ca742d1332774dc4978e5a168fc4e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 The resulting coreboot.rom is not runtime tested (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have moved on to gcc 4.8, this version under certain circumstances can't compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/patches/gcc-4.7.2_armv7a.patch | 12 ---- util/crossgcc/patches/gcc-4.7.2_texinfo.patch | 98 --------------------------- util/crossgcc/patches/gcc-4.7.3_armv7a.patch | 12 ++++ 4 files changed, 13 insertions(+), 111 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 34518a8..dc9b979 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.1 MPC_VERSION=1.0.1 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.7.2 +GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.23 GDB_VERSION=7.5 diff --git a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch b/util/crossgcc/patches/gcc-4.7.2_armv7a.patch deleted file mode 100644 index 82e6609..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur gcc-4.7.2/config.sub gcc-4.7.2/config.sub ---- gcc-4.7.2/config.sub 2012-08-06 07:34:27.000000000 -0700 -+++ gcc-4.7.2/config.sub 2012-12-04 15:03:30.813137430 -0800 -@@ -250,7 +250,7 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ - | be32 | be64 \ - | bfin \ - | c4x | clipper \ diff --git a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch b/util/crossgcc/patches/gcc-4.7.2_texinfo.patch deleted file mode 100644 index 34c6a68..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -diff -urp gcc-4.7.2/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi ---- gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:41:01.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:55:05.000000000 +0100 -@@ -803,7 +803,7 @@ Replacement: [ ] @{ @} - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff -urp gcc-4.7.2/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi ---- gcc-4.7.2/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/generic.texi 2013-03-28 14:01:19.000000000 +0100 -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff -urp gcc-4.7.2/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi ---- gcc-4.7.2/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200 -+++ gcc-4.7.2/gcc/doc/invoke.texi 2013-03-28 13:55:57.000000000 +0100 -@@ -5179,7 +5179,7 @@ thus dbg_cnt() returns true always unles - e.g. With -fdbg-cnt=dce:10,tail_call:0 - dbg_cnt(dce) will return true only for first 10 invocations - --@itemx -fenable-@var{kind}-@var{pass} -+@item -fenable-@var{kind}-@var{pass} - @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list} - @opindex fdisable- - @opindex fenable- -@@ -5327,11 +5327,11 @@ Dump after duplicating the computed goto - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5342,11 +5342,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5391,7 +5391,7 @@ Dump after the initialization of the reg - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5421,7 +5421,7 @@ Dump after removing redundant mode switc - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5433,7 +5433,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function prologues and epilogues. - diff --git a/util/crossgcc/patches/gcc-4.7.3_armv7a.patch b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch new file mode 100644 index 0000000..ccbc01e --- /dev/null +++ b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch @@ -0,0 +1,12 @@ +diff -ur gcc-4.7.3/config.sub gcc-4.7.3-patched/config.sub +--- gcc-4.7.3/config.sub 2012-08-06 16:34:27.000000000 +0200 ++++ gcc-4.7.3-patched/config.sub 2013-04-19 00:25:16.401391381 +0200 +@@ -250,7 +250,7 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | clipper \

1 0

New patch to review for coreboot: 2f0fb1e crossgcc: update to gcc 4.7.3
by Idwer Vollering 19 Apr '13

19 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3112 -gerrit commit 2f0fb1e714aa3f8ce4dcc6a941be657841f9dc0e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Fri Apr 19 00:56:57 2013 +0200 crossgcc: update to gcc 4.7.3 Update crossgcc to use gcc 4.7.3 Untested on hardware (any volunteers?). Drop the texinfo patch, rename the armv7a patch. Some Linux distributions have early-adopted gcc 4.8, this version couldn't compile gcc 4.7.2 Bug report: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56927 Change-Id: Id8ce5f86c34e1a0900d44dc6ae4e81cb9548ecc2 Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/patches/gcc-4.7.2_armv7a.patch | 12 ---- util/crossgcc/patches/gcc-4.7.2_texinfo.patch | 98 --------------------------- util/crossgcc/patches/gcc-4.7.3_armv7a.patch | 12 ++++ 4 files changed, 13 insertions(+), 111 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 34518a8..dc9b979 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -33,7 +33,7 @@ GMP_VERSION=5.0.5 MPFR_VERSION=3.1.1 MPC_VERSION=1.0.1 LIBELF_VERSION=0.8.13 -GCC_VERSION=4.7.2 +GCC_VERSION=4.7.3 GCC_AUTOCONF_VERSION=2.64 BINUTILS_VERSION=2.23 GDB_VERSION=7.5 diff --git a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch b/util/crossgcc/patches/gcc-4.7.2_armv7a.patch deleted file mode 100644 index 82e6609..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_armv7a.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -ur gcc-4.7.2/config.sub gcc-4.7.2/config.sub ---- gcc-4.7.2/config.sub 2012-08-06 07:34:27.000000000 -0700 -+++ gcc-4.7.2/config.sub 2012-12-04 15:03:30.813137430 -0800 -@@ -250,7 +250,7 @@ - | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ - | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ - | am33_2.0 \ -- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ -+ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ - | be32 | be64 \ - | bfin \ - | c4x | clipper \ diff --git a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch b/util/crossgcc/patches/gcc-4.7.2_texinfo.patch deleted file mode 100644 index 34c6a68..0000000 --- a/util/crossgcc/patches/gcc-4.7.2_texinfo.patch +++ /dev/null @@ -1,98 +0,0 @@ -diff -urp gcc-4.7.2/gcc/doc/cppopts.texi gcc-4.7.2/gcc/doc/cppopts.texi ---- gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:41:01.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/cppopts.texi 2013-03-28 13:55:05.000000000 +0100 -@@ -803,7 +803,7 @@ Replacement: [ ] @{ @} - Enable special code to work around file systems which only permit very - short file names, such as MS-DOS@. - --@itemx --help -+@item --help - @itemx --target-help - @opindex help - @opindex target-help -diff -urp gcc-4.7.2/gcc/doc/generic.texi gcc-4.7.2/gcc/doc/generic.texi ---- gcc-4.7.2/gcc/doc/generic.texi 2011-12-23 23:07:16.000000000 +0100 -+++ gcc-4.7.2/gcc/doc/generic.texi 2013-03-28 14:01:19.000000000 +0100 -@@ -1415,13 +1415,13 @@ generate these expressions anyhow, if it - not matter. The type of the operands and that of the result are - always of @code{BOOLEAN_TYPE} or @code{INTEGER_TYPE}. - --@itemx POINTER_PLUS_EXPR -+@item POINTER_PLUS_EXPR - This node represents pointer arithmetic. The first operand is always - a pointer/reference type. The second operand is always an unsigned - integer type compatible with sizetype. This is the only binary - arithmetic operand that can operate on pointer types. - --@itemx PLUS_EXPR -+@item PLUS_EXPR - @itemx MINUS_EXPR - @itemx MULT_EXPR - These nodes represent various binary arithmetic operations. -diff -urp gcc-4.7.2/gcc/doc/invoke.texi gcc-4.7.2/gcc/doc/invoke.texi ---- gcc-4.7.2/gcc/doc/invoke.texi 2012-09-14 22:45:27.000000000 +0200 -+++ gcc-4.7.2/gcc/doc/invoke.texi 2013-03-28 13:55:57.000000000 +0100 -@@ -5179,7 +5179,7 @@ thus dbg_cnt() returns true always unles - e.g. With -fdbg-cnt=dce:10,tail_call:0 - dbg_cnt(dce) will return true only for first 10 invocations - --@itemx -fenable-@var{kind}-@var{pass} -+@item -fenable-@var{kind}-@var{pass} - @itemx -fdisable-@var{kind}-@var{pass}=@var{range-list} - @opindex fdisable- - @opindex fenable- -@@ -5327,11 +5327,11 @@ Dump after duplicating the computed goto - @option{-fdump-rtl-ce3} enable dumping after the three - if conversion passes. - --@itemx -fdump-rtl-cprop_hardreg -+@item -fdump-rtl-cprop_hardreg - @opindex fdump-rtl-cprop_hardreg - Dump after hard register copy propagation. - --@itemx -fdump-rtl-csa -+@item -fdump-rtl-csa - @opindex fdump-rtl-csa - Dump after combining stack adjustments. - -@@ -5342,11 +5342,11 @@ Dump after combining stack adjustments. - @option{-fdump-rtl-cse1} and @option{-fdump-rtl-cse2} enable dumping after - the two common sub-expression elimination passes. - --@itemx -fdump-rtl-dce -+@item -fdump-rtl-dce - @opindex fdump-rtl-dce - Dump after the standalone dead code elimination passes. - --@itemx -fdump-rtl-dbr -+@item -fdump-rtl-dbr - @opindex fdump-rtl-dbr - Dump after delayed branch scheduling. - -@@ -5391,7 +5391,7 @@ Dump after the initialization of the reg - @opindex fdump-rtl-initvals - Dump after the computation of the initial value sets. - --@itemx -fdump-rtl-into_cfglayout -+@item -fdump-rtl-into_cfglayout - @opindex fdump-rtl-into_cfglayout - Dump after converting to cfglayout mode. - -@@ -5421,7 +5421,7 @@ Dump after removing redundant mode switc - @opindex fdump-rtl-rnreg - Dump after register renumbering. - --@itemx -fdump-rtl-outof_cfglayout -+@item -fdump-rtl-outof_cfglayout - @opindex fdump-rtl-outof_cfglayout - Dump after converting from cfglayout mode. - -@@ -5433,7 +5433,7 @@ Dump after the peephole pass. - @opindex fdump-rtl-postreload - Dump after post-reload optimizations. - --@itemx -fdump-rtl-pro_and_epilogue -+@item -fdump-rtl-pro_and_epilogue - @opindex fdump-rtl-pro_and_epilogue - Dump after generating the function prologues and epilogues. - diff --git a/util/crossgcc/patches/gcc-4.7.3_armv7a.patch b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch new file mode 100644 index 0000000..ccbc01e --- /dev/null +++ b/util/crossgcc/patches/gcc-4.7.3_armv7a.patch @@ -0,0 +1,12 @@ +diff -ur gcc-4.7.3/config.sub gcc-4.7.3-patched/config.sub +--- gcc-4.7.3/config.sub 2012-08-06 16:34:27.000000000 +0200 ++++ gcc-4.7.3-patched/config.sub 2013-04-19 00:25:16.401391381 +0200 +@@ -250,7 +250,7 @@ + | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ + | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ + | am33_2.0 \ +- | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ ++ | arc | arm | arm[bl]e | arme[lb] | armv* | armv[345][lb] | avr | avr32 \ + | be32 | be64 \ + | bfin \ + | c4x | clipper \

1 0

New patch to review for coreboot: 2ca12d2 exynos5250: get xres and yres out of the device tree and into the panel descriptor
by Ronald G. Minnich 19 Apr '13

19 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3111 -gerrit commit 2ca12d2e5ef0c49263abebed37723ae0e9d3f01a Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 18 16:10:29 2013 -0700 exynos5250: get xres and yres out of the device tree and into the panel descriptor We neglected to copy xres and yres out; now we do. Change-Id: Icc4a8eb35799d156b11274f71bcfb4a1d10e01e3 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/samsung/exynos5250/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index ee33cf3..09b670e 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -51,6 +51,8 @@ static void exynos_displayport_init(device_t dev) panel.left_margin = conf->left_margin; panel.right_margin = conf->right_margin; panel.hsync = conf->hsync; + panel.xres = conf->xres; + panel.yres = conf->yres; vi.vl_col = conf->xres; vi.vl_row = conf->yres;

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coreboot-gerrit April 2013