coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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506 discussions

New patch to review for coreboot: 3c40cac snow: Get rid of the oprom loaded GPIO.
by Gabe Black 16 Apr '13

16 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3094 -gerrit commit 3c40cac347a1d717bd9118c1c534919cf6db00ec Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 19:07:10 2013 -0700 snow: Get rid of the oprom loaded GPIO. ARM doesn't use option ROMs, so this value doesn't make sense. Change-Id: I1a0f0854e1dd4b9594ca0c147e590337520436da Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index ca105e7..e9e03aa 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -87,14 +87,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); count++; - /* Was VGA Option ROM loaded? */ - gpios->gpios[count].port = -1; /* This is a pseudo GPIO */ - gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = 0; - strncpy((char *)gpios->gpios[count].name, "oprom", - GPIO_MAX_NAME_LENGTH); - count++; - gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); gpios->count = count;

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New patch to review for coreboot: 56aa3f1 snow: Tidy up chromeos.c.
by Gabe Black 16 Apr '13

16 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3093 -gerrit commit 56aa3f1860638a9730886d467746d258ee4670b8 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 18:22:11 2013 -0700 snow: Tidy up chromeos.c. Got rid of a lot of #defines, some of which were converted to enums and the rest which were eliminated entirely. Got rid of cruft in get_developer_mode_switch and started using it for the dev mode GPIO. Instead of a macro defining how many GPIOs are expected, now the code actually counts the GPIOs as they're added. Change-Id: I97b6b9f52a72d1276eb3cf36d7f9dd7b335b4d19 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 101 ++++++++++++++++++----------------- 1 file changed, 51 insertions(+), 50 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index f33f103..ca105e7 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <boot/coreboot_tables.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> @@ -27,19 +28,16 @@ #include <cpu/samsung/exynos5250/gpio.h> #include <cpu/samsung/exynos5-common/gpio.h> -#define ACTIVE_LOW 0 -#define ACTIVE_HIGH 1 -#define WP_GPIO 6 -#define DEVMODE_GPIO 54 -#define RECMODE_GPIO 0 -#define FORCE_RECOVERY_MODE 0 -#define FORCE_DEVELOPER_MODE 0 -#define LID_OPEN 5 -#define POWER_BUTTON 3 - -#include <boot/coreboot_tables.h> +enum { + ACTIVE_LOW = 0, + ACTIVE_HIGH = 1 +}; -#define GPIO_COUNT 6 +enum { + WP_GPIO = 6, + RECMODE_GPIO = 0, + LID_GPIO = 5 +}; static struct exynos5_gpio_part1 *gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; @@ -48,62 +46,65 @@ static struct exynos5_gpio_part2 *gpio_pt2 = void fill_lb_gpios(struct lb_gpios *gpios) { - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + int count = 0; /* Write Protect: active low */ - gpios->gpios[0].port = EXYNOS5_GPD1; - gpios->gpios[0].polarity = ACTIVE_LOW; - gpios->gpios[0].value = s5p_gpio_get_value(&gpio_pt1->d1, WP_GPIO); - strncpy((char *)gpios->gpios[0].name,"write protect", - GPIO_MAX_NAME_LENGTH); + gpios->gpios[count].port = EXYNOS5_GPD1; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = s5p_gpio_get_value(&gpio_pt1->d1, WP_GPIO); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; /* Recovery: active low */ - gpios->gpios[1].port = -1; - gpios->gpios[1].polarity = ACTIVE_HIGH; - gpios->gpios[1].value = get_recovery_mode_switch(); - strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; /* Lid: active high */ - gpios->gpios[2].port = EXYNOS5_GPX3; - gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt2->x3, LID_OPEN); - strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); + gpios->gpios[count].port = EXYNOS5_GPX3; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = s5p_gpio_get_value(&gpio_pt2->x3, LID_GPIO); + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; /* Power: virtual GPIO active low */ - gpios->gpios[3].port = -1; - gpios->gpios[3].polarity = ACTIVE_LOW; - gpios->gpios[3].value = 1; - strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = 1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; /* Developer: virtual GPIO active high */ - gpios->gpios[4].port = -1; - gpios->gpios[4].polarity = ACTIVE_HIGH; - gpios->gpios[4].value = 0; - strncpy((char *)gpios->gpios[4].name,"developer", - GPIO_MAX_NAME_LENGTH); + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; /* Was VGA Option ROM loaded? */ - gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ - gpios->gpios[5].polarity = ACTIVE_HIGH; - gpios->gpios[5].value = 0; - strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); + gpios->gpios[count].port = -1; /* This is a pseudo GPIO */ + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = 0; + strncpy((char *)gpios->gpios[count].name, "oprom", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; - printk(BIOS_ERR, "Added %d GPIOS size %d\n", GPIO_COUNT, gpios->size); + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); } int get_developer_mode_switch(void) { - int dev_mode = 0; - - printk(BIOS_DEBUG,"FORCING DEVELOPER MODE.\n"); - - dev_mode = 1; - printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO, - dev_mode); - - return dev_mode; + return 0; } int get_recovery_mode_switch(void)

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New patch to review for coreboot: 7327d66 snow: Add support for EC based recovery.
by Gabe Black 16 Apr '13

16 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3092 -gerrit commit 7327d665a7b2c9b4d43155f3985c7f16a2b7f0b0 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 18:09:15 2013 -0700 snow: Add support for EC based recovery. Implement the get_recovery_mode_switch function using the newly added I2C based Chrome EC support. Change-Id: I9d0200629887f202edf017cba3222a7d7f5b053e Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index e74df6d..f33f103 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -18,20 +18,20 @@ */ #include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <arch/io.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/gpio.h> #include <cpu/samsung/exynos5-common/gpio.h> -#include <device/device.h> - #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 #define WP_GPIO 6 #define DEVMODE_GPIO 54 +#define RECMODE_GPIO 0 #define FORCE_RECOVERY_MODE 0 #define FORCE_DEVELOPER_MODE 0 #define LID_OPEN 5 @@ -41,17 +41,16 @@ #define GPIO_COUNT 6 +static struct exynos5_gpio_part1 *gpio_pt1 = + (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; +static struct exynos5_gpio_part2 *gpio_pt2 = + (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; + void fill_lb_gpios(struct lb_gpios *gpios) { - struct exynos5_gpio_part1 *gpio_pt1; - struct exynos5_gpio_part2 *gpio_pt2; - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); gpios->count = GPIO_COUNT; - gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; - gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; - /* Write Protect: active low */ gpios->gpios[0].port = EXYNOS5_GPD1; gpios->gpios[0].polarity = ACTIVE_LOW; @@ -60,9 +59,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) GPIO_MAX_NAME_LENGTH); /* Recovery: active low */ - gpios->gpios[1].port = EXYNOS5_GPY1; - gpios->gpios[1].polarity = ACTIVE_LOW; - gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + gpios->gpios[1].port = -1; + gpios->gpios[1].polarity = ACTIVE_HIGH; + gpios->gpios[1].value = get_recovery_mode_switch(); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: active high */ @@ -109,9 +108,15 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - int ec_rec_mode = 0; + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!s5p_gpio_get_value(&gpio_pt1->y1, RECMODE_GPIO)) + return 1; - return ec_rec_mode; + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_recovery_mode_from_vbnv(void)

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New patch to review for coreboot: 2d74384 snow: Fix some comments in chromeos.c.
by Gabe Black 16 Apr '13

16 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3091 -gerrit commit 2d74384aa780c8078c4c0c991312017059a2db10 Author: Gabe Black <gabeblack(a)chromium.org> Date: Mon Apr 15 16:25:02 2013 -0700 snow: Fix some comments in chromeos.c. The comment about the lid switch was left over from when this file was copied from another board and was incorrect. Also fixed a capitalization inconsistency. Change-Id: Icefd19047971e13c08f615578e4a181e82a2997f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 015b71e..e74df6d 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -52,7 +52,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; - /* Write Protect: active Low */ + /* Write Protect: active low */ gpios->gpios[0].port = EXYNOS5_GPD1; gpios->gpios[0].polarity = ACTIVE_LOW; gpios->gpios[0].value = s5p_gpio_get_value(&gpio_pt1->d1, WP_GPIO); @@ -65,7 +65,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Lid: the "switch" comes from the EC */ + /* Lid: active high */ gpios->gpios[2].port = EXYNOS5_GPX3; gpios->gpios[2].polarity = ACTIVE_HIGH; gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt2->x3, LID_OPEN);

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Patch merged into coreboot/master: ed7e29e Lenovo ThinkPad X60: Add Native VGA init.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit ed7e29e6202485ba7b4f27bd415c891abdbb9f1d Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Feb 24 12:01:44 2013 +0100 Lenovo ThinkPad X60: Add Native VGA init. The code has been taken from the google link mainboard and modified to fit the ThinkPad X60. Change-Id: Ie16e45163acdc651ea46699ecc33055bfd34099c Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/2998 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Apr 15 05:09:40 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Apr 16 05:20:11 2013, giving +2 See http://review.coreboot.org/2998 for details. -gerrit

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Patch set updated for coreboot: 6a563db AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI
by Siyuan Wang 16 Apr '13

16 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3090 -gerrit commit 6a563db1e65b8de480dc1f5883e756d8e67c7496 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Apr 15 19:10:24 2013 +0800 AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1] I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. [1] http://review.coreboot.org/#/c/3088/ Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/PlatformGnbPcie.c | 34 +++++++----------------------- 1 file changed, 8 insertions(+), 26 deletions(-) diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index acb9542..51dd9fd 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -79,41 +79,23 @@ PCIe_PORT_DESCRIPTOR PortList [] = { PCIe_DDI_DESCRIPTOR DdiList [] = { /* DP0 to HDMI0/DP */ { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, /* DP1 to FCH */ { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, /* DP2 to HDMI1/DP */ { - 0, + 1, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */ - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) }, - /* GFX Lane 15-12 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - /* GFX Lane 11-8 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - /* GFX Lane 7-4 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -158,7 +140,7 @@ OemCustomizeInitEarly ( /* */ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + sizeof (PCIe_DDI_DESCRIPTOR)) * 3; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -189,12 +171,12 @@ OemCustomizeInitEarly ( LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;

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Patch merged into coreboot/master: cef4ea7 documentation: Complete the AMD-S3.txt
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit cef4ea7fb53f01a74126b85232503a2d106d9933 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Feb 26 18:10:52 2013 +0800 documentation: Complete the AMD-S3.txt Fix some typos and finish empty sections. Change-Id: I08cc971e763252b035ab8ed2118180140e34ac72 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/2483 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Build-Tested: build bot (Jenkins) at Tue Feb 26 11:13:06 2013, giving +1 Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Tue Apr 16 02:31:07 2013, giving +2 See http://review.coreboot.org/2483 for details. -gerrit

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Patch merged into coreboot/master: 76720d0 ec/google: Move plug-n-play initialization to LPC protocol.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit 76720d064da18d67c1be53ab4c0b2af6f1fcfd06 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:06:32 2013 +0800 ec/google: Move plug-n-play initialization to LPC protocol. "Plug-n-play" is not supported on all platforms using Google's Chrome EC. For example, EC on I2C bus will need explicit configuration and initialization. So move the plug-n-play initialization to the LPC implementation. Verified by building Google/Link (with EC/LPC) successfully. Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3089 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Mon Apr 15 17:16:00 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Tue Apr 16 01:07:14 2013, giving +2 See http://review.coreboot.org/3089 for details. -gerrit

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Patch merged into coreboot/master: 6bfbb33 ec/google: Support Google's Chrome EC on I2C interface.
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit 6bfbb33a64f95bcfdf46f8a35c342177886bb594 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:27:24 2013 +0800 ec/google: Support Google's Chrome EC on I2C interface. Google's Chrome EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: http://review.coreboot.org/3074 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Apr 15 17:41:57 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Apr 16 00:32:49 2013, giving +2 See http://review.coreboot.org/3074 for details. -gerrit

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Patch merged into coreboot/master: 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments
by gerrit＠coreboot.org 16 Apr '13

16 Apr '13

the following patch was just integrated into master: commit 07e0f1bf1a2781102e6f6a242a7a97944b0f3ba0 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 13 15:58:03 2013 +0200 AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments When looking into possible reasons for a proposed revert [1], I noticed that the comments use four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER # manually squeeze whitespace in output […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. Luckily the compiler, at least gcc, warns about a wrong number of arguments, and therefore no incorrect code resulted from the wrong documentation. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3080 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Apr 15 13:06:59 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Tue Apr 16 00:14:11 2013, giving +2 See http://review.coreboot.org/3080 for details. -gerrit

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coreboot-gerrit April 2013