coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 8764b0e Fam14 DSDT: Also return for unrecognized UUID in _OSC
by gerrit＠coreboot.org 15 Apr '13

15 Apr '13

the following patch was just integrated into master: commit 8764b0e1c03c6934ebefd47fbe4dc26069911f3d Author: Mike Loptien <mike.loptien(a)se-eng.com> Date: Thu Apr 4 16:05:11 2013 -0600 Fam14 DSDT: Also return for unrecognized UUID in _OSC Fixing warnings introduced by the following patches: http://review.coreboot.org/#/c/2684/ http://review.coreboot.org/#/c/2739/ http://review.coreboot.org/#/c/2714/ These patches were meant to fix the dmesg warning about the OSC method not granting control appropriately. These patches then introduced warnings during the coreboot build process which were missed during the patch submission process. These warnings are below: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 15 2010] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1088 - ^ Not all control paths return a value (_OSC) dsdt.ramstage.asl 1143: Method(_OSC,4) Warning 1081 - ^ Reserved method must return a value (Buffer required for _OSC) ASL Input: dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations This patch gives the following compilation status: Intel ACPI Component Architecture ASL Optimizing Compiler version 20100528 [Oct 1 2012] Copyright (c) 2000 - 2010 Intel Corporation Supports ACPI Specification Revision 4.0a ASL Input: dsdt.ramstage.asl - 1732 lines, 33295 bytes, 941 keywords AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations The fix is simply adding an Else statement to the If which checks for the proper UUID. This way, all outcomes will return a full control package. This patch has no effect on the dmesg output. Change-Id: I8fa246400310b26679ffa3aa278069d2e9507160 Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Apr 10 21:54:20 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 15 23:42:34 2013, giving +2 See http://review.coreboot.org/3052 for details. -gerrit

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Patch merged into coreboot/master: 17c05f2 inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow
by gerrit＠coreboot.org 15 Apr '13

15 Apr '13

the following patch was just integrated into master: commit 17c05f23e215ff741bfc3fa611d7d2087198c3c1 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Apr 3 10:00:33 2013 +0200 inteltool: pcie.c: Use `0xffULL` instead of `0xff` to avoid shift overflow When building inteltool with Clang, it warns about the following. $ clang --version Debian clang version 3.2-1~exp6 (tags/RELEASE_32/final) (based on LLVM 3.2) Target: i386-pc-linux-gnu Thread model: posix $ CC=clang make […] clang -O2 -g -Wall -W -c -o pcie.o pcie.c pcie.c:297:40: warning: signed shift result (0xFF0000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0xff << 28); ~~~~ ^ ~~ pcie.c:301:41: warning: signed shift result (0xFF8000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0x1ff << 27); ~~~~~ ^ ~~ pcie.c:305:41: warning: signed shift result (0xFFC000000) requires 37 bits to represent, but 'int' only has 32 bits [-Wshift-overflow] pciexbar_phys = pciexbar_reg & (0x3ff << 26); ~~~~~ ^ ~~ 3 warnings generated. […] Specifying the length by using the suffix `0xffULL` fixes these issues as now enough bits are available. These issues were introduced in commit 1162f25a [1]. commit 1162f25a49e8f39822123d664cda10fef466b351 Author: Stefan Reinauer <stepan(a)coresystems.de> Date: Thu Dec 4 15:18:20 2008 +0000 Patch to util/inteltool: * PMBASE dumping now knows the registers. * Add support for i965, i975, ICH8M * Add support for Darwin OS using DirectIO [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=1162f25a49e8f39… Change-Id: I7b9a15b04ef3bcae64e06266667597d0f9f07b79 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3015 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Apr 15 12:16:10 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Mon Apr 15 19:03:19 2013, giving +2 See http://review.coreboot.org/3015 for details. -gerrit

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Patch set updated for coreboot: 91cdf23 ec/google: Support Google's Chrome EC on I2C interface.
by Hung-Te Lin 15 Apr '13

15 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3074 -gerrit commit 91cdf23e5449dd78f3cbf8bcef93ee64156b22b0 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:27:24 2013 +0800 ec/google: Support Google's Chrome EC on I2C interface. Google's Chrome EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 20 ++++- src/ec/google/chromeec/Makefile.inc | 3 + src/ec/google/chromeec/ec.c | 9 ++ src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_i2c.c | 159 ++++++++++++++++++++++++++++++++++++ src/mainboard/google/snow/Kconfig | 7 +- 6 files changed, 196 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index ce96da7..c3f0499 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -10,9 +10,25 @@ config EC_GOOGLE_API_ROOT help Path to the ec API file (ec/ec_commands.h). +config EC_GOOGLE_CHROMEEC_I2C + depends on EC_GOOGLE_CHROMEEC && !EC_GOOGLE_CHROMEEC_LPC + bool + default y + help + Google's Chrome EC via I2C bus. + +config EC_GOOGLE_CHROMEEC_I2C_BUS + depends on EC_GOOGLE_CHROMEEC_I2C + hex "I2C bus for Google's Chrome EC" + +config EC_GOOGLE_CHROMEEC_I2C_CHIP + depends on EC_GOOGLE_CHROMEEC_I2C + hex + default 0x1e + config EC_GOOGLE_CHROMEEC_LPC - depends on EC_GOOGLE_CHROMEEC + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. bool - default y if ARCH_X86 + default y help Google Chrome EC via LPC bus. diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 5fb258f..5bc9268 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,8 +1,11 @@ ramstage-y += ec.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c smm-y += ec.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-y += ec.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT)) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 42115be..d94338f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -33,6 +33,15 @@ #include "ec_commands.h" #include <vendorcode/google/chromeos/chromeos.h> +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) +{ + int csum; + + for (csum = 0; size > 0; data++, size--) + csum += *data; + return (uint8_t)(csum & 0xff); +} + int google_chromeec_kbbacklight(int percent) { struct chromeec_command cec_cmd; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f7512d7..3eb555c 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -33,6 +33,7 @@ u16 google_chromeec_get_board_version(void); void google_chromeec_init(void); #endif +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u32 google_chromeec_get_events_b(void); int google_chromeec_kbbacklight(int percent); void google_chromeec_post(u8 postcode); diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c new file mode 100644 index 0000000..a13dde6 --- /dev/null +++ b/src/ec/google/chromeec/ec_i2c.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <string.h> +#include "ec.h" +#include "ec_commands.h" + +/* Command (host->device) format for I2C: + * uint8_t version, cmd, len, data[len], checksum; + * + * Response (device->host) format for I2C: + * uint8_t response, len, data[len], checksum; + * + * Note the location of checksum is different from LPC protocol. + * + * The length is 8 bit so maximum data size is 0xff. + * Any I2C command should fit in 0xff + 4 bytes, and max response length + * is 0xff + 3 bytes. + */ +#define MAX_I2C_DATA_SIZE (0xff) + +typedef struct { + uint8_t version; + uint8_t command; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcCommandI2c; + +typedef struct { + uint8_t response; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcResponseI2c; + +static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) +{ +#ifdef TRACE_CHROMEEC + printk(BIOS_INFO, "i2c: bus=%d, chip=%#x, size=%d, data: ", bus, chip, + size); + while (size-- > 0) { + printk(BIOS_INFO, "%02X ", *data++); + } + printk(BIOS_INFO, "\n"); +#endif +} + +static int ec_verify_checksum(const EcResponseI2c *resp) +{ + size_t size = sizeof(*resp) - sizeof(resp->data) + resp->length; + uint8_t calculated = google_chromeec_calc_checksum( + (const uint8_t *)resp, size); + uint8_t received = resp->data[resp->length]; + if (calculated != received) { + printk(BIOS_ERR, "%s: Unmatch (rx: %#02x, calc: %#02x)\n", + __func__, received, calculated); + return 0; + } + return 1; +} + +static void ec_fill_checksum(EcCommandI2c *cmd) +{ + size_t size = sizeof(*cmd) - sizeof(cmd->data) + cmd->length; + cmd->data[cmd->length] = google_chromeec_calc_checksum( + (const uint8_t *)cmd, size); +} + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + EcCommandI2c cmd; + EcResponseI2c resp; + int bus = CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS; + int chip = CONFIG_EC_GOOGLE_CHROMEEC_I2C_CHIP; + size_t size_i2c_cmd = (sizeof(cmd) - sizeof(cmd.data) + + cec_command->cmd_size_in + 1), + size_i2c_resp = (sizeof(resp) - sizeof(resp.data) + + cec_command->cmd_size_out + 1); + + if (cec_command->cmd_size_in > MAX_I2C_DATA_SIZE || + cec_command->cmd_size_out > MAX_I2C_DATA_SIZE) { + printk(BIOS_ERR, "%s: Command data size too large (%d,%d)\n", + __func__, cec_command->cmd_size_in, + cec_command->cmd_size_out); + cec_command->cmd_code = EC_RES_INVALID_PARAM; + return 1; + } + + /* Construct command. */ + cmd.version = EC_CMD_VERSION0 + cec_command->cmd_version; + cmd.command = cec_command->cmd_code; + cmd.length = cec_command->cmd_size_in; + memcpy(cmd.data, cec_command->cmd_data_in, cmd.length); + ec_fill_checksum(&cmd); + + /* Start I2C communication */ + i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd); + if (i2c_write(bus, chip, 0, 0, (uint8_t *)&cmd, size_i2c_cmd) != 0) { + printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + if (i2c_read(bus, chip, 0, 0, (uint8_t *)&resp, size_i2c_resp) != 0) { + printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + + /* Verify and return response */ + cec_command->cmd_code = resp.response; + if (resp.response != EC_RES_SUCCESS) { + printk(BIOS_DEBUG, "%s: Received bad result code %d\n", + __func__, (int)resp.response); + return 1; + } + if (resp.length > cec_command->cmd_size_out) { + printk(BIOS_ERR, "%s: Received len %#02x too large\n", + __func__, (int)resp.length); + cec_command->cmd_code = EC_RES_INVALID_RESPONSE; + return 1; + } + if (!ec_verify_checksum(&resp)) { + cec_command->cmd_code = EC_RES_INVALID_CHECKSUM; + return 1; + } + cec_command->cmd_size_out = resp.length; + memcpy(cec_command->cmd_data_out, resp.data, resp.length); + return 0; +} + +#ifndef __PRE_RAM__ +u8 google_chromeec_get_event(void) +{ + printk(BIOS_ERR, "%s: Not supported.\n", __func__); + return 0; +} +#endif diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index f070056..6d3d7c8 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -24,7 +24,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5 select HAVE_UART_MEMORY_MAPPED -# select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_I2C select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES @@ -106,6 +107,10 @@ config CONSOLE_SERIAL_UART_ADDRESS help Map the UART names to the respective MMIO address. +config EC_GOOGLE_CHROMEEC_I2C_BUS + hex + default 4 + ################################################################# # stuff from smdk5250.h # # FIXME: can we move some of these to exynos5250's Kconfig? #

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Patch set updated for coreboot: 1d7e8c7 ec/google: Move plug-n-play initialization to LPC protocol.
by Hung-Te Lin 15 Apr '13

15 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3089 -gerrit commit 1d7e8c7bdc083aef02755509fa90f8c0b67af174 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:06:32 2013 +0800 ec/google: Move plug-n-play initialization to LPC protocol. "Plug-n-play" is not supported on all platforms using Google's Chrome EC. For example, EC on I2C bus will need explicit configuration and initialization. So move the plug-n-play initialization to the LPC implementation. Verified by building Google/Link (with EC/LPC) successfully. Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/ec.c | 56 +++++++---------------------------------- src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_lpc.c | 49 ++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 47 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index d830529..42115be 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <arch/io.h> #include <delay.h> -#include <device/pnp.h> #ifndef __PRE_RAM__ #include <elog.h> #include <stdlib.h> @@ -235,26 +234,20 @@ int google_chromeec_hello(void) static int ec_image_type; /* Cached EC image type (ro or rw). */ -static void google_chromeec_init(device_t dev) +void google_chromeec_init(void) { struct chromeec_command cec_cmd; - struct ec_google_chromeec_config *conf = dev->chip_info; - struct ec_response_get_version lpcv_cmd; - - if (!dev->enabled) - return; + struct ec_response_get_version cec_resp = {{0}}; printk(BIOS_DEBUG, "Google Chrome EC: Initializing keyboard.\n"); - pc_keyboard_init(&conf->keyboard); google_chromeec_hello(); - memset(&lpcv_cmd, 0, sizeof(lpcv_cmd)); cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; - cec_cmd.cmd_data_out = &lpcv_cmd; + cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; - cec_cmd.cmd_size_out = sizeof(lpcv_cmd); + cec_cmd.cmd_size_out = sizeof(cec_resp); google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code) { @@ -262,16 +255,16 @@ static void google_chromeec_init(device_t dev) "Google Chrome EC: version command failed!\n"); } else { printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); - printk(BIOS_DEBUG, " ro: %s\n", lpcv_cmd.version_string_ro); - printk(BIOS_DEBUG, " rw: %s\n", lpcv_cmd.version_string_rw); + printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); + printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); printk(BIOS_DEBUG, " running image: %d\n", - lpcv_cmd.current_image); - ec_image_type = lpcv_cmd.current_image; + cec_resp.current_image); + ec_image_type = cec_resp.current_image; } if (cec_cmd.cmd_code || (recovery_mode_enabled() && - (lpcv_cmd.current_image != EC_IMAGE_RO))) { + (cec_resp.current_image != EC_IMAGE_RO))) { struct ec_params_reboot_ec reboot_ec; /* Reboot the EC and make it come back in RO mode */ reboot_ec.cmd = EC_REBOOT_COLD; @@ -290,37 +283,6 @@ static void google_chromeec_init(device_t dev) } -static void google_chromeec_read_resources(device_t dev) -{ - /* Nothing, but this function avoids an error on serial console. */ -} - -static void google_chromeec_enable_resources(device_t dev) -{ - /* Nothing, but this function avoids an error on serial console. */ -} - -static struct device_operations ops = { - .init = google_chromeec_init, - .read_resources = google_chromeec_read_resources, - .enable_resources = google_chromeec_enable_resources -}; - -static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } -}; - -static void enable_dev(device_t dev) -{ - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); -} - -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = enable_dev, -}; - int google_ec_running_ro(void) { return (ec_image_type == EC_IMAGE_RO); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c78560f..f7512d7 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -30,6 +30,7 @@ int google_chromeec_set_wake_mask(u32 mask); u8 google_chromeec_get_event(void); int google_ec_running_ro(void); u16 google_chromeec_get_board_version(void); +void google_chromeec_init(void); #endif u32 google_chromeec_get_events_b(void); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 6443592..4e8d3fb 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -18,9 +18,13 @@ */ #include <stdint.h> +#include <stdlib.h> + #include <console/console.h> #include <arch/io.h> #include <delay.h> +#include <device/pnp.h> +#include "chip.h" #include "ec.h" #include "ec_commands.h" @@ -180,6 +184,51 @@ int google_chromeec_command(struct chromeec_command *cec_command) } #ifndef __PRE_RAM__ + +#ifndef __SMM__ +static void lpc_ec_init(device_t dev) +{ + struct ec_google_chromeec_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + pc_keyboard_init(&conf->keyboard); + google_chromeec_init(); +} + +static void lpc_ec_read_resources(device_t dev) +{ + /* Nothing, but this function avoids an error on serial console. */ +} + +static void lpc_ec_enable_resources(device_t dev) +{ + /* Nothing, but this function avoids an error on serial console. */ +} + +static struct device_operations ops = { + .init = lpc_ec_init, + .read_resources = lpc_ec_read_resources, + .enable_resources = lpc_ec_enable_resources +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, 0, 0, { 0, 0 }, } +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("Google Chrome EC") + .enable_dev = enable_dev, +}; + +#endif /* __SMM__ */ + u8 google_chromeec_get_event(void) { if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) {

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Patch set updated for coreboot: 9f92813 ec/google: Support ChromeOS EC on I2C interface.
by Hung-Te Lin 15 Apr '13

15 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3074 -gerrit commit 9f92813ed077588a09aaf788440753e07d54b905 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:27:24 2013 +0800 ec/google: Support ChromeOS EC on I2C interface. ChromeOS EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 20 ++++- src/ec/google/chromeec/Makefile.inc | 3 + src/ec/google/chromeec/ec.c | 9 ++ src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_i2c.c | 159 ++++++++++++++++++++++++++++++++++++ src/mainboard/google/snow/Kconfig | 7 +- 6 files changed, 196 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index ce96da7..c3f0499 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -10,9 +10,25 @@ config EC_GOOGLE_API_ROOT help Path to the ec API file (ec/ec_commands.h). +config EC_GOOGLE_CHROMEEC_I2C + depends on EC_GOOGLE_CHROMEEC && !EC_GOOGLE_CHROMEEC_LPC + bool + default y + help + Google's Chrome EC via I2C bus. + +config EC_GOOGLE_CHROMEEC_I2C_BUS + depends on EC_GOOGLE_CHROMEEC_I2C + hex "I2C bus for Google's Chrome EC" + +config EC_GOOGLE_CHROMEEC_I2C_CHIP + depends on EC_GOOGLE_CHROMEEC_I2C + hex + default 0x1e + config EC_GOOGLE_CHROMEEC_LPC - depends on EC_GOOGLE_CHROMEEC + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. bool - default y if ARCH_X86 + default y help Google Chrome EC via LPC bus. diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 5fb258f..5bc9268 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,8 +1,11 @@ ramstage-y += ec.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c smm-y += ec.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-y += ec.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT)) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 42115be..d94338f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -33,6 +33,15 @@ #include "ec_commands.h" #include <vendorcode/google/chromeos/chromeos.h> +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) +{ + int csum; + + for (csum = 0; size > 0; data++, size--) + csum += *data; + return (uint8_t)(csum & 0xff); +} + int google_chromeec_kbbacklight(int percent) { struct chromeec_command cec_cmd; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f7512d7..3eb555c 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -33,6 +33,7 @@ u16 google_chromeec_get_board_version(void); void google_chromeec_init(void); #endif +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u32 google_chromeec_get_events_b(void); int google_chromeec_kbbacklight(int percent); void google_chromeec_post(u8 postcode); diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c new file mode 100644 index 0000000..a13dde6 --- /dev/null +++ b/src/ec/google/chromeec/ec_i2c.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <string.h> +#include "ec.h" +#include "ec_commands.h" + +/* Command (host->device) format for I2C: + * uint8_t version, cmd, len, data[len], checksum; + * + * Response (device->host) format for I2C: + * uint8_t response, len, data[len], checksum; + * + * Note the location of checksum is different from LPC protocol. + * + * The length is 8 bit so maximum data size is 0xff. + * Any I2C command should fit in 0xff + 4 bytes, and max response length + * is 0xff + 3 bytes. + */ +#define MAX_I2C_DATA_SIZE (0xff) + +typedef struct { + uint8_t version; + uint8_t command; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcCommandI2c; + +typedef struct { + uint8_t response; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcResponseI2c; + +static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) +{ +#ifdef TRACE_CHROMEEC + printk(BIOS_INFO, "i2c: bus=%d, chip=%#x, size=%d, data: ", bus, chip, + size); + while (size-- > 0) { + printk(BIOS_INFO, "%02X ", *data++); + } + printk(BIOS_INFO, "\n"); +#endif +} + +static int ec_verify_checksum(const EcResponseI2c *resp) +{ + size_t size = sizeof(*resp) - sizeof(resp->data) + resp->length; + uint8_t calculated = google_chromeec_calc_checksum( + (const uint8_t *)resp, size); + uint8_t received = resp->data[resp->length]; + if (calculated != received) { + printk(BIOS_ERR, "%s: Unmatch (rx: %#02x, calc: %#02x)\n", + __func__, received, calculated); + return 0; + } + return 1; +} + +static void ec_fill_checksum(EcCommandI2c *cmd) +{ + size_t size = sizeof(*cmd) - sizeof(cmd->data) + cmd->length; + cmd->data[cmd->length] = google_chromeec_calc_checksum( + (const uint8_t *)cmd, size); +} + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + EcCommandI2c cmd; + EcResponseI2c resp; + int bus = CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS; + int chip = CONFIG_EC_GOOGLE_CHROMEEC_I2C_CHIP; + size_t size_i2c_cmd = (sizeof(cmd) - sizeof(cmd.data) + + cec_command->cmd_size_in + 1), + size_i2c_resp = (sizeof(resp) - sizeof(resp.data) + + cec_command->cmd_size_out + 1); + + if (cec_command->cmd_size_in > MAX_I2C_DATA_SIZE || + cec_command->cmd_size_out > MAX_I2C_DATA_SIZE) { + printk(BIOS_ERR, "%s: Command data size too large (%d,%d)\n", + __func__, cec_command->cmd_size_in, + cec_command->cmd_size_out); + cec_command->cmd_code = EC_RES_INVALID_PARAM; + return 1; + } + + /* Construct command. */ + cmd.version = EC_CMD_VERSION0 + cec_command->cmd_version; + cmd.command = cec_command->cmd_code; + cmd.length = cec_command->cmd_size_in; + memcpy(cmd.data, cec_command->cmd_data_in, cmd.length); + ec_fill_checksum(&cmd); + + /* Start I2C communication */ + i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd); + if (i2c_write(bus, chip, 0, 0, (uint8_t *)&cmd, size_i2c_cmd) != 0) { + printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + if (i2c_read(bus, chip, 0, 0, (uint8_t *)&resp, size_i2c_resp) != 0) { + printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + + /* Verify and return response */ + cec_command->cmd_code = resp.response; + if (resp.response != EC_RES_SUCCESS) { + printk(BIOS_DEBUG, "%s: Received bad result code %d\n", + __func__, (int)resp.response); + return 1; + } + if (resp.length > cec_command->cmd_size_out) { + printk(BIOS_ERR, "%s: Received len %#02x too large\n", + __func__, (int)resp.length); + cec_command->cmd_code = EC_RES_INVALID_RESPONSE; + return 1; + } + if (!ec_verify_checksum(&resp)) { + cec_command->cmd_code = EC_RES_INVALID_CHECKSUM; + return 1; + } + cec_command->cmd_size_out = resp.length; + memcpy(cec_command->cmd_data_out, resp.data, resp.length); + return 0; +} + +#ifndef __PRE_RAM__ +u8 google_chromeec_get_event(void) +{ + printk(BIOS_ERR, "%s: Not supported.\n", __func__); + return 0; +} +#endif diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index f070056..6d3d7c8 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -24,7 +24,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_SAMSUNG_EXYNOS5 select HAVE_UART_MEMORY_MAPPED -# select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_I2C select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 # select HAVE_ACPI_TABLES @@ -106,6 +107,10 @@ config CONSOLE_SERIAL_UART_ADDRESS help Map the UART names to the respective MMIO address. +config EC_GOOGLE_CHROMEEC_I2C_BUS + hex + default 4 + ################################################################# # stuff from smdk5250.h # # FIXME: can we move some of these to exynos5250's Kconfig? #

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New patch to review for coreboot: 6911e50 AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI
by Siyuan Wang 15 Apr '13

15 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3090 -gerrit commit 6911e5032e2483eccc371c5f8e2d527e87780eee Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Apr 15 19:10:24 2013 +0800 AMD Parmer: change DdiList to ConnectorTypeDP to support DP and HDMI This patch is based on >>AMD Thatcher: ConnectorTypeDP supports both DP and HDMI<< (I23cf1c6) [1] I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. [1] http://review.coreboot.org/#/c/3088/ Change-Id: I291beff43609ecb68ece24939f2dbc7c08dd0374 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/PlatformGnbPcie.c | 28 +++++----------------------- 1 file changed, 5 insertions(+), 23 deletions(-) diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index acb9542..1de6b03 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -81,7 +81,7 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, /* DP1 to FCH */ { @@ -94,26 +94,8 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux3, Hdp3) */ - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3) }, - /* GFX Lane 15-12 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux4, Hdp4) - }, - /* GFX Lane 11-8 */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux5, Hdp5) - }, - /* GFX Lane 7-4 */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 20, 23), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux6, Hdp6) - } }; PCIe_COMPLEX_DESCRIPTOR Trinity = { @@ -158,7 +140,7 @@ OemCustomizeInitEarly ( /* */ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) + sizeof (PCIe_PORT_DESCRIPTOR) * 7 + - sizeof (PCIe_DDI_DESCRIPTOR)) * 6; + sizeof (PCIe_DDI_DESCRIPTOR)) * 3; AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; AllocHeapParams.Persist = HEAP_LOCAL_CACHE; @@ -189,12 +171,12 @@ OemCustomizeInitEarly ( LibAmdMemFill (TrinityPcieDdiPtr, 0, - sizeof (PCIe_DDI_DESCRIPTOR) * 6, + sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 6, &InitEarly->StdHeader); + LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr; ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;

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Patch set updated for coreboot: 2b09322 AMD Thatcher: ConnectorTypeDP supports both DP and HDMI
by Siyuan Wang 15 Apr '13

15 Apr '13

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3088 -gerrit commit 2b09322d06e64d7ae8871de4b9d729e8edffdc5d Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Apr 15 17:58:57 2013 +0800 AMD Thatcher: ConnectorTypeDP supports both DP and HDMI It seems that ConnectorTypeDP in DdiList supports both DP and HDMI monitors. I tested by DP monitor and HDMI monitor connected by passive DP->HDMI adapter. Video and audio are OK. Hot plugging is also supported. This commit partially reverts commit >>AMD Thatcher: Fix PCIE link issues<< (7f23aeb0) [1]. [1] http://review.coreboot.org/3011 Change-Id: I23cf1c69a8274f47daf56f1a12aafd88bad4a128 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index ade2840..9ab8a51 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -23,7 +23,6 @@ #include "heapManager.h" #include "PlatformGnbPcieComplex.h" #include "Filecode.h" -#include "Fch.h" #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -130,7 +129,6 @@ OemCustomizeInitEarly ( VOID *TrinityPcieComplexListPtr; VOID *TrinityPciePortPtr; VOID *TrinityPcieDdiPtr; - UINT8 Value; ALLOCATE_HEAP_PARAMS AllocHeapParams; @@ -177,13 +175,6 @@ OemCustomizeInitEarly ( LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof (PCIe_COMPLEX_DESCRIPTOR), &InitEarly->StdHeader); LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof (PCIe_PORT_DESCRIPTOR) * 7, &InitEarly->StdHeader); - - LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 50, &Value, &InitEarly->StdHeader); - if (!(Value & 0x80)) - DdiList[0].Ddi.ConnectorType = ConnectorTypeHDMI; - LibAmdMemRead (AccessWidth8, ACPI_MMIO_BASE + GPIO_BASE + 51, &Value, &InitEarly->StdHeader); - if (!(Value & 0x80)) - DdiList[1].Ddi.ConnectorType = ConnectorTypeHDMI; LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof (PCIe_DDI_DESCRIPTOR) * 3, &InitEarly->StdHeader); ((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;

1 0

Patch set updated for coreboot: 0648a25 ec/google: Support ChromeOS EC on I2C interface.
by Hung-Te Lin 15 Apr '13

15 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3074 -gerrit commit 0648a251ffa5ae928786bf265365893a361fa323 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:27:24 2013 +0800 ec/google: Support ChromeOS EC on I2C interface. ChromeOS EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 17 ++++ src/ec/google/chromeec/Makefile.inc | 3 + src/ec/google/chromeec/ec.c | 9 ++ src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_i2c.c | 159 ++++++++++++++++++++++++++++++++++++ 5 files changed, 189 insertions(+) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index ce96da7..4fb41e8 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -10,6 +10,23 @@ config EC_GOOGLE_API_ROOT help Path to the ec API file (ec/ec_commands.h). +config EC_GOOGLE_CHROMEEC_I2C + depends on EC_GOOGLE_CHROMEEC + bool + default y if ARCH_ARMV7 + help + Google Chrome EC via I2C bus. + +config EC_GOOGLE_CHROMEEC_I2C_BUS + depends on EC_GOOGLE_CHROMEEC_I2C + hex + default 4 + +config EC_GOOGLE_CHROMEEC_I2C_CHIP + depends on EC_GOOGLE_CHROMEEC_I2C + hex + default 0x1e + config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC bool diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 5fb258f..5bc9268 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,8 +1,11 @@ ramstage-y += ec.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c smm-y += ec.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-y += ec.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT)) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 42115be..d94338f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -33,6 +33,15 @@ #include "ec_commands.h" #include <vendorcode/google/chromeos/chromeos.h> +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) +{ + int csum; + + for (csum = 0; size > 0; data++, size--) + csum += *data; + return (uint8_t)(csum & 0xff); +} + int google_chromeec_kbbacklight(int percent) { struct chromeec_command cec_cmd; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f7512d7..3eb555c 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -33,6 +33,7 @@ u16 google_chromeec_get_board_version(void); void google_chromeec_init(void); #endif +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u32 google_chromeec_get_events_b(void); int google_chromeec_kbbacklight(int percent); void google_chromeec_post(u8 postcode); diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c new file mode 100644 index 0000000..f8e5177 --- /dev/null +++ b/src/ec/google/chromeec/ec_i2c.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <string.h> +#include "ec.h" +#include "ec_commands.h" + +/* Command (host->device) format for I2C: + * uint8_t version, cmd, len, data[len], checksum; + * + * Response (device->host) format for I2C: + * uint8_t response, len, data[len], checksum; + * + * Note the location of checksum is different from LPC protocol. + * + * The length is 8 bit so maximum data size is 0xff. + * Any I2C command should fit in 0xff + 4 bytes, and max response length + * is 0xff + 3 bytes. + */ +#define MAX_I2C_DATA_SIZE (0xff) + +typedef struct { + uint8_t version; + uint8_t command; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcCommandI2c; + +typedef struct { + uint8_t response; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcResponseI2c; + +static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) +{ +#ifdef TRACE_CHROMEEC + printk(BIOS_INFO, "i2c: bus=%d, chip=%#x, size=%d, data: ", bus, chip, + size); + while (size-- > 0) { + printk(BIOS_INFO, "%02X ", *data++); + } + printk(BIOS_INFO, "\n"); +#endif +} + +static int ec_verify_checksum(const EcResponseI2c *resp) +{ + size_t size = sizeof(*resp) - sizeof(resp->data) + resp->length; + uint8_t calculated = google_chromeec_calc_checksum( + (const uint8_t *)resp, size); + uint8_t received = resp->data[resp->length]; + if (calculated != received) { + printk(BIOS_ERR, "%s: unmatch (rx: %#02x, calc: %#02x)\n", + __func__, received, calculated); + return 0; + } + return 1; +} + +static void ec_fill_checksum(EcCommandI2c *cmd) +{ + size_t size = sizeof(*cmd) - sizeof(cmd->data) + cmd->length; + cmd->data[cmd->length] = google_chromeec_calc_checksum( + (const uint8_t *)cmd, size); +} + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + EcCommandI2c cmd; + EcResponseI2c resp; + int bus = CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS, + chip = CONFIG_EC_GOOGLE_CHROMEEC_I2C_CHIP; + size_t size_i2c_cmd = (sizeof(cmd) - sizeof(cmd.data) + + cec_command->cmd_size_in + 1), + size_i2c_resp = (sizeof(resp) - sizeof(resp.data) + + cec_command->cmd_size_out + 1); + + if (cec_command->cmd_size_in > MAX_I2C_DATA_SIZE || + cec_command->cmd_size_out > MAX_I2C_DATA_SIZE) { + printk(BIOS_ERR, "%s: command data size too large (%d,%d)\n", + __func__, cec_command->cmd_size_in, + cec_command->cmd_size_out); + cec_command->cmd_code = EC_RES_INVALID_PARAM; + return 1; + } + + /* Construct command. */ + cmd.version = EC_CMD_VERSION0 + cec_command->cmd_version; + cmd.command = cec_command->cmd_code; + cmd.length = cec_command->cmd_size_in; + memcpy(cmd.data, cec_command->cmd_data_in, cmd.length); + ec_fill_checksum(&cmd); + + /* Start I2C communication */ + i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd); + if (i2c_write(bus, chip, 0, 0, (uint8_t *)&cmd, size_i2c_cmd) != 0) { + printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:0x%x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + if (i2c_read(bus, chip, 0, 0, (uint8_t *)&resp, size_i2c_resp) != 0) { + printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:0x%x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + + /* Verify and return response */ + cec_command->cmd_code = resp.response; + if (resp.response != EC_RES_SUCCESS) { + printk(BIOS_DEBUG, "%s: Received bad result code %d\n", + __func__, (int)resp.response); + return 1; + } + if (resp.length > cec_command->cmd_size_out) { + printk(BIOS_ERR, "%s: Received len %#02x too large\n", + __func__, (int)resp.length); + cec_command->cmd_code = EC_RES_INVALID_RESPONSE; + return 1; + } + if (!ec_verify_checksum(&resp)) { + cec_command->cmd_code = EC_RES_INVALID_CHECKSUM; + return 1; + } + cec_command->cmd_size_out = resp.length; + memcpy(cec_command->cmd_data_out, resp.data, resp.length); + return 0; +} + +#ifndef __PRE_RAM__ +u8 google_chromeec_get_event(void) +{ + printk(BIOS_ERR, "%s: not supported.\n", __func__); + return 0; +} +#endif

1 0

New patch to review for coreboot: 4b040f8 ec/google: Move plug-n-play initialization to LPC protocol.
by Hung-Te Lin 15 Apr '13

15 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3089 -gerrit commit 4b040f81ba6e5b1503983663c00cfd7f39005bc1 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:06:32 2013 +0800 ec/google: Move plug-n-play initialization to LPC protocol. Plug-n-play device is not supported on every platform using ChromeOS EC. For example, EC on I2C bus will need explicit configuration and initialization. The plug-n-play initialization should be moved to LPC implementation. Verified by building Google/Link (with EC/LPC) successfully. Change-Id: I49e5943503fd5301aa2b2f8c1265f3813719d7e3 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/ec.c | 56 +++++++---------------------------------- src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_lpc.c | 49 ++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 47 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index d830529..42115be 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <arch/io.h> #include <delay.h> -#include <device/pnp.h> #ifndef __PRE_RAM__ #include <elog.h> #include <stdlib.h> @@ -235,26 +234,20 @@ int google_chromeec_hello(void) static int ec_image_type; /* Cached EC image type (ro or rw). */ -static void google_chromeec_init(device_t dev) +void google_chromeec_init(void) { struct chromeec_command cec_cmd; - struct ec_google_chromeec_config *conf = dev->chip_info; - struct ec_response_get_version lpcv_cmd; - - if (!dev->enabled) - return; + struct ec_response_get_version cec_resp = {{0}}; printk(BIOS_DEBUG, "Google Chrome EC: Initializing keyboard.\n"); - pc_keyboard_init(&conf->keyboard); google_chromeec_hello(); - memset(&lpcv_cmd, 0, sizeof(lpcv_cmd)); cec_cmd.cmd_code = EC_CMD_GET_VERSION; cec_cmd.cmd_version = 0; - cec_cmd.cmd_data_out = &lpcv_cmd; + cec_cmd.cmd_data_out = &cec_resp; cec_cmd.cmd_size_in = 0; - cec_cmd.cmd_size_out = sizeof(lpcv_cmd); + cec_cmd.cmd_size_out = sizeof(cec_resp); google_chromeec_command(&cec_cmd); if (cec_cmd.cmd_code) { @@ -262,16 +255,16 @@ static void google_chromeec_init(device_t dev) "Google Chrome EC: version command failed!\n"); } else { printk(BIOS_DEBUG, "Google Chrome EC: version:\n"); - printk(BIOS_DEBUG, " ro: %s\n", lpcv_cmd.version_string_ro); - printk(BIOS_DEBUG, " rw: %s\n", lpcv_cmd.version_string_rw); + printk(BIOS_DEBUG, " ro: %s\n", cec_resp.version_string_ro); + printk(BIOS_DEBUG, " rw: %s\n", cec_resp.version_string_rw); printk(BIOS_DEBUG, " running image: %d\n", - lpcv_cmd.current_image); - ec_image_type = lpcv_cmd.current_image; + cec_resp.current_image); + ec_image_type = cec_resp.current_image; } if (cec_cmd.cmd_code || (recovery_mode_enabled() && - (lpcv_cmd.current_image != EC_IMAGE_RO))) { + (cec_resp.current_image != EC_IMAGE_RO))) { struct ec_params_reboot_ec reboot_ec; /* Reboot the EC and make it come back in RO mode */ reboot_ec.cmd = EC_REBOOT_COLD; @@ -290,37 +283,6 @@ static void google_chromeec_init(device_t dev) } -static void google_chromeec_read_resources(device_t dev) -{ - /* Nothing, but this function avoids an error on serial console. */ -} - -static void google_chromeec_enable_resources(device_t dev) -{ - /* Nothing, but this function avoids an error on serial console. */ -} - -static struct device_operations ops = { - .init = google_chromeec_init, - .read_resources = google_chromeec_read_resources, - .enable_resources = google_chromeec_enable_resources -}; - -static struct pnp_info pnp_dev_info[] = { - { &ops, 0, 0, { 0, 0 }, } -}; - -static void enable_dev(device_t dev) -{ - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); -} - -struct chip_operations ec_google_chromeec_ops = { - CHIP_NAME("Google Chrome EC") - .enable_dev = enable_dev, -}; - int google_ec_running_ro(void) { return (ec_image_type == EC_IMAGE_RO); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index c78560f..f7512d7 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -30,6 +30,7 @@ int google_chromeec_set_wake_mask(u32 mask); u8 google_chromeec_get_event(void); int google_ec_running_ro(void); u16 google_chromeec_get_board_version(void); +void google_chromeec_init(void); #endif u32 google_chromeec_get_events_b(void); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 6443592..4e8d3fb 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -18,9 +18,13 @@ */ #include <stdint.h> +#include <stdlib.h> + #include <console/console.h> #include <arch/io.h> #include <delay.h> +#include <device/pnp.h> +#include "chip.h" #include "ec.h" #include "ec_commands.h" @@ -180,6 +184,51 @@ int google_chromeec_command(struct chromeec_command *cec_command) } #ifndef __PRE_RAM__ + +#ifndef __SMM__ +static void lpc_ec_init(device_t dev) +{ + struct ec_google_chromeec_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + pc_keyboard_init(&conf->keyboard); + google_chromeec_init(); +} + +static void lpc_ec_read_resources(device_t dev) +{ + /* Nothing, but this function avoids an error on serial console. */ +} + +static void lpc_ec_enable_resources(device_t dev) +{ + /* Nothing, but this function avoids an error on serial console. */ +} + +static struct device_operations ops = { + .init = lpc_ec_init, + .read_resources = lpc_ec_read_resources, + .enable_resources = lpc_ec_enable_resources +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, 0, 0, { 0, 0 }, } +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), + pnp_dev_info); +} + +struct chip_operations ec_google_chromeec_ops = { + CHIP_NAME("Google Chrome EC") + .enable_dev = enable_dev, +}; + +#endif /* __SMM__ */ + u8 google_chromeec_get_event(void) { if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) {

1 0

Patch set updated for coreboot: 7cc4178 ec/google: Support ChromeOS EC in I2C interface.
by Hung-Te Lin 15 Apr '13

15 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3074 -gerrit commit 7cc417838cb5c3a1ff124800712c6094c1ce7c48 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Apr 15 18:27:24 2013 +0800 ec/google: Support ChromeOS EC in I2C interface. Adds I2C protocol for ChromeOS EC. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 17 ++++ src/ec/google/chromeec/Makefile.inc | 3 + src/ec/google/chromeec/ec.c | 9 ++ src/ec/google/chromeec/ec.h | 1 + src/ec/google/chromeec/ec_i2c.c | 159 ++++++++++++++++++++++++++++++++++++ 5 files changed, 189 insertions(+) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index ce96da7..4fb41e8 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -10,6 +10,23 @@ config EC_GOOGLE_API_ROOT help Path to the ec API file (ec/ec_commands.h). +config EC_GOOGLE_CHROMEEC_I2C + depends on EC_GOOGLE_CHROMEEC + bool + default y if ARCH_ARMV7 + help + Google Chrome EC via I2C bus. + +config EC_GOOGLE_CHROMEEC_I2C_BUS + depends on EC_GOOGLE_CHROMEEC_I2C + hex + default 4 + +config EC_GOOGLE_CHROMEEC_I2C_CHIP + depends on EC_GOOGLE_CHROMEEC_I2C + hex + default 0x1e + config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC bool diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 5fb258f..5bc9268 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,8 +1,11 @@ ramstage-y += ec.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c smm-y += ec.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-y += ec.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT)) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 42115be..d94338f 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -33,6 +33,15 @@ #include "ec_commands.h" #include <vendorcode/google/chromeos/chromeos.h> +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size) +{ + int csum; + + for (csum = 0; size > 0; data++, size--) + csum += *data; + return (uint8_t)(csum & 0xff); +} + int google_chromeec_kbbacklight(int percent) { struct chromeec_command cec_cmd; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f7512d7..3eb555c 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -33,6 +33,7 @@ u16 google_chromeec_get_board_version(void); void google_chromeec_init(void); #endif +uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size); u32 google_chromeec_get_events_b(void); int google_chromeec_kbbacklight(int percent); void google_chromeec_post(u8 postcode); diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c new file mode 100644 index 0000000..f8e5177 --- /dev/null +++ b/src/ec/google/chromeec/ec_i2c.c @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <string.h> +#include "ec.h" +#include "ec_commands.h" + +/* Command (host->device) format for I2C: + * uint8_t version, cmd, len, data[len], checksum; + * + * Response (device->host) format for I2C: + * uint8_t response, len, data[len], checksum; + * + * Note the location of checksum is different from LPC protocol. + * + * The length is 8 bit so maximum data size is 0xff. + * Any I2C command should fit in 0xff + 4 bytes, and max response length + * is 0xff + 3 bytes. + */ +#define MAX_I2C_DATA_SIZE (0xff) + +typedef struct { + uint8_t version; + uint8_t command; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcCommandI2c; + +typedef struct { + uint8_t response; + uint8_t length; + uint8_t data[MAX_I2C_DATA_SIZE + 1]; +} EcResponseI2c; + +static inline void i2c_dump(int bus, int chip, const uint8_t *data, size_t size) +{ +#ifdef TRACE_CHROMEEC + printk(BIOS_INFO, "i2c: bus=%d, chip=%#x, size=%d, data: ", bus, chip, + size); + while (size-- > 0) { + printk(BIOS_INFO, "%02X ", *data++); + } + printk(BIOS_INFO, "\n"); +#endif +} + +static int ec_verify_checksum(const EcResponseI2c *resp) +{ + size_t size = sizeof(*resp) - sizeof(resp->data) + resp->length; + uint8_t calculated = google_chromeec_calc_checksum( + (const uint8_t *)resp, size); + uint8_t received = resp->data[resp->length]; + if (calculated != received) { + printk(BIOS_ERR, "%s: unmatch (rx: %#02x, calc: %#02x)\n", + __func__, received, calculated); + return 0; + } + return 1; +} + +static void ec_fill_checksum(EcCommandI2c *cmd) +{ + size_t size = sizeof(*cmd) - sizeof(cmd->data) + cmd->length; + cmd->data[cmd->length] = google_chromeec_calc_checksum( + (const uint8_t *)cmd, size); +} + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + EcCommandI2c cmd; + EcResponseI2c resp; + int bus = CONFIG_EC_GOOGLE_CHROMEEC_I2C_BUS, + chip = CONFIG_EC_GOOGLE_CHROMEEC_I2C_CHIP; + size_t size_i2c_cmd = (sizeof(cmd) - sizeof(cmd.data) + + cec_command->cmd_size_in + 1), + size_i2c_resp = (sizeof(resp) - sizeof(resp.data) + + cec_command->cmd_size_out + 1); + + if (cec_command->cmd_size_in > MAX_I2C_DATA_SIZE || + cec_command->cmd_size_out > MAX_I2C_DATA_SIZE) { + printk(BIOS_ERR, "%s: command data size too large (%d,%d)\n", + __func__, cec_command->cmd_size_in, + cec_command->cmd_size_out); + cec_command->cmd_code = EC_RES_INVALID_PARAM; + return 1; + } + + /* Construct command. */ + cmd.version = EC_CMD_VERSION0 + cec_command->cmd_version; + cmd.command = cec_command->cmd_code; + cmd.length = cec_command->cmd_size_in; + memcpy(cmd.data, cec_command->cmd_data_in, cmd.length); + ec_fill_checksum(&cmd); + + /* Start I2C communication */ + i2c_dump(bus, chip, (const uint8_t *)&cmd, size_i2c_cmd); + if (i2c_write(bus, chip, 0, 0, (uint8_t *)&cmd, size_i2c_cmd) != 0) { + printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:0x%x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + if (i2c_read(bus, chip, 0, 0, (uint8_t *)&resp, size_i2c_resp) != 0) { + printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:0x%x\n", + __func__, bus, chip); + cec_command->cmd_code = EC_RES_ERROR; + return 1; + } + + /* Verify and return response */ + cec_command->cmd_code = resp.response; + if (resp.response != EC_RES_SUCCESS) { + printk(BIOS_DEBUG, "%s: Received bad result code %d\n", + __func__, (int)resp.response); + return 1; + } + if (resp.length > cec_command->cmd_size_out) { + printk(BIOS_ERR, "%s: Received len %#02x too large\n", + __func__, (int)resp.length); + cec_command->cmd_code = EC_RES_INVALID_RESPONSE; + return 1; + } + if (!ec_verify_checksum(&resp)) { + cec_command->cmd_code = EC_RES_INVALID_CHECKSUM; + return 1; + } + cec_command->cmd_size_out = resp.length; + memcpy(cec_command->cmd_data_out, resp.data, resp.length); + return 0; +} + +#ifndef __PRE_RAM__ +u8 google_chromeec_get_event(void) +{ + printk(BIOS_ERR, "%s: not supported.\n", __func__); + return 0; +} +#endif

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coreboot-gerrit April 2013