coreboot-gerrit April 2013

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New patch to review for coreboot: 6fcd373 AMD AGESA: Correct argument list for in comment
by Paul Menzel 13 Apr '13

13 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3080 -gerrit commit 6fcd373e7c1ffa0577f5e61418b69e55a7c93ac8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Apr 13 15:58:03 2013 +0200 AMD AGESA: Correct argument list for in comment When looking into possible reasons for a proposed revert [1], I noticed that the comments have four arguments for `PCIE_DDI_DATA_INITIALIZER`, but the actual definition only uses three. $ git grep -A1 PCIE_DDI_DATA_INITIALIZER […] -- src/vendorcode/amd/agesa/f10/AGESA.h:#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ src/vendorcode/amd/agesa/f10/AGESA.h-{mConnectorType, mAuxIndex, mHpdIndex} -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * }, -- src/vendorcode/amd/agesa/f10/AGESA.h: * PCIE_DDI_DATA_INITIALIZER (ConnectorType src/vendorcode/amd/agesa/f10/AGESA.h- * } -- […] So remove the fourth argument in the comments. [1] http://review.coreboot.org/#/c/3077/ Change-Id: I3e5a02c66a23af1eb2d86be8dbc7aaa3e5cea05e Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/AGESA.h | 4 ++-- src/vendorcode/amd/agesa/f14/AGESA.h | 4 ++-- src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h | 12 ++++++------ src/vendorcode/amd/agesa/f15/AGESA.h | 4 ++-- src/vendorcode/amd/agesa/f15/Include/GnbPage.h | 12 ++++++------ src/vendorcode/amd/agesa/f15tn/AGESA.h | 4 ++-- src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h | 12 ++++++------ 7 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/AGESA.h b/src/vendorcode/amd/agesa/f10/AGESA.h index c50086d..e6f5cfb 100644 --- a/src/vendorcode/amd/agesa/f10/AGESA.h +++ b/src/vendorcode/amd/agesa/f10/AGESA.h @@ -792,13 +792,13 @@ typedef struct { * { * 0, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) * }, * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) * } * }; * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 3333976..2a9bed1 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -905,13 +905,13 @@ typedef struct { * { * 0, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) * }, * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) * } * }; * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h index fec1603..ecc9ca6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/GnbPage.h @@ -121,7 +121,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. @@ -129,7 +129,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. @@ -137,7 +137,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. @@ -145,7 +145,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. @@ -153,7 +153,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. @@ -161,7 +161,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * @endcode diff --git a/src/vendorcode/amd/agesa/f15/AGESA.h b/src/vendorcode/amd/agesa/f15/AGESA.h index b18659e..6b0171b 100644 --- a/src/vendorcode/amd/agesa/f15/AGESA.h +++ b/src/vendorcode/amd/agesa/f15/AGESA.h @@ -1173,13 +1173,13 @@ typedef struct { * { * 0, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) * }, * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) * } * }; * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { diff --git a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h index 2ccdfc5..b571128 100644 --- a/src/vendorcode/amd/agesa/f15/Include/GnbPage.h +++ b/src/vendorcode/amd/agesa/f15/Include/GnbPage.h @@ -139,7 +139,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. @@ -147,7 +147,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. @@ -155,7 +155,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. @@ -163,7 +163,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. @@ -171,7 +171,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. @@ -179,7 +179,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * @endcode diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index fdd02df..9bd2e88 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -1299,13 +1299,13 @@ typedef struct { * { * 0, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) * }, * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) * } * }; * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { diff --git a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h index 9c051c5..aae2e40 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/GnbPage.h @@ -166,7 +166,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 32), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on dedicated display lanes. DP0_TXP/N[0]..DP0_TXP/N[3] - master, DP1_TXP/N[0]..DP1_TXP/N[3] - slave. @@ -174,7 +174,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 24), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - master, P_GFX_TXP/N[4]..P_GFX_TXP/N[7] - slave. @@ -182,7 +182,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 15), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[7]..P_GFX_TXP/N[4] - master, P_GFX_TXP/N[0]..P_GFX_TXP/N[3] - slave. @@ -190,7 +190,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 15, 8), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - master, P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - slave. @@ -198,7 +198,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 23), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * // Dual Link DVI on PCIe lanes. P_GFX_TXP/N[12]..P_GFX_TXP/N[15] - master, P_GFX_TXP/N[8]..P_GFX_TXP/N[11] - slave. @@ -206,7 +206,7 @@ * { * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 23, 16), - * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1, 0) + * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDualLinkDvi, Aux1, Hdp1) * } * } * @endcode

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Patch merged into coreboot/master: cd4c8c1 exynos5/snow: remove wait_ms arg from dp_controller_init()
by gerrit＠coreboot.org 13 Apr '13

13 Apr '13

the following patch was just integrated into master: commit cd4c8c1e0e9049b264bdbe62e9f2192dee8c3d31 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 16:02:44 2013 -0700 exynos5/snow: remove wait_ms arg from dp_controller_init() This removes the wait_ms argument from the dp_controller_init(). The only delay involved is a constant 60ms delay that happens if everything else goes well. This delay is derived from the LCD spec so there's no reason it should be baked into the controller code. (This patch also has the side-effect of fixing a bug where we were delaying on an undefined value for wait_ms). Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/3078 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Sat Apr 13 03:37:24 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Sat Apr 13 05:12:18 2013, giving +2 See http://review.coreboot.org/3078 for details. -gerrit

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New patch to review for coreboot: b88fe21 armv7/exynos5250: Deprecate sdelay in favor of udelay
by David Hendricks 13 Apr '13

13 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3079 -gerrit commit b88fe21f723f8c3d192b383e7ddc9e6d57cfb9e9 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 15:11:05 2013 -0700 armv7/exynos5250: Deprecate sdelay in favor of udelay This gets rid of the clock-tick based sdelay in favor of udelay(). udelay() is more consistent and easier to work with, and this allows us to carry one less variation of timers (and headers and sources...). Every 1 unit in the sdelay() argument was assumed to cause a delay of 2 clock ticks (@1.7GHz). So the conversion factor is roughly: sdelay(N) = udelay(((N * 2) / 1.7 * 10^9) * 10^6) = udelay((N * 2) / (1.7 * 10^3)) The sdelay() periods used were: sdelay(100) --> udelay(1) sdelay(0x10000) --> udelay(78) (rounded up to udelay(100)) There was one instance of sdelay(10000), which looked like sort of a typo since sdelay(0x10000) was used elsewhere. sdelay(10000) should approximate to about 12us, so we'll stick with that for now and leave a note. Change-Id: I5e7407865ceafa701eea1d613bbe50cf4734f33e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/arch/armv7/bootblock.inc | 2 -- src/arch/armv7/include/system.h | 26 -------------------- src/arch/armv7/lib/Makefile.inc | 1 - src/arch/armv7/lib/syslib.c | 39 ------------------------------ src/cpu/samsung/exynos5250/clock_init.c | 1 - src/cpu/samsung/exynos5250/dmc_common.c | 23 +++++++++++------- src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 7 ++++-- 7 files changed, 19 insertions(+), 80 deletions(-) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index 8db31b4..bac32e2 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -29,8 +29,6 @@ * MA 02111-1307 USA */ -#include <system.h> - .section ".bl1", "a", %progbits _bl1: /* For now we have to live with a first stage boot loader diff --git a/src/arch/armv7/include/system.h b/src/arch/armv7/include/system.h deleted file mode 100644 index 0643852..0000000 --- a/src/arch/armv7/include/system.h +++ /dev/null @@ -1,26 +0,0 @@ -/* FIXME(dhendrix): This is split out from asm/system.h. */ -#ifndef SYSTEM_H_ -#define SYSTEM_H_ - -/* - * This is used to ensure the compiler did actually allocate the register we - * asked it for some inline assembly sequences. Apparently we can't trust - * the compiler from one version to another so a bit of paranoia won't hurt. - * This string is meant to be concatenated with the inline asm string and - * will cause compilation to stop on mismatch. - * (for details, see gcc PR 15089) - */ -#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" - -#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); - -#define arch_align_stack(x) (x) - -#ifndef __ASSEMBLER__ - /* - * FIXME: sdelay originally came from arch/arm/cpu/armv7/exynos5/setup.h in - * u-boot but does not seem specific to exynos5... - */ -void sdelay(unsigned long loops); -#endif // __ASSEMBLY__ -#endif /* SYSTEM_H_ */ diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 0cb5737..b10c1ab 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -5,7 +5,6 @@ bootblock-y += cache.c romstage-y += cache.c romstage-y += div0.c -romstage-y += syslib.c romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c ramstage-y += div0.c diff --git a/src/arch/armv7/lib/syslib.c b/src/arch/armv7/lib/syslib.c deleted file mode 100644 index a6ed080..0000000 --- a/src/arch/armv7/lib/syslib.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments, <www.ti.com> - * - * Richard Woodruff <r-woodruff2(a)ti.com> - * Syed Mohammed Khasim <khasim(a)ti.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <arch/io.h> -#include <system.h> /* FIXME: dumping ground for prototypes */ - -/************************************************************ - * sdelay() - simple spin loop. Will be constant time as - * its generally used in bypass conditions only. This - * is necessary until timers are accessible. - * - * not inline to increase chances its in cache when called - *************************************************************/ -void sdelay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0"(loops)); -} - diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index c8479de..c94cadf 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -25,7 +25,6 @@ #include <delay.h> #include <stdlib.h> #include <types.h> -#include <system.h> #include <console/console.h> diff --git a/src/cpu/samsung/exynos5250/dmc_common.c b/src/cpu/samsung/exynos5250/dmc_common.c index 8c4b583..bcfc9fe 100644 --- a/src/cpu/samsung/exynos5250/dmc_common.c +++ b/src/cpu/samsung/exynos5250/dmc_common.c @@ -24,12 +24,11 @@ #include <arch/io.h> #include <assert.h> -#include <common.h> +#include <delay.h> #include <console/console.h> #include <cpu/samsung/exynos5250/setup.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/clock_init.h> -#include <system.h> #include "clock_init.h" #include "setup.h" @@ -75,7 +74,7 @@ int dmc_config_zq(struct mem_timings *mem, */ i = ZQ_INIT_TIMEOUT; while ((readl(&phy0_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { - sdelay(100); + udelay(1); i--; } if (!i) @@ -84,7 +83,7 @@ int dmc_config_zq(struct mem_timings *mem, i = ZQ_INIT_TIMEOUT; while ((readl(&phy1_ctrl->phy_con17) & ZQ_DONE) != ZQ_DONE && i > 0) { - sdelay(100); + udelay(1); i--; } if (!i) @@ -135,21 +134,27 @@ void dmc_config_mrs(struct mem_timings *mem, struct exynos5_dmc *dmc) * delays? This one and the next were not there for * DDR3. */ - sdelay(0x10000); + udelay(100); /* Sending EMRS/MRS commands */ for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) { writel(mem->direct_cmd_msr[i] | mask, &dmc->directcmd); - sdelay(0x10000); + udelay(100); } if (mem->send_zq_init) { /* Sending ZQINIT command */ writel(DIRECT_CMD_ZQINIT | mask, &dmc->directcmd); - - sdelay(10000); + /* + * FIXME: This was originally sdelay(10000) + * in the imported u-boot code. That may have + * been meant to be sdelay(0x10000) since that + * was used elsewhere in this function. Either + * way seems to work, though. + */ + udelay(12); } } } @@ -168,7 +173,7 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc) /* PALL (all banks precharge) CMD */ writel(DIRECT_CMD_PALL | mask, &dmc->directcmd); - sdelay(0x10000); + udelay(100); } } } diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c index 9a4ead0..5bb8a37 100644 --- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c +++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c @@ -23,12 +23,12 @@ */ #include <config.h> +#include <delay.h> #include <arch/io.h> #include <console/console.h> //#include "clock.h" /* FIXME(dhendrix): untangle clock/clk ... */ #include <cpu/samsung/exynos5-common/clock.h> -#include <system.h> #include "clk.h" #include "cpu.h" #include "dmc.h" @@ -44,6 +44,7 @@ static void reset_phy_ctrl(void) writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl); writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); +#if 0 /* * For proper memory initialization there should be a minimum delay of * 500us after the LPDDR3PHY_CTRL_PHY_RESET signal. @@ -56,6 +57,8 @@ static void reset_phy_ctrl(void) * TODO(hatim.rv(a)samsung.com): Implement the delay using timer/counter */ sdelay(425000); +#endif + udelay(500); } int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) @@ -236,7 +239,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) * TODO(waihong): Comment on how long this take to * timeout */ - sdelay(100); + udelay(1); i--; } if (!i){

1 0

Patch set updated for coreboot: 6a055d2 exynos5/snow: remove wait_ms arg from dp_controller_init()
by David Hendricks 13 Apr '13

13 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3078 -gerrit commit 6a055d2d3c13dabb1a1f33dbb099230d2290e74d Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 16:02:44 2013 -0700 exynos5/snow: remove wait_ms arg from dp_controller_init() This removes the wait_ms argument from the dp_controller_init(). The only delay involved is a constant 60ms delay that happens if everything else goes well. This delay is derived from the LCD spec so there's no reason it should be baked into the controller code. (This patch also has the side-effect of fixing a bug where we were delaying on an undefined value for wait_ms). Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 11 +---------- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 +- src/mainboard/google/snow/ramstage.c | 20 +++++++++++++------- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index b57e276..11d666b 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -505,7 +505,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* * Initialize DP display */ -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +int dp_controller_init(struct s5p_dp_device *dp_device) { int ret; struct s5p_dp_device *dp = dp_device; @@ -561,15 +561,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) return ret; } - /* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ - *wait_ms = 60; return 0; } diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 2988d5d..4df848d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int dp_controller_init(struct s5p_dp_device *dp_device); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* _S5P_DP_CORE_H */ diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index ad0266b..962c79b 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -139,6 +139,16 @@ static void exynos_dp_reset(void) udelay(300 * 1000); } +/* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ +#define LCD_T3_DELAY_MS 60 + #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 @@ -199,7 +209,6 @@ static struct video_info snow_dp_video_info = { static void mainboard_init(device_t dev) { int dp_tries; - unsigned int wait_ms; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &snow_dp_video_info, @@ -215,20 +224,17 @@ static void mainboard_init(device_t dev) exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { - if (wait_ms) { - udelay(wait_ms); - wait_ms = 0; - } - exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } - if (dp_controller_init(&dp_device, &wait_ms)) + if (dp_controller_init(&dp_device)) continue; + udelay(LCD_T3_DELAY_MS * 1000); + snow_backlight_vdd(); snow_backlight_pwm(); snow_backlight_en();

1 0

Patch set updated for coreboot: a79ad3e exynos5/snow: remove wait_ms arg from dp_controller_init()
by David Hendricks 13 Apr '13

13 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3078 -gerrit commit a79ad3ef6f8c10f141e9c796478649c4d9a68908 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 16:02:44 2013 -0700 exynos5/snow: remove wait_ms arg from dp_controller_init() This removes the wait_ms argument from the dp_controller_init(). The only delay involved is a constant 60ms delay that happens if everything else goes well. This delay is derived from the LCD spec so there's no reason it should be baked into the controller code. (This patch also has the side-effect of fixing a bug where we were delaying on an undefined value for wait_ms). Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 11 +---------- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 +- src/mainboard/google/snow/ramstage.c | 20 +++++++++++++------- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index b57e276..11d666b 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -505,7 +505,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* * Initialize DP display */ -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +int dp_controller_init(struct s5p_dp_device *dp_device) { int ret; struct s5p_dp_device *dp = dp_device; @@ -561,15 +561,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) return ret; } - /* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ - *wait_ms = 60; return 0; } diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 2988d5d..4df848d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int dp_controller_init(struct s5p_dp_device *dp_device); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* _S5P_DP_CORE_H */ diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index ad0266b..50295cd 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -139,6 +139,16 @@ static void exynos_dp_reset(void) udelay(300 * 1000); } +/* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ +#define LCD_T3_DELAY_MS 60 + #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 @@ -199,7 +209,6 @@ static struct video_info snow_dp_video_info = { static void mainboard_init(device_t dev) { int dp_tries; - unsigned int wait_ms; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &snow_dp_video_info, @@ -215,20 +224,17 @@ static void mainboard_init(device_t dev) exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { - if (wait_ms) { - udelay(wait_ms); - wait_ms = 0; - } - exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } - if (dp_controller_init(&dp_device, &wait_ms)) + if (dp_controller_init(&dp_device)) continue; + udelay(LCD_T3_DELAY_MS * 1000): + snow_backlight_vdd(); snow_backlight_pwm(); snow_backlight_en();

1 0

New patch to review for coreboot: 561be97 exynos5/snow: remove wait_ms arg from dp_controller_init()
by David Hendricks 13 Apr '13

13 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3078 -gerrit commit 561be97b37e76395110cb9cc17b7de3beb120e71 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 16:02:44 2013 -0700 exynos5/snow: remove wait_ms arg from dp_controller_init() This removes the wait_ms argument from the dp_controller_init(). The only delay involved is a constant 60ms delay that happens if everything else goes well. This delay is derived from the LCD spec so there's no reason it should be baked into the controller code. (This patch also has the side-effect of fixing a bug where we were delaying on an undefined value for wait_ms). Change-Id: I03aa19f2ac2f720524fcb7c795e10cc57f0a226e Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 11 +---------- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 +- src/mainboard/google/snow/ramstage.c | 19 ++++++++++++------- 3 files changed, 14 insertions(+), 18 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index b57e276..11d666b 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -505,7 +505,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* * Initialize DP display */ -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +int dp_controller_init(struct s5p_dp_device *dp_device) { int ret; struct s5p_dp_device *dp = dp_device; @@ -561,15 +561,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) return ret; } - /* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ - *wait_ms = 60; return 0; } diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 2988d5d..4df848d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int dp_controller_init(struct s5p_dp_device *dp_device); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* _S5P_DP_CORE_H */ diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index ad0266b..718bb27 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -139,6 +139,7 @@ static void exynos_dp_reset(void) udelay(300 * 1000); } +#define LCD_T3_DELAY_MS 60 #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 @@ -199,7 +200,6 @@ static struct video_info snow_dp_video_info = { static void mainboard_init(device_t dev) { int dp_tries; - unsigned int wait_ms; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &snow_dp_video_info, @@ -215,20 +215,25 @@ static void mainboard_init(device_t dev) exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { - if (wait_ms) { - udelay(wait_ms); - wait_ms = 0; - } - exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } - if (dp_controller_init(&dp_device, &wait_ms)) + if (dp_controller_init(&dp_device)) continue; + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + udelay(LCD_T3_DELAY_MS * 1000); + snow_backlight_vdd(); snow_backlight_pwm(); snow_backlight_en();

1 0

Patch merged into coreboot/master: c0b972f Exynos5250: add a microsecond timer
by gerrit＠coreboot.org 13 Apr '13

13 Apr '13

the following patch was just integrated into master: commit c0b972f60dbd1a3dadfc568b5245c6b0ee6df559 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/3073 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Sat Apr 13 00:39:01 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Fri Apr 12 22:35:04 2013, giving +2 See http://review.coreboot.org/3073 for details. -gerrit

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New patch to review for coreboot: fc47bfa Revert "AMD f14 vendorcode: Fix warning"
by thomas dylst 12 Apr '13

12 Apr '13

thomas dylst (dylst3(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3077 -gerrit commit fc47bfaf6b755b1103a0a84e64a5eb5204b60cd6 Author: thomas dylst <dylst3(a)gmail.com> Date: Fri Apr 12 22:59:11 2013 +0200 Revert "AMD f14 vendorcode: Fix warning" This reverts commit e533f daa5902d228c4db694db390113b437a9777 Change-Id: I2cf24e813be26cb8de8408dcd0fcdcadbf08d569 --- src/vendorcode/amd/agesa/f14/AGESA.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/AGESA.h b/src/vendorcode/amd/agesa/f14/AGESA.h index 3333976..5eaa638 100644 --- a/src/vendorcode/amd/agesa/f14/AGESA.h +++ b/src/vendorcode/amd/agesa/f14/AGESA.h @@ -813,7 +813,7 @@ typedef enum { #define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \ {mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap} } #define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ -{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}} +{mConnectorType, mAuxIndex, mHpdIndex, {0, 0}} #define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1) \ {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}}

1 0

Patch set updated for coreboot: baa285c Exynos5250: add a microsecond timer
by Ronald G. Minnich 12 Apr '13

12 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit baa285c6846458f7669cc14ae02f8f15ddd013c7 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 ++-- src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clk.h | 5 ++ src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 117 ++++++++++++++++++++++++++++++++ src/include/time.h | 26 +++++++ src/mainboard/google/snow/bootblock.c | 6 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 169 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index dbddce0..4785894 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -25,6 +25,11 @@ #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/pinmux.h> + +#define MCT_ADDRESS 0x101c0000 + +#define MCT_HZ 24000000 + /* * Set mshci controller instances clock drivder * diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..ddabbf7 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,117 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> +#include "clk.h" + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + static uint32_t ticks_per_microsecond = MCT_HZ/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..2cfcb35 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +void timer_start(void); +u32 timer_us(void); + +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..d2e0b50 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -28,6 +29,11 @@ void bootblock_mainboard_init(void); void bootblock_mainboard_init(void) { + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); + exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE); #if CONFIG_EARLY_CONSOLE exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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Patch set updated for coreboot: 852344a exynos5250/snow: debugging display bring-up
by David Hendricks 12 Apr '13

12 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3076 -gerrit commit 852344a67335a3fa65b1332500b0956285bc9465 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 12:53:15 2013 -0700 exynos5250/snow: debugging display bring-up ** do not submit ** This is just a WIP patch with loads of extra debug prints. Any functional changes will be split out into other patches. Change-Id: I275e646d30d291323f3ace602cac8d3ea76af2f0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 28 +++++++++++++++-------- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 +- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 11 +++++++-- src/mainboard/google/snow/ramstage.c | 34 ++++++++++++++-------------- 4 files changed, 45 insertions(+), 30 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index b57e276..0cce458 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -207,6 +208,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } +#if 0 start = get_timer(0); do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { @@ -219,6 +221,21 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, printk(BIOS_DEBUG, "Video Clock Not ok\n"); return -ERR_VIDEO_CLOCK_BAD; } +#endif + int not_fucked = 0; + start = timer_us(); + while (timer_us() < start + (STREAM_ON_TIMEOUT * 1000)) { + if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { + not_fucked = 1; + break; + } + } + + if (!not_fucked) { + printk(BIOS_DEBUG, "Video Clock Not ok, we are still fucked.\n"); + return -ERR_VIDEO_CLOCK_BAD; + } + /* Set to use the register calculated M/N video */ s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); @@ -505,7 +522,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* * Initialize DP display */ -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +int dp_controller_init(struct s5p_dp_device *dp_device) { int ret; struct s5p_dp_device *dp = dp_device; @@ -561,15 +578,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) return ret; } - /* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ - *wait_ms = 60; return 0; } diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 2988d5d..4df848d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int dp_controller_init(struct s5p_dp_device *dp_device); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* _S5P_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..0c6b214 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -184,12 +184,13 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) while (!(reg & RPLY_RECEIV)) reg = readl(&base->dp_int_sta); + printk(BIOS_DEBUG, "%s: checkpoint 1, dp_int_sta: 0x%08x\n", __func__, reg); /* Clear interrupt source for AUX CH command reply */ writel(RPLY_RECEIV, &base->dp_int_sta); /* Clear interrupt source for AUX CH access error */ reg = readl(&base->dp_int_sta); - printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg); + printk(BIOS_DEBUG, "%s: checkpoint 2, dp_int_sta: 0x%08x\n", __func__, reg); if (reg & AUX_ERR) { writel(AUX_ERR, &base->dp_int_sta); return -1; @@ -203,6 +204,8 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) return -1; } + printk(BIOS_DEBUG, "%s: done, dp_int_sta: 0x%08x, aux_ch_sta: 0x%08x\n", + __func__, reg, readl(&base->aux_ch_sta)); return 0; } @@ -356,8 +359,10 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_1); - if (!(reg & DET_STA)) + if (!(reg & DET_STA)) { + printk(BIOS_DEBUG, "%s: sys_ctl_1: 0x%08x\n", __func__, reg); return -1; + } reg = readl(&base->sys_ctl_2); writel(reg, &base->sys_ctl_2); @@ -365,10 +370,12 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_2); if (reg & CHA_STA) { + printk(BIOS_DEBUG, "%s: sys_ctl_2: 0x%08x\n", __func__, reg); printk(BIOS_DEBUG, "Input stream clk is changing\n"); return -1; } + printk(BIOS_DEBUG, "%s: done\n", __func__); return 0; } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index ad0266b..0bb264a 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -98,8 +98,6 @@ static void exynos_dp_bridge_setup(void) gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE); udelay(10); gpio_set_value(dp_rst_l, 1); - - udelay(90000); /* FIXME: this might be unnecessary */ } static void exynos_dp_bridge_init(void) @@ -116,19 +114,13 @@ static void exynos_dp_bridge_init(void) * roughly 50ms after PD is de-asserted. The phantom high * makes it hard for us to know when the NXP chip is up. */ - udelay(90000); /* FIXME: this might be unnecessary */ + udelay(90000); } static int exynos_dp_hotplug(void) { - int x = gpio_get_value(dp_hpd); /* Check HPD. If it's high, we're all good. */ -// if (gpio_get_value(dp_hpd)) -// return 0; - printk(BIOS_DEBUG, "%s: dp_hpd: 0x%02x\n", __func__, x); - if (x) - return 0; - return -1; + return gpio_get_value(dp_hpd) ? 0 : 1; } static void exynos_dp_reset(void) @@ -139,6 +131,7 @@ static void exynos_dp_reset(void) udelay(300 * 1000); } +#define LCD_T3_DELAY_MS 60 #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 @@ -199,7 +192,6 @@ static struct video_info snow_dp_video_info = { static void mainboard_init(device_t dev) { int dp_tries; - unsigned int wait_ms; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &snow_dp_video_info, @@ -215,20 +207,28 @@ static void mainboard_init(device_t dev) exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { - if (wait_ms) { - udelay(wait_ms); - wait_ms = 0; - } - exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } - if (dp_controller_init(&dp_device, &wait_ms)) + if (dp_controller_init(&dp_device)) continue; + printk(BIOS_INFO, "%s: DP controller init done, powering on " + "backlight\n", __func__); + + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + udelay(LCD_T3_DELAY_MS * 1000); + snow_backlight_vdd(); snow_backlight_pwm(); snow_backlight_en();

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coreboot-gerrit April 2013