coreboot-gerrit April 2013

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Patch set updated for coreboot: 6173bfe Exynos5250: add a microsecond timer
by David Hendricks 12 Apr '13

12 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit 6173bfe150d9bb51fe3dcc3d6c7f8e248e5aac7f Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 +++- src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clk.h | 5 ++ src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 126 ++++++++++++++++++++++++++++++++ src/include/time.h | 28 +++++++ src/mainboard/google/snow/bootblock.c | 5 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 179 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index dbddce0..4785894 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -25,6 +25,11 @@ #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/pinmux.h> + +#define MCT_ADDRESS 0x101c0000 + +#define MCT_HZ 24000000 + /* * Set mshci controller instances clock drivder * diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..047cb65 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,126 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> +#include "clk.h" + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +/* I would prefer not to export these for now. + * I think it's best if we keep the hardware + * API limited to timer_start and timer_us. + */ +static uint64_t timer_hz(void) +{ + return MCT_HZ; +} + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + uint32_t ticks_per_microsecond = timer_hz()/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..6bd9e08 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +#if !defined( __ROMCC__) + +void timer_start(void); +u32 timer_us(void); +#endif +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..a0fe72b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -34,4 +35,8 @@ void bootblock_mainboard_init(void) console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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New patch to review for coreboot: 8d0a39f exynos5250/snow: debugging display bring-up
by David Hendricks 12 Apr '13

12 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3076 -gerrit commit 8d0a39f5c2e2cb7d0fb58b39e756d15e7ca3a275 Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Apr 12 12:53:15 2013 -0700 exynos5250/snow: debugging display bring-up ** do not submit ** This is just a WIP patch with loads of extra debug prints. Any functional changes will be split out into other patches. Change-Id: I275e646d30d291323f3ace602cac8d3ea76af2f0 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/cpu/samsung/exynos5-common/exynos-fb.c | 28 +++++++++++++++-------- src/cpu/samsung/exynos5-common/s5p-dp-core.h | 2 +- src/cpu/samsung/exynos5-common/s5p-dp-reg.c | 11 +++++++-- src/mainboard/google/snow/ramstage.c | 34 ++++++++++++++-------------- 4 files changed, 45 insertions(+), 30 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5-common/exynos-fb.c index b57e276..0cce458 100644 --- a/src/cpu/samsung/exynos5-common/exynos-fb.c +++ b/src/cpu/samsung/exynos5-common/exynos-fb.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <stdlib.h> #include <string.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/power.h> @@ -207,6 +208,7 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, return -ERR_PLL_NOT_UNLOCKED; } +#if 0 start = get_timer(0); do { if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { @@ -219,6 +221,21 @@ static int s5p_dp_config_video(struct s5p_dp_device *dp, printk(BIOS_DEBUG, "Video Clock Not ok\n"); return -ERR_VIDEO_CLOCK_BAD; } +#endif + int not_fucked = 0; + start = timer_us(); + while (timer_us() < start + (STREAM_ON_TIMEOUT * 1000)) { + if (s5p_dp_is_slave_video_stream_clock_on(dp) == 0) { + not_fucked = 1; + break; + } + } + + if (!not_fucked) { + printk(BIOS_DEBUG, "Video Clock Not ok, we are still fucked.\n"); + return -ERR_VIDEO_CLOCK_BAD; + } + /* Set to use the register calculated M/N video */ s5p_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); @@ -505,7 +522,7 @@ static int s5p_dp_hw_link_training(struct s5p_dp_device *dp, /* * Initialize DP display */ -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) +int dp_controller_init(struct s5p_dp_device *dp_device) { int ret; struct s5p_dp_device *dp = dp_device; @@ -561,15 +578,6 @@ int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms) return ret; } - /* - * This delay is T3 in the LCD timing spec (defined as >200ms). We set - * this down to 60ms since that's the approximate maximum amount of time - * it'll take a bridge to start outputting LVDS data. The delay of - * >200ms is just a conservative value to avoid turning on the backlight - * when there's random LCD data on the screen. Shaving 140ms off the - * boot is an acceptable trade-off. - */ - *wait_ms = 60; return 0; } diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5-common/s5p-dp-core.h index 2988d5d..4df848d 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h +++ b/src/cpu/samsung/exynos5-common/s5p-dp-core.h @@ -252,6 +252,6 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp); /* startup and init */ struct exynos5_fimd_panel; void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd); -int dp_controller_init(struct s5p_dp_device *dp_device, unsigned *wait_ms); +int dp_controller_init(struct s5p_dp_device *dp_device); int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase); #endif /* _S5P_DP_CORE_H */ diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c index 60e1398..0c6b214 100644 --- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c +++ b/src/cpu/samsung/exynos5-common/s5p-dp-reg.c @@ -184,12 +184,13 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) while (!(reg & RPLY_RECEIV)) reg = readl(&base->dp_int_sta); + printk(BIOS_DEBUG, "%s: checkpoint 1, dp_int_sta: 0x%08x\n", __func__, reg); /* Clear interrupt source for AUX CH command reply */ writel(RPLY_RECEIV, &base->dp_int_sta); /* Clear interrupt source for AUX CH access error */ reg = readl(&base->dp_int_sta); - printk(BIOS_DEBUG, "%s: dp_int_sta: 0x%02x\n", __func__, reg); + printk(BIOS_DEBUG, "%s: checkpoint 2, dp_int_sta: 0x%08x\n", __func__, reg); if (reg & AUX_ERR) { writel(AUX_ERR, &base->dp_int_sta); return -1; @@ -203,6 +204,8 @@ int s5p_dp_start_aux_transaction(struct s5p_dp_device *dp) return -1; } + printk(BIOS_DEBUG, "%s: done, dp_int_sta: 0x%08x, aux_ch_sta: 0x%08x\n", + __func__, reg, readl(&base->aux_ch_sta)); return 0; } @@ -356,8 +359,10 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_1); - if (!(reg & DET_STA)) + if (!(reg & DET_STA)) { + printk(BIOS_DEBUG, "%s: sys_ctl_1: 0x%08x\n", __func__, reg); return -1; + } reg = readl(&base->sys_ctl_2); writel(reg, &base->sys_ctl_2); @@ -365,10 +370,12 @@ int s5p_dp_is_slave_video_stream_clock_on(struct s5p_dp_device *dp) reg = readl(&base->sys_ctl_2); if (reg & CHA_STA) { + printk(BIOS_DEBUG, "%s: sys_ctl_2: 0x%08x\n", __func__, reg); printk(BIOS_DEBUG, "Input stream clk is changing\n"); return -1; } + printk(BIOS_DEBUG, "%s: done\n", __func__); return 0; } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index ad0266b..0bb264a 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -98,8 +98,6 @@ static void exynos_dp_bridge_setup(void) gpio_set_pull(dp_rst_l, EXYNOS_GPIO_PULL_NONE); udelay(10); gpio_set_value(dp_rst_l, 1); - - udelay(90000); /* FIXME: this might be unnecessary */ } static void exynos_dp_bridge_init(void) @@ -116,19 +114,13 @@ static void exynos_dp_bridge_init(void) * roughly 50ms after PD is de-asserted. The phantom high * makes it hard for us to know when the NXP chip is up. */ - udelay(90000); /* FIXME: this might be unnecessary */ + udelay(90000); } static int exynos_dp_hotplug(void) { - int x = gpio_get_value(dp_hpd); /* Check HPD. If it's high, we're all good. */ -// if (gpio_get_value(dp_hpd)) -// return 0; - printk(BIOS_DEBUG, "%s: dp_hpd: 0x%02x\n", __func__, x); - if (x) - return 0; - return -1; + return gpio_get_value(dp_hpd) ? 0 : 1; } static void exynos_dp_reset(void) @@ -139,6 +131,7 @@ static void exynos_dp_reset(void) udelay(300 * 1000); } +#define LCD_T3_DELAY_MS 60 #define LCD_T5_DELAY_MS 10 #define LCD_T6_DELAY_MS 10 @@ -199,7 +192,6 @@ static struct video_info snow_dp_video_info = { static void mainboard_init(device_t dev) { int dp_tries; - unsigned int wait_ms; struct s5p_dp_device dp_device = { .base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE, .video_info = &snow_dp_video_info, @@ -215,20 +207,28 @@ static void mainboard_init(device_t dev) exynos_dp_bridge_setup(); for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) { - if (wait_ms) { - udelay(wait_ms); - wait_ms = 0; - } - exynos_dp_bridge_init(); if (exynos_dp_hotplug()) { exynos_dp_reset(); continue; } - if (dp_controller_init(&dp_device, &wait_ms)) + if (dp_controller_init(&dp_device)) continue; + printk(BIOS_INFO, "%s: DP controller init done, powering on " + "backlight\n", __func__); + + /* + * This delay is T3 in the LCD timing spec (defined as >200ms). We set + * this down to 60ms since that's the approximate maximum amount of time + * it'll take a bridge to start outputting LVDS data. The delay of + * >200ms is just a conservative value to avoid turning on the backlight + * when there's random LCD data on the screen. Shaving 140ms off the + * boot is an acceptable trade-off. + */ + udelay(LCD_T3_DELAY_MS * 1000); + snow_backlight_vdd(); snow_backlight_pwm(); snow_backlight_en();

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Patch set updated for coreboot: 5fb2862 Exynos5250: add a microsecond timer
by David Hendricks 12 Apr '13

12 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit 5fb28627b7971b80586594eeb5fd601c29aa039d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls microsecond() for any reason, using the result or not. From that point on, it returns microseconds from the first call. We show its use in romstage. You want it started very early. Finally, the delay.h changed having been (ironically) delayed, we create time.h and have it hold one declaration, for the microseconds prototype. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 ++-- src/cpu/samsung/exynos5250/Kconfig | 8 +++ src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 122 ++++++++++++++++++++++++++++++++ src/include/time.h | 28 ++++++++ src/mainboard/google/snow/bootblock.c | 5 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 178 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index cc67abd..a63ccd7 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -97,3 +97,11 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex default 0x4000000 + +config MCT_ADDRESS + hex + default 0x101c0000 + +config MCT_HZ + int + default 24000000 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..8342982 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +/* I would prefer not to export these for now. */ +static uint64_t timer_hz(void) +{ + return CONFIG_MCT_HZ; +} + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)CONFIG_MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + uint32_t ticks_per_microsecond = timer_hz()/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..6bd9e08 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +#if !defined( __ROMCC__) + +void timer_start(void); +u32 timer_us(void); +#endif +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..a0fe72b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -34,4 +35,8 @@ void bootblock_mainboard_init(void) console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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New patch to review for coreboot: 9bf0cf6 google/snow: enable 32KHz sleep clock
by David Hendricks 12 Apr '13

12 Apr '13

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3075 -gerrit commit 9bf0cf62bd52d8a55403161570f0753db1d7a21a Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Apr 11 12:58:25 2013 -0700 google/snow: enable 32KHz sleep clock Change-Id: I9db91826e4534b8a6eea2b13bcf7c6abd848b4e4 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index d34c379..2b3620e 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -90,6 +90,8 @@ static int setup_pmic(void) error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, CONFIG_VDD_LDO10_MV, REG_ENABLE, MAX77686_MV); + error |= max77686_enable_32khz_cp(PMIC_BUS); + if (error) printk(BIOS_CRIT, "%s: Error during PMIC setup\n", __func__);

1 0

Patch set updated for coreboot: 8b150ed Exynos5250: add a microsecond timer
by Ronald G. Minnich 12 Apr '13

12 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit 8b150ed704eb8d2a14e4e911a1ae306dede729a9 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 +++- src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clk.h | 5 ++ src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 126 ++++++++++++++++++++++++++++++++ src/include/time.h | 28 +++++++ src/mainboard/google/snow/bootblock.c | 5 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 179 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index dbddce0..4785894 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -25,6 +25,11 @@ #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/pinmux.h> + +#define MCT_ADDRESS 0x101c0000 + +#define MCT_HZ 24000000 + /* * Set mshci controller instances clock drivder * diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..047cb65 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,126 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> +#include "clk.h" + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +/* I would prefer not to export these for now. + * I think it's best if we keep the hardware + * API limited to timer_start and timer_us. + */ +static uint64_t timer_hz(void) +{ + return MCT_HZ; +} + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + uint32_t ticks_per_microsecond = timer_hz()/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..6bd9e08 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +#if !defined( __ROMCC__) + +void timer_start(void); +u32 timer_us(void); +#endif +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..a0fe72b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -34,4 +35,8 @@ void bootblock_mainboard_init(void) console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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Patch set updated for coreboot: 991bdff Exynos5250: add a microsecond timer
by Ronald G. Minnich 12 Apr '13

12 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit 991bdff73cb762cdbefa4c3b8dc5189b9905f75e Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 +++- src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clk.h | 5 ++ src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 125 ++++++++++++++++++++++++++++++++ src/include/time.h | 28 +++++++ src/mainboard/google/snow/bootblock.c | 5 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 178 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h index dbddce0..bf59d6f 100644 --- a/src/cpu/samsung/exynos5250/clk.h +++ b/src/cpu/samsung/exynos5250/clk.h @@ -25,6 +25,11 @@ #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/pinmux.h> + +#define MCT_ADDRESS 0x101c0000 + +#defein MCT_HZ 24000000 + /* * Set mshci controller instances clock drivder * diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..c91f225 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,125 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +/* I would prefer not to export these for now. + * I think it's best if we keep the hardware + * API limited to timer_start and timer_us. + */ +static uint64_t timer_hz(void) +{ + return MCT_HZ; +} + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + uint32_t ticks_per_microsecond = timer_hz()/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..6bd9e08 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +#if !defined( __ROMCC__) + +void timer_start(void); +u32 timer_us(void); +#endif +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..a0fe72b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -34,4 +35,8 @@ void bootblock_mainboard_init(void) console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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Patch merged into coreboot/master: 2c8f81b cbfstool: cbfs-mkstage.c: Free `buffer` on error path
by gerrit＠coreboot.org 12 Apr '13

12 Apr '13

the following patch was just integrated into master: commit 2c8f81b57b20c14edf4b77d3f5dcd2bcce717180 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Apr 11 10:45:11 2013 +0200 cbfstool: cbfs-mkstage.c: Free `buffer` on error path Cppcheck warns about a memory leak, present since adding romtool, which was renamed to cbfstool, in commit 5d01ec0f. $ cppcheck --version Cppcheck 1.59 […] [cbfs-mkstage.c:170]: (error) Memory leak: buffer […] Indeed the memory pointed to by `buffer` is not freed on the error path, so add `free(buffer)` to fix this. Change-Id: I6cbf82479027747c800c5fe847f20b779e261ef4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3069 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Fri Apr 12 13:40:17 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 12 20:22:38 2013, giving +2 See http://review.coreboot.org/3069 for details. -gerrit

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Patch merged into coreboot/master: e76d8d7 acpica: update URL
by gerrit＠coreboot.org 12 Apr '13

12 Apr '13

the following patch was just integrated into master: commit e76d8d7ced79d618291f6f0b1331d60a86855f2e Author: Idwer Vollering <vidwer(a)gmail.com> Date: Thu Apr 11 12:01:19 2013 +0200 acpica: update URL The URL to acpica-unix-20121114 has changed, update the URL. Change-Id: I1c8c228094f19455af3682f36f1990586fe3934c Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-on: http://review.coreboot.org/3070 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Build-Tested: build bot (Jenkins) at Thu Apr 11 12:32:27 2013, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Apr 12 20:15:51 2013, giving +2 See http://review.coreboot.org/3070 for details. -gerrit

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Patch set updated for coreboot: 242ff74 Exynos5250: add a microsecond timer
by Ronald G. Minnich 12 Apr '13

12 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit 242ff74d3f9633d4413c3f9bea1544d199e42caf Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds since the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h change having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 ++-- src/cpu/samsung/exynos5250/Kconfig | 8 +++ src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 122 ++++++++++++++++++++++++++++++++ src/include/time.h | 28 ++++++++ src/mainboard/google/snow/bootblock.c | 5 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 178 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index cc67abd..a63ccd7 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -97,3 +97,11 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex default 0x4000000 + +config MCT_ADDRESS + hex + default 0x101c0000 + +config MCT_HZ + int + default 24000000 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..8342982 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +/* I would prefer not to export these for now. */ +static uint64_t timer_hz(void) +{ + return CONFIG_MCT_HZ; +} + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)CONFIG_MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + uint32_t ticks_per_microsecond = timer_hz()/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..6bd9e08 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +#if !defined( __ROMCC__) + +void timer_start(void); +u32 timer_us(void); +#endif +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..a0fe72b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -34,4 +35,8 @@ void bootblock_mainboard_init(void) console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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Patch set updated for coreboot: 14c710f Exynos5250: add a microsecond timer
by Ronald G. Minnich 12 Apr '13

12 Apr '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3073 -gerrit commit 14c710fda83bde020ac04ade2db95f0599179ae3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Apr 11 15:03:28 2013 -0700 Exynos5250: add a microsecond timer Add a microsecond timer, its declaration, the function to start it, and its usage. To start it, one calls timer_start(). From that point on, one can call timer_us() to find microseconds from the timer was started. We show its use in the bootblock. You want it started very early. Finally, the delay.h changed having been (ironically) delayed, we create time.h and have it hold one declaration, for the timer_us() and timer_start() prototype. We feel that these two functions should become the hardware specific functions, allowing us to finally move udelay() into src/lib where it belongs. Change-Id: I19cbc2bb0089a3de88cfb94276266af38b9363c5 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/lib/Makefile.inc | 2 - src/cpu/samsung/exynos5-common/timer.c | 15 ++-- src/cpu/samsung/exynos5250/Kconfig | 8 +++ src/cpu/samsung/exynos5250/Makefile.inc | 4 +- src/cpu/samsung/exynos5250/clock_init.c | 13 ---- src/cpu/samsung/exynos5250/mct.c | 122 ++++++++++++++++++++++++++++++++ src/include/time.h | 28 ++++++++ src/mainboard/google/snow/bootblock.c | 5 ++ src/mainboard/google/snow/romstage.c | 1 + 9 files changed, 178 insertions(+), 20 deletions(-) diff --git a/src/arch/armv7/lib/Makefile.inc b/src/arch/armv7/lib/Makefile.inc index 56a1bb7..0cb5737 100644 --- a/src/arch/armv7/lib/Makefile.inc +++ b/src/arch/armv7/lib/Makefile.inc @@ -1,6 +1,5 @@ #FIXME: cache_v7 and cache-cp15 will go away eventually -bootblock-y += syslib.c bootblock-$(CONFIG_EARLY_CONSOLE) += early_console.c bootblock-y += cache.c @@ -13,7 +12,6 @@ ramstage-y += div0.c #ramstage-y += interrupts.c #ramstage-y += memcpy.S #ramstage-y += memset.S -ramstage-y += syslib.c ramstage-y += cache.c ramstage-y += mmu.c diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5-common/timer.c index 6cd5f5d..ca15501 100644 --- a/src/cpu/samsung/exynos5-common/timer.c +++ b/src/cpu/samsung/exynos5-common/timer.c @@ -25,6 +25,8 @@ #include <common.h> #include <arch/io.h> +#include <time.h> +#include <console/console.h> #include <cpu/samsung/exynos5-common/pwm.h> #include <cpu/samsung/exynos5-common/clk.h> #include <cpu/samsung/exynos5250/cpu.h> @@ -117,12 +119,17 @@ unsigned long timer_get_us(void) } /* delay x useconds */ -void __udelay(unsigned long usec) +void udelay(unsigned long usec) { - unsigned long count_value; + unsigned long start; - count_value = timer_get_us_down(); - while ((int)(count_value - timer_get_us_down()) < (int)usec) + start = timer_us(); + if ((start + usec) < start){ + printk(BIOS_EMERG, "udelay: %08lx is impossibly large\n", + usec); + usec = 1000000; + } + while ((timer_us() - start) < usec) ; } diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index cc67abd..a63ccd7 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -97,3 +97,11 @@ config SYS_TEXT_BASE config COREBOOT_TABLES_SIZE hex default 0x4000000 + +config MCT_ADDRESS + hex + default 0x101c0000 + +config MCT_HZ + int + default 24000000 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 74bc871..1046b8b 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,7 +3,7 @@ # image outside of CBFS #INTERMEDIATE += exynos5250_add_bl1 -bootblock-y += pinmux.c +bootblock-y += pinmux.c mct.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c @@ -16,6 +16,7 @@ romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. romstage-y += dmc_common.c romstage-y += dmc_init_ddr3.c romstage-y += power.c +romstage-y += mct.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c @@ -27,6 +28,7 @@ ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c ramstage-y += cpu.c +ramstage-y += mct.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c index 618fdb6..c8479de 100644 --- a/src/cpu/samsung/exynos5250/clock_init.c +++ b/src/cpu/samsung/exynos5250/clock_init.c @@ -452,16 +452,3 @@ void clock_init_dp_clock(void) setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1); } -/* - * This is a custom implementation for the udelay(), as we do not the timer - * initialise during the SPL boot. We are assuming the cpu takes 3 instruction - * pre cycle. This is based on the implementation of sdelay() function. - */ -void udelay(unsigned usec) -{ - unsigned long count; - - /* TODO(alim.akhtar(a)samsung.com): Comment on why divided by 30000000 */ - count = usec * (get_pll_clk(APLL) / (3 * 10000000)); - sdelay(count); -} diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c new file mode 100644 index 0000000..8342982 --- /dev/null +++ b/src/cpu/samsung/exynos5250/mct.c @@ -0,0 +1,122 @@ +/* + * Copyright 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <arch/io.h> +#include <stdint.h> +#include <time.h> + +struct __attribute__((packed)) mct_regs +{ + uint32_t mct_cfg; + uint8_t reserved0[0xfc]; + uint32_t g_cnt_l; + uint32_t g_cnt_u; + uint8_t reserved1[0x8]; + uint32_t g_cnt_wstat; + uint8_t reserved2[0xec]; + uint32_t g_comp0_l; + uint32_t g_comp0_u; + uint32_t g_comp0_addr_incr; + uint8_t reserved3[0x4]; + uint32_t g_comp1_l; + uint32_t g_comp1_u; + uint32_t g_comp1_addr_incr; + uint8_t reserved4[0x4]; + uint32_t g_comp2_l; + uint32_t g_comp2_u; + uint32_t g_comp2_addr_incr; + uint8_t reserved5[0x4]; + uint32_t g_comp3_l; + uint32_t g_comp3_u; + uint32_t g_comp3_addr_incr; + uint8_t reserved6[0x4]; + uint32_t g_tcon; + uint32_t g_int_cstat; + uint32_t g_int_enb; + uint32_t g_wstat; + uint8_t reserved7[0xb0]; + uint32_t l0_tcntb; + uint32_t l0_tcnto; + uint32_t l0_icntb; + uint32_t l0_icnto; + uint32_t l0_frcntb; + uint32_t l0_frcnto; + uint8_t reserved8[0x8]; + uint32_t l0_tcon; + uint8_t reserved9[0xc]; + uint32_t l0_int_cstat; + uint32_t l0_int_enb; + uint8_t reserved10[0x8]; + uint32_t l0_wstat; + uint8_t reserved11[0xbc]; + uint32_t l1_tcntb; + uint32_t l1_tcnto; + uint32_t l1_icntb; + uint32_t l1_icnto; + uint32_t l1_frcntb; + uint32_t l1_frcnto; + uint8_t reserved12[0x8]; + uint32_t l1_tcon; + uint8_t reserved13[0xc]; + uint32_t l1_int_cstat; + uint32_t l1_int_enb; + uint8_t reserved14[0x8]; + uint32_t l1_wstat; +}; + +/* I would prefer not to export these for now. */ +static uint64_t timer_hz(void) +{ + return CONFIG_MCT_HZ; +} + +static int enabled = 0; +static struct mct_regs *const mct = + (struct mct_regs *)CONFIG_MCT_ADDRESS; + +static uint64_t timer_raw_value(void) +{ + if (!enabled) { + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; + } + + uint64_t upper = readl(&mct->g_cnt_u); + uint64_t lower = readl(&mct->g_cnt_l); + + return (upper << 32) | lower; +} + +void timer_start(void) +{ + writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon); + enabled = 1; +} + +u32 timer_us(void) +{ + uint64_t raw = timer_raw_value(); + uint32_t ticks_per_microsecond = timer_hz()/1000000; + uint32_t usec = raw / ticks_per_microsecond; + return usec; +} + diff --git a/src/include/time.h b/src/include/time.h new file mode 100644 index 0000000..6bd9e08 --- /dev/null +++ b/src/include/time.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#ifndef TIME_H +#define TIME_H + +#if !defined( __ROMCC__) + +void timer_start(void); +u32 timer_us(void); +#endif +#endif /* TIME_H */ diff --git a/src/mainboard/google/snow/bootblock.c b/src/mainboard/google/snow/bootblock.c index 2df0e4e..a0fe72b 100644 --- a/src/mainboard/google/snow/bootblock.c +++ b/src/mainboard/google/snow/bootblock.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <cbfs.h> #include <uart.h> +#include <time.h> #include <console/console.h> #include <cpu/samsung/exynos5250/periph.h> #include <cpu/samsung/exynos5250/pinmux.h> @@ -34,4 +35,8 @@ void bootblock_mainboard_init(void) console_init(); printk(BIOS_INFO, "\n\n\n%s: UART initialized\n", __func__); #endif + /* kick off the microsecond timer. We want to do this as early + * as we can. + */ + timer_start(); } diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7a26ed9..dda4e7c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -36,6 +36,7 @@ #include <cpu/samsung/exynos5250/clock_init.h> #include <console/console.h> #include <arch/stages.h> +#include <time.h> #include <drivers/maxim/max77686/max77686.h> #include <device/i2c.h>

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coreboot-gerrit April 2013