coreboot-gerrit April 2013

coreboot-gerrit@coreboot.org

1 participants
506 discussions

New patch to review for coreboot: 70e2b28 libpayload: storage.c: Fix typo in st*orage in comment
by Paul Menzel 11 Apr '13

11 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3071 -gerrit commit 70e2b28e923744cdad052ae6f21a3025196bdfc6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Apr 11 15:19:04 2013 +0200 libpayload: storage.c: Fix typo in st*orage in comment Reading commit »libpayload: New AHCI, ATA and ATAPI drivers« (1f6bd94f) [1], the spelling error was found and is now fixed. [1] http://review.coreboot.org/1622 Change-Id: Id418bcb99c1a9a400a49fc04078e465bd0908074 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- payloads/libpayload/drivers/storage/storage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index f623077..ae60309 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -106,7 +106,7 @@ ssize_t storage_read_blocks512(const size_t dev_num, * Initializes storage controllers * * This function should be called once at startup to bring up supported - * strorage controllers. + * storage controllers. */ void storage_initialize(void) {

1 0

New patch to review for coreboot: aa80e57 acpica: update URL
by Idwer Vollering 11 Apr '13

11 Apr '13

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3070 -gerrit commit aa80e577b6e92753b37fdf078d9f8fb5b5f7ad01 Author: Idwer Vollering <vidwer(a)gmail.com> Date: Thu Apr 11 12:01:19 2013 +0200 acpica: update URL The URL to acpica-unix-20121114 has changed, update the URL. Change-Id: I1c8c228094f19455af3682f36f1990586fe3934c Signed-off-by: Idwer Vollering <vidwer(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 34518a8..be8d1f2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -49,7 +49,7 @@ LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" BINUTILS_ARCHIVE="http://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.gz" GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.bz2" -IASL_ARCHIVE="http://www.acpica.org/download/acpica-unix-${IASL_VERSION}.tar.gz" +IASL_ARCHIVE="http://www.acpica.org/sites/acpica/files/acpica-unix-${IASL_VERSION}.tar.gz" PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}…" EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.t…"

1 0

New patch to review for coreboot: cc6ddb6 cbfstool: cbfs-mkstage.c: Free `buffer` on error path
by Paul Menzel 11 Apr '13

11 Apr '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3069 -gerrit commit cc6ddb6a99c0ed161089f5c4de0eadc9142b8966 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu Apr 11 10:45:11 2013 +0200 cbfstool: cbfs-mkstage.c: Free `buffer` on error path Cppcheck warns about a memory leak, present since adding romtool, the former name of cbfstool, in commit 5d01ec0f. $ cppcheck --version Cppcheck 1.59 […] [cbfs-mkstage.c:170]: (error) Memory leak: buffer […] Indeed the memory pointed to by `buffer` is not free’d on the error path, so add `free(buffer)` to fix this. Change-Id: I6cbf82479027747c800c5fe847f20b779e261ef4 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/cbfstool/cbfs-mkstage.c | 1 + 1 file changed, 1 insertion(+) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 4008367..dfc93c2 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -167,6 +167,7 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, if (buffer_create(output, sizeof(*stage) + data_end - data_start, input->name) != 0) { ERROR("Unable to allocate memory: %m\n"); + free(buffer); return -1; } memset(output->data, 0, output->size);

1 0

New patch to review for coreboot: b8c3b63 ec/google: Isolate EC bus protocol implementation.
by Hung-Te Lin 11 Apr '13

11 Apr '13

Hung-Te Lin (hungte(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3068 -gerrit commit b8c3b636a71f0f4d9c9db908630a0dee8cab6bff Author: Hung-Te Lin <hungte(a)chromium.org> Date: Thu Apr 11 15:58:12 2013 +0800 ec/google: Isolate EC bus protocol implementation. The Chrome EC can be connected by different types of bus like LPC / I2C / SPI, and the current implementation is only for LPC. To support other types, we must first isolate the LPC protocol stuff and add configuration variable (EC_GOOGLE_CHROMEEC_LPC) to specify bus type. Verified by building google/link (with chromeec) configuration successfully. Change-Id: Ib2920d8d935bcc77a5394e818f69e9265e26e8a0 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- src/ec/google/chromeec/Kconfig | 7 ++ src/ec/google/chromeec/Makefile.inc | 3 + src/ec/google/chromeec/ec.c | 186 --------------------------------- src/ec/google/chromeec/ec.h | 13 +++ src/ec/google/chromeec/ec_lpc.c | 201 ++++++++++++++++++++++++++++++++++++ 5 files changed, 224 insertions(+), 186 deletions(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index b8d3444..ce96da7 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -9,3 +9,10 @@ config EC_GOOGLE_API_ROOT default "/usr/include" help Path to the ec API file (ec/ec_commands.h). + +config EC_GOOGLE_CHROMEEC_LPC + depends on EC_GOOGLE_CHROMEEC + bool + default y if ARCH_X86 + help + Google Chrome EC via LPC bus. diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 93ad333..5fb258f 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,5 +1,8 @@ ramstage-y += ec.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c smm-y += ec.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c romstage-y += ec.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT)) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5ae0178..d830529 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <arch/io.h> #include <delay.h> -#include <device/device.h> #include <device/pnp.h> #ifndef __PRE_RAM__ #include <elog.h> @@ -35,172 +34,6 @@ #include "ec_commands.h" #include <vendorcode/google/chromeos/chromeos.h> -/* an internal API to send a command to the EC and wait for response. */ -struct chromeec_command { - u8 cmd_code; /* command code in, status out */ - u8 cmd_version; /* command version */ - const void* cmd_data_in; /* command data, if any */ - void* cmd_data_out; /* command response, if any */ - u16 cmd_size_in; /* size of command data */ - u16 cmd_size_out; /* expected size of command response in, - * actual received size out */ -}; - -static int google_chromeec_wait_ready(u16 port) -{ - u8 ec_status = inb(port); - u32 time_count = 0; - - /* - * One second is more than plenty for any EC operation to complete - * (and the bus accessing/code execution) overhead will make the - * timeout even longer. - */ -#define MAX_EC_TIMEOUT_US 1000000 - - while (ec_status & - (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) { - udelay(1); - if (time_count++ == MAX_EC_TIMEOUT_US) - return -1; - ec_status = inb(port); - } - return 0; -} - -static int google_chromeec_cmd_args_supported(void) -{ - if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) == 'E' && - inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) == 'C' && - (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS) & - EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED)) - return 1; - - return 0; -} - -static int google_chromeec_command_old(struct chromeec_command *cec_command) -{ - int i; - - if (cec_command->cmd_version) { - printk(BIOS_ERR, "Invalid version for command protocol!\n"); - return 1; - } - - if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { - printk(BIOS_ERR, "Timeout waiting for EC ready!\n"); - return 1; - } - - /* Copy command data, if any. */ - for (i = 0; i < cec_command->cmd_size_in; i++) - outb(((char*)cec_command->cmd_data_in)[i], - EC_LPC_ADDR_OLD_PARAM + i); - - /* Issue the command. */ - outb(cec_command->cmd_code, EC_LPC_ADDR_HOST_CMD); - - if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { - printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", - cec_command->cmd_code); - return 1; - } - - for (i = 0; i < cec_command->cmd_size_out; i++) - ((char*)cec_command->cmd_data_out)[i] = - inb(EC_LPC_ADDR_OLD_PARAM + i); - cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA); - return 0; -} - -static int google_chromeec_command(struct chromeec_command *cec_command) -{ - struct ec_lpc_host_args args; - const u8 *d; - u8 *dout; - u8 cmd_code = cec_command->cmd_code; - int csum; - int i; - - /* Fall back to old command protocol if necessary */ - if (!google_chromeec_cmd_args_supported()) - return google_chromeec_command_old(cec_command); - - /* Fill in args */ - args.flags = EC_HOST_ARGS_FLAG_FROM_HOST; - args.command_version = cec_command->cmd_version; - args.data_size = cec_command->cmd_size_in; - - /* Initialize checksum */ - csum = cmd_code + args.flags + args.command_version + args.data_size; - - /* Write data and update checksum */ - for (i = 0, d = (const u8 *)cec_command->cmd_data_in; - i < cec_command->cmd_size_in; i++, d++) { - outb(*d, EC_LPC_ADDR_HOST_PARAM + i); - csum += *d; - } - - /* Finalize checksum and write args */ - args.checksum = (u8)csum; - for (i = 0, d = (const u8 *)&args; i < sizeof(args); i++, d++) - outb(*d, EC_LPC_ADDR_HOST_ARGS + i); - - - /* Issue the command */ - outb(cmd_code, EC_LPC_ADDR_HOST_CMD); - - if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { - printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", - cec_command->cmd_code); - return 1; - } - - /* Check result */ - cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA); - if (cec_command->cmd_code) - return 1; - - /* Read back args */ - for (i = 0, dout = (u8 *)&args; i < sizeof(args); i++, dout++) - *dout = inb(EC_LPC_ADDR_HOST_ARGS + i); - - /* - * If EC didn't modify args flags, then somehow we sent a new-style - * command to an old EC, which means it would have read its params - * from the wrong place. - */ - if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) { - printk(BIOS_ERR, "EC protocol mismatch\n"); - return 1; - } - - if (args.data_size > cec_command->cmd_size_out) { - printk(BIOS_ERR, "EC returned too much data\n"); - return 1; - } - cec_command->cmd_size_out = args.data_size; - - /* Start calculating response checksum */ - csum = cmd_code + args.flags + args.command_version + args.data_size; - - /* Read data, if any */ - for (i = 0, dout = (u8 *)cec_command->cmd_data_out; - i < args.data_size; i++, dout++) { - *dout = inb(EC_LPC_ADDR_HOST_PARAM + i); - csum += *dout; - } - - /* Verify checksum */ - if (args.checksum != (u8)csum) { - printk(BIOS_ERR, "EC response has invalid checksum\n"); - return 1; - } - - return 0; -} - int google_chromeec_kbbacklight(int percent) { struct chromeec_command cec_cmd; @@ -344,25 +177,6 @@ void google_chromeec_log_events(u32 mask) #endif } -u8 google_chromeec_get_event(void) -{ - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { - printk(BIOS_ERR, "Timeout waiting for EC ready!\n"); - return 1; - } - - /* Issue the ACPI query-event command */ - outb(EC_CMD_ACPI_QUERY_EVENT, EC_LPC_ADDR_ACPI_CMD); - - if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { - printk(BIOS_ERR, "Timeout waiting for EC QUERY_EVENT!\n"); - return 0; - } - - /* Event (or 0 if none) is returned directly in the data byte */ - return inb(EC_LPC_ADDR_ACPI_DATA); -} - u16 google_chromeec_get_board_version(void) { struct chromeec_command cmd; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index f056d26..c78560f 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -46,4 +46,17 @@ enum usb_charge_mode { }; int google_chromeec_set_usb_charge_mode(u8 port_id, enum usb_charge_mode mode); +/* internal structure to send a command to the EC and wait for response. */ +struct chromeec_command { + uint8_t cmd_code; /* command code in, status out */ + uint8_t cmd_version; /* command version */ + const void* cmd_data_in; /* command data, if any */ + void* cmd_data_out; /* command response, if any */ + uint16_t cmd_size_in; /* size of command data */ + uint16_t cmd_size_out; /* expected size of command response in, + * actual received size out */ +}; + +int google_chromeec_command(struct chromeec_command *cec_command); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c new file mode 100644 index 0000000..6443592 --- /dev/null +++ b/src/ec/google/chromeec/ec_lpc.c @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <console/console.h> +#include <arch/io.h> +#include <delay.h> +#include "ec.h" +#include "ec_commands.h" + +static int google_chromeec_wait_ready(u16 port) +{ + u8 ec_status = inb(port); + u32 time_count = 0; + + /* + * One second is more than plenty for any EC operation to complete + * (and the bus accessing/code execution) overhead will make the + * timeout even longer. + */ +#define MAX_EC_TIMEOUT_US 1000000 + + while (ec_status & + (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) { + udelay(1); + if (time_count++ == MAX_EC_TIMEOUT_US) + return -1; + ec_status = inb(port); + } + return 0; +} + +static int google_chromeec_cmd_args_supported(void) +{ + if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) == 'E' && + inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) == 'C' && + (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS) & + EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED)) + return 1; + + return 0; +} + +static int google_chromeec_command_old(struct chromeec_command *cec_command) +{ + int i; + + if (cec_command->cmd_version) { + printk(BIOS_ERR, "Invalid version for command protocol!\n"); + return 1; + } + + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC ready!\n"); + return 1; + } + + /* Copy command data, if any. */ + for (i = 0; i < cec_command->cmd_size_in; i++) + outb(((char*)cec_command->cmd_data_in)[i], + EC_LPC_ADDR_OLD_PARAM + i); + + /* Issue the command. */ + outb(cec_command->cmd_code, EC_LPC_ADDR_HOST_CMD); + + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", + cec_command->cmd_code); + return 1; + } + + for (i = 0; i < cec_command->cmd_size_out; i++) + ((char*)cec_command->cmd_data_out)[i] = + inb(EC_LPC_ADDR_OLD_PARAM + i); + cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA); + return 0; +} + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + struct ec_lpc_host_args args; + const u8 *d; + u8 *dout; + u8 cmd_code = cec_command->cmd_code; + int csum; + int i; + + /* Fall back to old command protocol if necessary */ + if (!google_chromeec_cmd_args_supported()) + return google_chromeec_command_old(cec_command); + + /* Fill in args */ + args.flags = EC_HOST_ARGS_FLAG_FROM_HOST; + args.command_version = cec_command->cmd_version; + args.data_size = cec_command->cmd_size_in; + + /* Initialize checksum */ + csum = cmd_code + args.flags + args.command_version + args.data_size; + + /* Write data and update checksum */ + for (i = 0, d = (const u8 *)cec_command->cmd_data_in; + i < cec_command->cmd_size_in; i++, d++) { + outb(*d, EC_LPC_ADDR_HOST_PARAM + i); + csum += *d; + } + + /* Finalize checksum and write args */ + args.checksum = (u8)csum; + for (i = 0, d = (const u8 *)&args; i < sizeof(args); i++, d++) + outb(*d, EC_LPC_ADDR_HOST_ARGS + i); + + + /* Issue the command */ + outb(cmd_code, EC_LPC_ADDR_HOST_CMD); + + if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", + cec_command->cmd_code); + return 1; + } + + /* Check result */ + cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA); + if (cec_command->cmd_code) + return 1; + + /* Read back args */ + for (i = 0, dout = (u8 *)&args; i < sizeof(args); i++, dout++) + *dout = inb(EC_LPC_ADDR_HOST_ARGS + i); + + /* + * If EC didn't modify args flags, then somehow we sent a new-style + * command to an old EC, which means it would have read its params + * from the wrong place. + */ + if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) { + printk(BIOS_ERR, "EC protocol mismatch\n"); + return 1; + } + + if (args.data_size > cec_command->cmd_size_out) { + printk(BIOS_ERR, "EC returned too much data\n"); + return 1; + } + cec_command->cmd_size_out = args.data_size; + + /* Start calculating response checksum */ + csum = cmd_code + args.flags + args.command_version + args.data_size; + + /* Read data, if any */ + for (i = 0, dout = (u8 *)cec_command->cmd_data_out; + i < args.data_size; i++, dout++) { + *dout = inb(EC_LPC_ADDR_HOST_PARAM + i); + csum += *dout; + } + + /* Verify checksum */ + if (args.checksum != (u8)csum) { + printk(BIOS_ERR, "EC response has invalid checksum\n"); + return 1; + } + + return 0; +} + +#ifndef __PRE_RAM__ +u8 google_chromeec_get_event(void) +{ + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC ready!\n"); + return 1; + } + + /* Issue the ACPI query-event command */ + outb(EC_CMD_ACPI_QUERY_EVENT, EC_LPC_ADDR_ACPI_CMD); + + if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) { + printk(BIOS_ERR, "Timeout waiting for EC QUERY_EVENT!\n"); + return 0; + } + + /* Event (or 0 if none) is returned directly in the data byte */ + return inb(EC_LPC_ADDR_ACPI_DATA); +} +#endif

1 0

Patch merged into coreboot/master: 1a5c9cd Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage.
by gerrit＠coreboot.org 11 Apr '13

11 Apr '13

the following patch was just integrated into master: commit 1a5c9cd33b6f08f80d574acaca611550ae596841 Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed Apr 10 14:34:57 2013 -0700 Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage. We need these to be inputs so they can be read when populating the coreboot tables. It seems like a good idea to do this early to ensure that the input gate capacitance has had a chance to charge, and if we decide to use actually use that information during the ROM stage to do earlier RW firmware selection. It is not guarded by a ChromeOS config variable because those lines are always intended to be input GPIOs, regardless of whether we're running ChromeOS or not. Change-Id: Id76008931b5081253737c6676980a1bdb476ac09 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3067 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Apr 11 04:09:29 2013, giving +1 Reviewed-By: Gabe Black <gabeblack(a)chromium.org> at Thu Apr 11 04:13:43 2013, giving +2 See http://review.coreboot.org/3067 for details. -gerrit

1 0

Patch merged into coreboot/master: fe3b024 Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number.
by gerrit＠coreboot.org 11 Apr '13

11 Apr '13

the following patch was just integrated into master: commit fe3b024a44451b2f11d497ba6e2715fa6d6539a7 Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed Apr 10 14:39:09 2013 -0700 Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number. Change-Id: I34097f878291367b28962048190e11ccaacfc514 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3066 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Apr 11 03:47:38 2013, giving +1 Reviewed-By: Gabe Black <gabeblack(a)chromium.org> at Thu Apr 11 04:13:24 2013, giving +2 See http://review.coreboot.org/3066 for details. -gerrit

1 0

Patch merged into coreboot/master: 514f202 ARM: Unmask aborts very early in the bootblock.
by gerrit＠coreboot.org 11 Apr '13

11 Apr '13

the following patch was just integrated into master: commit 514f20293957666d10f1ae3f946dc6f94d635364 Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed Apr 10 14:32:56 2013 -0700 ARM: Unmask aborts very early in the bootblock. It's better to recognize aborts when they occur than to mask them to discover them later without knowing where they actually came from. Change-Id: Ic8f5321415f411afac94b5ef9dd440790df6d82c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-on: http://review.coreboot.org/3065 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Thu Apr 11 03:25:05 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Apr 11 03:16:27 2013, giving +2 See http://review.coreboot.org/3065 for details. -gerrit

1 0

Patch set updated for coreboot: 8faff7a Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage.
by Gabe Black 11 Apr '13

11 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3067 -gerrit commit 8faff7a9569f70f7f6311cb38ca4ce204eb384f1 Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed Apr 10 14:34:57 2013 -0700 Snow: Set up the ChromeOS GPIOs as inputs during the ROM stage. We need these to be inputs so they can be read when populating the coreboot tables. It seems like a good idea to do this early to ensure that the input gate capacitance has had a chance to charge, and if we decide to use actually use that information during the ROM stage to do earlier RW firmware selection. It is not guarded by a ChromeOS config variable because those lines are always intended to be input GPIOs, regardless of whether we're running ChromeOS or not. Change-Id: Id76008931b5081253737c6676980a1bdb476ac09 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/romstage.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index d34c379..7a26ed9 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -27,6 +27,7 @@ #include <arch/gpio.h> #include <cpu/samsung/exynos5-common/i2c.h> #include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/cpu.h> #include <cpu/samsung/exynos5250/dmc.h> #include <cpu/samsung/exynos5250/gpio.h> #include <cpu/samsung/exynos5250/setup.h> @@ -118,6 +119,31 @@ static void graphics(void) exynos_pinmux_config(PERIPH_ID_DPHPD, 0); } +static void chromeos_gpios(void) +{ + struct exynos5_gpio_part1 *gpio_pt1; + struct exynos5_gpio_part2 *gpio_pt2; + + enum { + WP_GPIO = 6, + FORCE_RECOVERY_MODE = 0, + LID_OPEN = 5 + }; + + gpio_pt1 = (struct exynos5_gpio_part1 *)EXYNOS5_GPIO_PART1_BASE; + gpio_pt2 = (struct exynos5_gpio_part2 *)EXYNOS5_GPIO_PART2_BASE; + + s5p_gpio_direction_input(&gpio_pt1->d1, WP_GPIO); + s5p_gpio_set_pull(&gpio_pt1->d1, WP_GPIO, EXYNOS_GPIO_PULL_NONE); + + s5p_gpio_direction_input(&gpio_pt1->y1, FORCE_RECOVERY_MODE); + s5p_gpio_set_pull(&gpio_pt1->y1, FORCE_RECOVERY_MODE, + EXYNOS_GPIO_PULL_NONE); + + s5p_gpio_direction_input(&gpio_pt2->x3, LID_OPEN); + s5p_gpio_set_pull(&gpio_pt2->x3, LID_OPEN, EXYNOS_GPIO_PULL_NONE); +} + void main(void) { struct mem_timings *mem; @@ -161,6 +187,8 @@ void main(void) initialize_s5p_mshc(); + chromeos_gpios(); + graphics(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");

1 0

Patch set updated for coreboot: 1940b3d Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number.
by Gabe Black 11 Apr '13

11 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3066 -gerrit commit 1940b3d8c77960ead5ca55982e12efba4d65c4aa Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed Apr 10 14:39:09 2013 -0700 Snow: Fix the recovery GPIO polarity, and lid GPIO polarity and number. Change-Id: I34097f878291367b28962048190e11ccaacfc514 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/snow/chromeos.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index d29aa2a..015b71e 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -34,7 +34,7 @@ #define DEVMODE_GPIO 54 #define FORCE_RECOVERY_MODE 0 #define FORCE_DEVELOPER_MODE 0 -#define LID_OPEN 3 +#define LID_OPEN 5 #define POWER_BUTTON 3 #include <boot/coreboot_tables.h> @@ -59,15 +59,15 @@ void fill_lb_gpios(struct lb_gpios *gpios) strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH); - /* Recovery: active high */ + /* Recovery: active low */ gpios->gpios[1].port = EXYNOS5_GPY1; - gpios->gpios[1].polarity = ACTIVE_HIGH; + gpios->gpios[1].polarity = ACTIVE_LOW; gpios->gpios[1].value = s5p_gpio_get_value(&gpio_pt1->y1, FORCE_RECOVERY_MODE); strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); /* Lid: the "switch" comes from the EC */ gpios->gpios[2].port = EXYNOS5_GPX3; - gpios->gpios[2].polarity = ACTIVE_LOW; + gpios->gpios[2].polarity = ACTIVE_HIGH; gpios->gpios[2].value = s5p_gpio_get_value(&gpio_pt2->x3, LID_OPEN); strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);

1 0

Patch set updated for coreboot: 72683aa ARM: Unmask aborts very early in the bootblock.
by Gabe Black 11 Apr '13

11 Apr '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3065 -gerrit commit 72683aac9c82dd4535d07864b2f364d9db9bb53d Author: Gabe Black <gabeblack(a)chromium.org> Date: Wed Apr 10 14:32:56 2013 -0700 ARM: Unmask aborts very early in the bootblock. It's better to recognize aborts when they occur than to mask them to discover them later without knowing where they actually came from. Change-Id: Ic8f5321415f411afac94b5ef9dd440790df6d82c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/bootblock.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/armv7/bootblock.inc b/src/arch/armv7/bootblock.inc index faf5475..8db31b4 100644 --- a/src/arch/armv7/bootblock.inc +++ b/src/arch/armv7/bootblock.inc @@ -53,11 +53,14 @@ _cbfs_master_header: reset: /* - * set the cpu to SVC32 mode + * Set the cpu to SVC32 mode and unmask aborts. Aborts might happen + * before logging is turned on and may crash the machine, but at least + * the problem will show up near the code that causes it. */ mrs r0, cpsr bic r0, r0, #0x1f orr r0, r0, #0xd3 + bic r0, r0, #0x100 msr cpsr_cxsf,r0 /*

1 0

← Newer
1
...
29
30
31
32
33
34
35
...
51
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2013