New patch to review for coreboot: f7142b4 Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3100

-gerrit

commit f7142b464d4dfa6b0e41ea2f4139f0b9edc7ba9e
Author: Vladimir Serbinenko 
Date:   Tue Mar 12 15:53:44 2013 +0100

Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2

Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used
    `1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same
    value, instead makes it clear, that the APIC ID is 2.

[1] http://review.coreboot.org/853

Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453
    Signed-off-by: Vladimir Serbinenko 
    Signed-off-by: Paul Menzel 
---
 src/southbridge/intel/bd82x6x/lpc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index df37ddc..7bcadc9 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -52,7 +52,7 @@ static void pch_enable_apic(struct device *dev)
    pci_write_config8(dev, ACPI_CNTL, 0x80);

*ioapic_index = 0;
-	*ioapic_data = (1 << 25);
+	*ioapic_data = (2 << 24);

/* affirm full set of redirection table entries ("write once") */
    *ioapic_index = 1;
@@ -63,7 +63,7 @@ static void pch_enable_apic(struct device *dev)
    *ioapic_index = 0;
    reg32 = *ioapic_data;
    printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
-	if (reg32 != (1 << 25))
+	if (reg32 != (2 << 24))
    	die("APIC Error\n");

printk(BIOS_SPEW, "Dumping IOAPIC registers\n");